Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Common prep/pmac/chrp boot and setup code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/reboot.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/initrd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/tty.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/seq_file.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/root_dev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/console.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/memblock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/nvram.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/pgtable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <asm/prom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <asm/processor.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include <asm/setup.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #include <asm/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #include <asm/elf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #include <asm/cputable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #include <asm/bootx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #include <asm/btext.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #include <asm/machdep.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #include <asm/pmac_feature.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #include <asm/sections.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #include <asm/nvram.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #include <asm/xmon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #include <asm/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #include <asm/serial.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #include <asm/udbg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #include <asm/code-patching.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #include <asm/cpu_has_feature.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #include <asm/asm-prototypes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #include <asm/kdump.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #include <asm/feature-fixups.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #include <asm/early_ioremap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #include "setup.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define DBG(fmt...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) extern void bootx_init(unsigned long r4, unsigned long phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) int boot_cpuid_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) EXPORT_SYMBOL_GPL(boot_cpuid_phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) int smp_hw_index[NR_CPUS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) EXPORT_SYMBOL(smp_hw_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) unsigned int DMA_MODE_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) unsigned int DMA_MODE_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) EXPORT_SYMBOL(DMA_MODE_READ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) EXPORT_SYMBOL(DMA_MODE_WRITE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68)  * This is run before start_kernel(), the kernel has been relocated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69)  * and we are running with enough of the MMU enabled to have our
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70)  * proper kernel virtual addresses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72)  * We do the initial parsing of the flat device-tree and prepares
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73)  * for the MMU to be fully initialized.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) notrace void __init machine_init(u64 dt_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	struct ppc_inst *addr = (struct ppc_inst *)patch_site_addr(&patch__memset_nocache);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	struct ppc_inst insn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	/* Configure static keys first, now that we're relocated. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	setup_feature_keys();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	early_ioremap_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	/* Enable early debugging if any specified (see udbg.h) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	udbg_early_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	patch_instruction_site(&patch__memcpy_nocache, ppc_inst(PPC_INST_NOP));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	create_cond_branch(&insn, addr, branch_target(addr), 0x820000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	patch_instruction(addr, insn);	/* replace b by bne cr0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	/* Do some early initialization based on the flat device tree */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	early_init_devtree(__va(dt_ptr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	early_init_mmu();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	setup_kdump_trampoline();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* Checks "l2cr=xxxx" command-line option */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static int __init ppc_setup_l2cr(char *str)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	if (cpu_has_feature(CPU_FTR_L2CR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		unsigned long val = simple_strtoul(str, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		printk(KERN_INFO "l2cr set to %lx\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		_set_L2CR(0);		/* force invalidate by disable cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		_set_L2CR(val);		/* and enable it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) __setup("l2cr=", ppc_setup_l2cr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* Checks "l3cr=xxxx" command-line option */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static int __init ppc_setup_l3cr(char *str)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	if (cpu_has_feature(CPU_FTR_L3CR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		unsigned long val = simple_strtoul(str, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		printk(KERN_INFO "l3cr set to %lx\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		_set_L3CR(val);		/* and enable it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) __setup("l3cr=", ppc_setup_l3cr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static int __init ppc_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	/* clear the progress line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	if (ppc_md.progress)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		ppc_md.progress("             ", 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	/* call platform init */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	if (ppc_md.init != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		ppc_md.init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) arch_initcall(ppc_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static void *__init alloc_stack(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	void *ptr = memblock_alloc(THREAD_SIZE, THREAD_ALIGN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	if (!ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		panic("cannot allocate %d bytes for stack at %pS\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		      THREAD_SIZE, (void *)_RET_IP_);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	return ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) void __init irqstack_early_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	if (IS_ENABLED(CONFIG_VMAP_STACK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	/* interrupt stacks must be in lowmem, we get that for free on ppc32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	 * as the memblock is limited to lowmem by default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	for_each_possible_cpu(i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		softirq_ctx[i] = alloc_stack();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		hardirq_ctx[i] = alloc_stack();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #ifdef CONFIG_VMAP_STACK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) void *emergency_ctx[NR_CPUS] __ro_after_init = {[0] = &init_stack};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) void __init emergency_stack_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	for_each_possible_cpu(i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		emergency_ctx[i] = alloc_stack();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) void __init exc_lvl_early_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	unsigned int i, hw_cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	/* interrupt stacks must be in lowmem, we get that for free on ppc32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	 * as the memblock is limited to lowmem by MEMBLOCK_REAL_LIMIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	for_each_possible_cpu(i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		hw_cpu = get_hard_smp_processor_id(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		hw_cpu = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		critirq_ctx[hw_cpu] = alloc_stack();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #ifdef CONFIG_BOOKE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		dbgirq_ctx[hw_cpu] = alloc_stack();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		mcheckirq_ctx[hw_cpu] = alloc_stack();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) void __init setup_power_save(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #ifdef CONFIG_PPC_BOOK3S_32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	if (cpu_has_feature(CPU_FTR_CAN_DOZE) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	    cpu_has_feature(CPU_FTR_CAN_NAP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		ppc_md.power_save = ppc6xx_idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #ifdef CONFIG_E500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	if (cpu_has_feature(CPU_FTR_CAN_DOZE) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	    cpu_has_feature(CPU_FTR_CAN_NAP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		ppc_md.power_save = e500_idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) __init void initialize_cache_info(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	 * Set cache line size based on type of cpu as a default.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	 * Systems with OF can look in the properties on the cpu node(s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	 * for a possibly more accurate value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	dcache_bsize = cur_cpu_spec->dcache_bsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	icache_bsize = cur_cpu_spec->icache_bsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	ucache_bsize = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	if (IS_ENABLED(CONFIG_E200))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		ucache_bsize = icache_bsize = dcache_bsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }