^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2001 Dave Engebretsen, IBM Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * RTAS specific routines for PCI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Based on code from pci.c, chrp_pci.c and pSeries_pci.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/threads.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pgtable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/prom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/machdep.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/pci-bridge.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/iommu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/rtas.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/mpic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/ppc-pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <asm/eeh.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* RTAS tokens */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static int read_pci_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static int write_pci_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static int ibm_read_pci_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static int ibm_write_pci_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static inline int config_access_valid(struct pci_dn *dn, int where)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) if (where < 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) if (where < 4096 && dn->pci_ext_config_space)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) int rtas_read_config(struct pci_dn *pdn, int where, int size, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) int returnval = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) unsigned long buid, addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) if (!pdn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) if (!config_access_valid(pdn, where))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) return PCIBIOS_BAD_REGISTER_NUMBER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #ifdef CONFIG_EEH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) if (pdn->edev && pdn->edev->pe &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) (pdn->edev->pe->state & EEH_PE_CFG_BLOCKED))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return PCIBIOS_SET_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) addr = rtas_config_addr(pdn->busno, pdn->devfn, where);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) buid = pdn->phb->buid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) if (buid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) ret = rtas_call(ibm_read_pci_config, 4, 2, &returnval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) addr, BUID_HI(buid), BUID_LO(buid), size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) ret = rtas_call(read_pci_config, 2, 2, &returnval, addr, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) *val = returnval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static int rtas_pci_read_config(struct pci_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) int where, int size, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct pci_dn *pdn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) *val = 0xFFFFFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) pdn = pci_get_pdn_by_devfn(bus, devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* Validity of pdn is checked in here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) ret = rtas_read_config(pdn, where, size, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if (*val == EEH_IO_ERROR_VALUE(size) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) eeh_dev_check_failure(pdn_to_eeh_dev(pdn)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) int rtas_write_config(struct pci_dn *pdn, int where, int size, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) unsigned long buid, addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (!pdn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (!config_access_valid(pdn, where))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return PCIBIOS_BAD_REGISTER_NUMBER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #ifdef CONFIG_EEH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (pdn->edev && pdn->edev->pe &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) (pdn->edev->pe->state & EEH_PE_CFG_BLOCKED))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return PCIBIOS_SET_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) addr = rtas_config_addr(pdn->busno, pdn->devfn, where);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) buid = pdn->phb->buid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) if (buid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) ret = rtas_call(ibm_write_pci_config, 5, 1, NULL, addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) BUID_HI(buid), BUID_LO(buid), size, (ulong) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) ret = rtas_call(write_pci_config, 3, 1, NULL, addr, size, (ulong)val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static int rtas_pci_write_config(struct pci_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) int where, int size, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct pci_dn *pdn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) pdn = pci_get_pdn_by_devfn(bus, devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* Validity of pdn is checked in here. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return rtas_write_config(pdn, where, size, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static struct pci_ops rtas_pci_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .read = rtas_pci_read_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .write = rtas_pci_write_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static int is_python(struct device_node *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) const char *model = of_get_property(dev, "model", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (model && strstr(model, "Python"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static void python_countermeasures(struct device_node *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct resource registers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) void __iomem *chip_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) volatile u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (of_address_to_resource(dev, 0, ®isters)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) printk(KERN_ERR "Can't get address for Python workarounds !\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* Python's register file is 1 MB in size. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) chip_regs = ioremap(registers.start & ~(0xfffffUL), 0x100000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * Firmware doesn't always clear this bit which is critical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * for good performance - Anton
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define PRG_CL_RESET_VALID 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) val = in_be32(chip_regs + 0xf6030);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (val & PRG_CL_RESET_VALID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) printk(KERN_INFO "Python workaround: ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) val &= ~PRG_CL_RESET_VALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) out_be32(chip_regs + 0xf6030, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * We must read it back for changes to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * take effect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) val = in_be32(chip_regs + 0xf6030);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) printk("reg0: %x\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) iounmap(chip_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) void __init init_pci_config_tokens(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) read_pci_config = rtas_token("read-pci-config");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) write_pci_config = rtas_token("write-pci-config");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) ibm_read_pci_config = rtas_token("ibm,read-pci-config");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) ibm_write_pci_config = rtas_token("ibm,write-pci-config");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) unsigned long get_phb_buid(struct device_node *phb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct resource r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (ibm_read_pci_config == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (of_address_to_resource(phb, 0, &r))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return r.start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static int phb_set_bus_ranges(struct device_node *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct pci_controller *phb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) const __be32 *bus_range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) unsigned int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) bus_range = of_get_property(dev, "bus-range", &len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (bus_range == NULL || len < 2 * sizeof(int)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) phb->first_busno = be32_to_cpu(bus_range[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) phb->last_busno = be32_to_cpu(bus_range[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) int rtas_setup_phb(struct pci_controller *phb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct device_node *dev = phb->dn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (is_python(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) python_countermeasures(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (phb_set_bus_ranges(dev, phb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) phb->ops = &rtas_pci_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) phb->buid = get_phb_buid(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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