^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #include <linux/regset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/elf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <asm/switch_to.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include "ptrace-decl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Get/set all the altivec registers vr0..vr31, vscr, vrsave, in one go.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * The transfer totals 34 quadword. Quadwords 0-31 contain the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * corresponding vector registers. Quadword 32 contains the vscr as the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * last word (offset 12) within that quadword. Quadword 33 contains the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * vrsave as the first word (offset 0) within the quadword.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * This definition of the VMX state is compatible with the current PPC32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * ptrace interface. This allows signal handling and ptrace to use the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * same structures. This also simplifies the implementation of a bi-arch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * (combined (32- and 64-bit) gdb.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) int vr_active(struct task_struct *target, const struct user_regset *regset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) flush_altivec_to_thread(target);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) return target->thread.used_vr ? regset->n : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * Regardless of transactions, 'vr_state' holds the current running
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * value of all the VMX registers and 'ckvr_state' holds the last
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * checkpointed value of all the VMX registers for the current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * transaction to fall back on in case it aborts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * Userspace interface buffer layout:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * struct data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * vector128 vr[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * vector128 vscr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * vector128 vrsave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) int vr_get(struct task_struct *target, const struct user_regset *regset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct membuf to)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) elf_vrreg_t reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) u32 word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) } vrsave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) flush_altivec_to_thread(target);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) BUILD_BUG_ON(offsetof(struct thread_vr_state, vscr) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) offsetof(struct thread_vr_state, vr[32]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) membuf_write(&to, &target->thread.vr_state, 33 * sizeof(vector128));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * Copy out only the low-order word of vrsave.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) memset(&vrsave, 0, sizeof(vrsave));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) vrsave.word = target->thread.vrsave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) return membuf_write(&to, &vrsave, sizeof(vrsave));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * Regardless of transactions, 'vr_state' holds the current running
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * value of all the VMX registers and 'ckvr_state' holds the last
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * checkpointed value of all the VMX registers for the current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * transaction to fall back on in case it aborts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * Userspace interface buffer layout:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * struct data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * vector128 vr[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * vector128 vscr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * vector128 vrsave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) int vr_set(struct task_struct *target, const struct user_regset *regset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) unsigned int pos, unsigned int count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) const void *kbuf, const void __user *ubuf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) flush_altivec_to_thread(target);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) BUILD_BUG_ON(offsetof(struct thread_vr_state, vscr) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) offsetof(struct thread_vr_state, vr[32]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) &target->thread.vr_state, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) 33 * sizeof(vector128));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if (!ret && count > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * We use only the first word of vrsave.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) int start, end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) elf_vrreg_t reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u32 word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) } vrsave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) memset(&vrsave, 0, sizeof(vrsave));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) vrsave.word = target->thread.vrsave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) start = 33 * sizeof(vector128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) end = start + sizeof(vrsave);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &vrsave,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) start, end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) target->thread.vrsave = vrsave.word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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