^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * arch/powerpc/kernel/pmc.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2004 David Gibson, IBM Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Includes code formerly from arch/ppc/kernel/perfmon.c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Andy Fleming
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (c) 2004 Freescale Semiconductor, Inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/bug.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/processor.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/cputable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/pmc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #ifndef MMCR0_PMAO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MMCR0_PMAO 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static void dummy_perf(struct pt_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #if defined(CONFIG_FSL_EMB_PERFMON)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) mtpmr(PMRN_PMGC0, mfpmr(PMRN_PMGC0) & ~PMGC0_PMIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #elif defined(CONFIG_PPC64) || defined(CONFIG_PPC_BOOK3S_32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) if (cur_cpu_spec->pmc_type == PPC_PMC_IBM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) mtspr(SPRN_MMCR0, mfspr(SPRN_MMCR0) & ~(MMCR0_PMXE|MMCR0_PMAO));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) mtspr(SPRN_MMCR0, mfspr(SPRN_MMCR0) & ~MMCR0_PMXE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static DEFINE_RAW_SPINLOCK(pmc_owner_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static void *pmc_owner_caller; /* mostly for debugging */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) perf_irq_t perf_irq = dummy_perf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) int reserve_pmc_hardware(perf_irq_t new_perf_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) raw_spin_lock(&pmc_owner_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) if (pmc_owner_caller) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) printk(KERN_WARNING "reserve_pmc_hardware: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) "PMC hardware busy (reserved by caller %p)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) pmc_owner_caller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) err = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) pmc_owner_caller = __builtin_return_address(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) perf_irq = new_perf_irq ? new_perf_irq : dummy_perf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) raw_spin_unlock(&pmc_owner_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) EXPORT_SYMBOL_GPL(reserve_pmc_hardware);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) void release_pmc_hardware(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) raw_spin_lock(&pmc_owner_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) WARN_ON(! pmc_owner_caller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) pmc_owner_caller = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) perf_irq = dummy_perf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) raw_spin_unlock(&pmc_owner_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) EXPORT_SYMBOL_GPL(release_pmc_hardware);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #ifdef CONFIG_PPC64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) void power4_enable_pmcs(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) unsigned long hid0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) hid0 = mfspr(SPRN_HID0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) hid0 |= 1UL << (63 - 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* POWER4 requires the following sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) asm volatile(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) "sync\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) "mtspr %1, %0\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) "mfspr %0, %1\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) "mfspr %0, %1\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) "mfspr %0, %1\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) "mfspr %0, %1\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) "mfspr %0, %1\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) "mfspr %0, %1\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) "isync" : "=&r" (hid0) : "i" (SPRN_HID0), "0" (hid0):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #endif /* CONFIG_PPC64 */