Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Port for PPC64 David Engebretsen, IBM Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *   Rework, based on alpha PCI code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #undef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/syscalls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/vmalloc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <asm/processor.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <asm/prom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <asm/pci-bridge.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include <asm/byteorder.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #include <asm/machdep.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #include <asm/ppc-pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) /* pci_io_base -- the base address from which io bars are offsets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  * This is the lowest I/O base address (so bar values are always positive),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  * and it *must* be the start of ISA space if an ISA bus exists because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  * ISA drivers use hard coded offsets.  If no ISA bus exists nothing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)  * is mapped on the first 64K of IO space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) unsigned long pci_io_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) EXPORT_SYMBOL(pci_io_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) static int __init pcibios_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	struct pci_controller *hose, *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	printk(KERN_INFO "PCI: Probing PCI hardware\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	/* For now, override phys_mem_access_prot. If we need it,g
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	 * later, we may move that initialization to each ppc_md
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	/* On ppc64, we always enable PCI domains and we keep domain 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	 * backward compatible in /proc for video cards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	pci_add_flags(PCI_ENABLE_PROC_DOMAINS | PCI_COMPAT_DOMAIN_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	/* Scan all of the recorded PCI controllers.  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 		pcibios_scan_phb(hose);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	/* Call common code to handle resource allocation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	pcibios_resource_survey();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	/* Add devices. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		pci_bus_add_devices(hose->bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	/* Call machine dependent fixup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	if (ppc_md.pcibios_fixup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		ppc_md.pcibios_fixup();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	printk(KERN_DEBUG "PCI: Probing PCI hardware done\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) subsys_initcall(pcibios_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) int pcibios_unmap_io_space(struct pci_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	struct pci_controller *hose;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	WARN_ON(bus == NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	/* If this is not a PHB, we only flush the hash table over
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	 * the area mapped by this bridge. We don't play with the PTE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	 * mappings since we might have to deal with sub-page alignments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	 * so flushing the hash table is the only sane way to make sure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	 * that no hash entries are covering that removed bridge area
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	 * while still allowing other busses overlapping those pages
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	 * Note: If we ever support P2P hotplug on Book3E, we'll have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	 * to do an appropriate TLB flush here too
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	if (bus->self) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #ifdef CONFIG_PPC_BOOK3S_64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		struct resource *res = bus->resource[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		pr_debug("IO unmapping for PCI-PCI bridge %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 			 pci_name(bus->self));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #ifdef CONFIG_PPC_BOOK3S_64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		__flush_hash_table_range(res->start + _IO_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 					 res->end + _IO_BASE + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	/* Get the host bridge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	hose = pci_bus_to_host(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	pr_debug("IO unmapping for PHB %pOF\n", hose->dn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	pr_debug("  alloc=0x%p\n", hose->io_base_alloc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	iounmap(hose->io_base_alloc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) EXPORT_SYMBOL_GPL(pcibios_unmap_io_space);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) void __iomem *ioremap_phb(phys_addr_t paddr, unsigned long size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	struct vm_struct *area;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	unsigned long addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	WARN_ON_ONCE(paddr & ~PAGE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	WARN_ON_ONCE(size & ~PAGE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	 * Let's allocate some IO space for that guy. We don't pass VM_IOREMAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	 * because we don't care about alignment tricks that the core does in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	 * that case.  Maybe we should due to stupid card with incomplete
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	 * address decoding but I'd rather not deal with those outside of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	 * reserved 64K legacy region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	area = __get_vm_area_caller(size, 0, PHB_IO_BASE, PHB_IO_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 				    __builtin_return_address(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	if (!area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	addr = (unsigned long)area->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	if (ioremap_page_range(addr, addr + size, paddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 			pgprot_noncached(PAGE_KERNEL))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		unmap_kernel_range(addr, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	return (void __iomem *)addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) EXPORT_SYMBOL_GPL(ioremap_phb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static int pcibios_map_phb_io_space(struct pci_controller *hose)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	unsigned long phys_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	unsigned long size_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	unsigned long io_virt_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	phys_page = ALIGN_DOWN(hose->io_base_phys, PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	size_page = ALIGN(hose->pci_io_size, PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	/* Make sure IO area address is clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	hose->io_base_alloc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	/* If there's no IO to map on that bus, get away too */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	if (hose->pci_io_size == 0 || hose->io_base_phys == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	/* Let's allocate some IO space for that guy. We don't pass
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	 * VM_IOREMAP because we don't care about alignment tricks that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	 * the core does in that case. Maybe we should due to stupid card
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	 * with incomplete address decoding but I'd rather not deal with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	 * those outside of the reserved 64K legacy region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	hose->io_base_alloc = ioremap_phb(phys_page, size_page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	if (!hose->io_base_alloc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	hose->io_base_virt = hose->io_base_alloc +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 				hose->io_base_phys - phys_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	pr_debug("IO mapping for PHB %pOF\n", hose->dn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	pr_debug("  phys=0x%016llx, virt=0x%p (alloc=0x%p)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		 hose->io_base_phys, hose->io_base_virt, hose->io_base_alloc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	pr_debug("  size=0x%016llx (alloc=0x%016lx)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		 hose->pci_io_size, size_page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	/* Fixup hose IO resource */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	io_virt_offset = pcibios_io_space_offset(hose);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	hose->io_resource.start += io_virt_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	hose->io_resource.end += io_virt_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	pr_debug("  hose->io_resource=%pR\n", &hose->io_resource);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) int pcibios_map_io_space(struct pci_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	WARN_ON(bus == NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	/* If this not a PHB, nothing to do, page tables still exist and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	 * thus HPTEs will be faulted in when needed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	if (bus->self) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		pr_debug("IO mapping for PCI-PCI bridge %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 			 pci_name(bus->self));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		pr_debug("  virt=0x%016llx...0x%016llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 			 bus->resource[0]->start + _IO_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 			 bus->resource[0]->end + _IO_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	return pcibios_map_phb_io_space(pci_bus_to_host(bus));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) EXPORT_SYMBOL_GPL(pcibios_map_io_space);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) void pcibios_setup_phb_io_space(struct pci_controller *hose)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	pcibios_map_phb_io_space(hose);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define IOBASE_BRIDGE_NUMBER	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define IOBASE_MEMORY		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define IOBASE_IO		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define IOBASE_ISA_IO		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define IOBASE_ISA_MEM		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) SYSCALL_DEFINE3(pciconfig_iobase, long, which, unsigned long, in_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 			  unsigned long, in_devfn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	struct pci_controller* hose;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	struct pci_bus *tmp_bus, *bus = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	struct device_node *hose_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	/* Argh ! Please forgive me for that hack, but that's the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	 * simplest way to get existing XFree to not lockup on some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	 * G5 machines... So when something asks for bus 0 io base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	 * (bus 0 is HT root), we return the AGP one instead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	if (in_bus == 0 && of_machine_is_compatible("MacRISC4")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		struct device_node *agp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		agp = of_find_compatible_node(NULL, NULL, "u3-agp");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		if (agp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 			in_bus = 0xf0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		of_node_put(agp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	/* That syscall isn't quite compatible with PCI domains, but it's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	 * used on pre-domains setup. We return the first match
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	list_for_each_entry(tmp_bus, &pci_root_buses, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		if (in_bus >= tmp_bus->number &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		    in_bus <= tmp_bus->busn_res.end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 			bus = tmp_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	if (bus == NULL || bus->dev.of_node == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	hose_node = bus->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	hose = PCI_DN(hose_node)->phb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	switch (which) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	case IOBASE_BRIDGE_NUMBER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		return (long)hose->first_busno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	case IOBASE_MEMORY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		return (long)hose->mem_offset[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	case IOBASE_IO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		return (long)hose->io_base_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	case IOBASE_ISA_IO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		return (long)isa_io_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	case IOBASE_ISA_MEM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #ifdef CONFIG_NUMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) int pcibus_to_node(struct pci_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	struct pci_controller *phb = pci_bus_to_host(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	return phb->node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) EXPORT_SYMBOL(pcibus_to_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #endif