^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Derived from "arch/powerpc/platforms/pseries/pci_dlpar.c"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2003 Linda Xie <lxie@us.ibm.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2005 International Business Machines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Updates, 2005, John Rose <johnrose@austin.ibm.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Updates, 2005, Linas Vepstas <linas@austin.ibm.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Updates, 2013, Gavin Shan <shangw@linux.vnet.ibm.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/pci-bridge.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/ppc-pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/firmware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/eeh.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static struct pci_bus *find_bus_among_children(struct pci_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct device_node *dn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct pci_bus *child = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct pci_bus *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) if (pci_bus_to_OF_node(bus) == dn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) return bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) list_for_each_entry(tmp, &bus->children, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) child = find_bus_among_children(tmp, dn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) if (child)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) return child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct pci_bus *pci_find_bus_by_node(struct device_node *dn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct pci_dn *pdn = PCI_DN(dn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) if (!pdn || !pdn->phb || !pdn->phb->bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) return find_bus_among_children(pdn->phb->bus, dn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) EXPORT_SYMBOL_GPL(pci_find_bus_by_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * pcibios_release_device - release PCI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * @dev: PCI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * The function is called before releasing the indicated PCI device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) void pcibios_release_device(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct pci_controller *phb = pci_bus_to_host(dev->bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct pci_dn *pdn = pci_get_pdn(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) if (phb->controller_ops.release_device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) phb->controller_ops.release_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* free()ing the pci_dn has been deferred to us, do it now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) if (pdn && (pdn->flags & PCI_DN_FLAG_DEAD)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) pci_dbg(dev, "freeing dead pdn\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) kfree(pdn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * pci_hp_remove_devices - remove all devices under this bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * @bus: the indicated PCI bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * Remove all of the PCI devices under this bus both from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * linux pci device tree, and from the powerpc EEH address cache.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) void pci_hp_remove_devices(struct pci_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct pci_dev *dev, *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct pci_bus *child_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* First go down child busses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) list_for_each_entry(child_bus, &bus->children, node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) pci_hp_remove_devices(child_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) pr_debug("PCI: Removing devices on bus %04x:%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) pci_domain_nr(bus), bus->number);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) list_for_each_entry_safe_reverse(dev, tmp, &bus->devices, bus_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) pr_debug(" Removing %s...\n", pci_name(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) pci_stop_and_remove_bus_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) EXPORT_SYMBOL_GPL(pci_hp_remove_devices);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * pci_hp_add_devices - adds new pci devices to bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * @bus: the indicated PCI bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * This routine will find and fixup new pci devices under
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * the indicated bus. This routine presumes that there
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * might already be some devices under this bridge, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * it carefully tries to add only new devices. (And that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * is how this routine differs from other, similar pcibios
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * routines.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) void pci_hp_add_devices(struct pci_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) int slotno, mode, max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct pci_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct pci_controller *phb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct device_node *dn = pci_bus_to_OF_node(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) phb = pci_bus_to_host(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) mode = PCI_PROBE_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (phb->controller_ops.probe_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) mode = phb->controller_ops.probe_mode(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (mode == PCI_PROBE_DEVTREE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* use ofdt-based probe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) of_rescan_bus(dn, bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) } else if (mode == PCI_PROBE_NORMAL &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) dn->child && PCI_DN(dn->child)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * Use legacy probe. In the partial hotplug case, we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * probably have grandchildren devices unplugged. So
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * we don't check the return value from pci_scan_slot() in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * order for fully rescan all the way down to pick them up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * They can have been removed during partial hotplug.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) slotno = PCI_SLOT(PCI_DN(dn->child)->devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) pci_scan_slot(bus, PCI_DEVFN(slotno, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) max = bus->busn_res.start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * Scan bridges that are already configured. We don't touch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * them unless they are misconfigured (which will be done in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * the second scan below).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) for_each_pci_bridge(dev, bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) max = pci_scan_bridge(bus, dev, max, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* Scan bridges that need to be reconfigured */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) for_each_pci_bridge(dev, bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) max = pci_scan_bridge(bus, dev, max, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) pcibios_finish_adding_to_bus(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) EXPORT_SYMBOL_GPL(pci_hp_add_devices);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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