Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * This file contains miscellaneous low-level functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * and Paul Mackerras.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Adapted for iSeries by Mike Corrigan (mikejc@us.ibm.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * PPC64 updates by Dave Engebretsen (engebret@us.ibm.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/sys.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <asm/unistd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <asm/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <asm/processor.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <asm/cache.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <asm/ppc_asm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <asm/asm-offsets.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <asm/cputable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <asm/thread_info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <asm/kexec.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <asm/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <asm/mmu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <asm/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <asm/feature-fixups.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	.text
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) _GLOBAL(call_do_softirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	mflr	r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	std	r0,16(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	stdu	r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	mr	r1,r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	bl	__do_softirq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	ld	r1,0(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	ld	r0,16(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	mtlr	r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	blr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) _GLOBAL(call_do_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	mflr	r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	std	r0,16(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	stdu	r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	mr	r1,r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	bl	__do_irq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	ld	r1,0(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	ld	r0,16(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	mtlr	r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	blr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) _GLOBAL(__bswapdi2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) EXPORT_SYMBOL(__bswapdi2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	srdi	r8,r3,32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	rlwinm	r7,r3,8,0xffffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	rlwimi	r7,r3,24,0,7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	rlwinm	r9,r8,8,0xffffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	rlwimi	r7,r3,24,16,23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	rlwimi	r9,r8,24,0,7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	rlwimi	r9,r8,24,16,23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	sldi	r7,r7,32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	or	r3,r7,r9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	blr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #ifdef CONFIG_PPC_EARLY_DEBUG_BOOTX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) _GLOBAL(rmci_on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	li	r3,0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	rldicl	r3,r3,32,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	mfspr	r5,SPRN_HID4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	or	r5,r5,r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	mtspr	SPRN_HID4,r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	slbia
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	blr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) _GLOBAL(rmci_off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	li	r3,0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	rldicl	r3,r3,32,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	mfspr	r5,SPRN_HID4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	andc	r5,r5,r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	mtspr	SPRN_HID4,r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	slbia
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	blr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #endif /* CONFIG_PPC_EARLY_DEBUG_BOOTX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #if defined(CONFIG_PPC_PMAC) || defined(CONFIG_PPC_MAPLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)  * Do an IO access in real mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) _GLOBAL(real_readb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	mfmsr	r7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	ori	r0,r7,MSR_DR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	xori	r0,r0,MSR_DR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	mtmsrd	r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	mfspr	r6,SPRN_HID4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	rldicl	r5,r6,32,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	ori	r5,r5,0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	rldicl	r5,r5,32,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	mtspr	SPRN_HID4,r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	slbia
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	lbz	r3,0(r3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	mtspr	SPRN_HID4,r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	slbia
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	mtmsrd	r7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	blr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)  * Do an IO access in real mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) _GLOBAL(real_writeb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	mfmsr	r7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	ori	r0,r7,MSR_DR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	xori	r0,r0,MSR_DR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	mtmsrd	r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	mfspr	r6,SPRN_HID4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	rldicl	r5,r6,32,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	ori	r5,r5,0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	rldicl	r5,r5,32,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	mtspr	SPRN_HID4,r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	slbia
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	stb	r3,0(r4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	mtspr	SPRN_HID4,r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	slbia
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	mtmsrd	r7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	blr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #endif /* defined(CONFIG_PPC_PMAC) || defined(CONFIG_PPC_MAPLE) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #ifdef CONFIG_PPC_PASEMI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) _GLOBAL(real_205_readb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	mfmsr	r7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	ori	r0,r7,MSR_DR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	xori	r0,r0,MSR_DR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	mtmsrd	r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	LBZCIX(R3,R0,R3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	mtmsrd	r7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	blr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) _GLOBAL(real_205_writeb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	mfmsr	r7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	ori	r0,r7,MSR_DR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	xori	r0,r0,MSR_DR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	mtmsrd	r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	STBCIX(R3,R0,R4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	mtmsrd	r7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	blr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #endif /* CONFIG_PPC_PASEMI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #if defined(CONFIG_CPU_FREQ_PMAC64) || defined(CONFIG_CPU_FREQ_MAPLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)  * SCOM access functions for 970 (FX only for now)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)  * unsigned long scom970_read(unsigned int address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)  * void scom970_write(unsigned int address, unsigned long value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)  * The address passed in is the 24 bits register address. This code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)  * is 970 specific and will not check the status bits, so you should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)  * know what you are doing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) _GLOBAL(scom970_read)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	/* interrupts off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	mfmsr	r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	ori	r0,r4,MSR_EE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	xori	r0,r0,MSR_EE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	mtmsrd	r0,1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	/* rotate 24 bits SCOM address 8 bits left and mask out it's low 8 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	 * (including parity). On current CPUs they must be 0'd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	 * and finally or in RW bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	rlwinm	r3,r3,8,0,15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	ori	r3,r3,0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	/* do the actual scom read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	mtspr	SPRN_SCOMC,r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	mfspr	r3,SPRN_SCOMD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	mfspr	r0,SPRN_SCOMC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	/* XXX:	fixup result on some buggy 970's (ouch ! we lost a bit, bah
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	 * that's the best we can do). Not implemented yet as we don't use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	 * the scom on any of the bogus CPUs yet, but may have to be done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	 * ultimately
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	/* restore interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	mtmsrd	r4,1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	blr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) _GLOBAL(scom970_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	/* interrupts off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	mfmsr	r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	ori	r0,r5,MSR_EE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	xori	r0,r0,MSR_EE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	mtmsrd	r0,1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	/* rotate 24 bits SCOM address 8 bits left and mask out it's low 8 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	 * (including parity). On current CPUs they must be 0'd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	rlwinm	r3,r3,8,0,15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	mtspr	SPRN_SCOMD,r4      /* write data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	mtspr	SPRN_SCOMC,r3      /* write command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	mfspr	3,SPRN_SCOMC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	/* restore interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	mtmsrd	r5,1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	blr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #endif /* CONFIG_CPU_FREQ_PMAC64 || CONFIG_CPU_FREQ_MAPLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /* kexec_wait(phys_cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)  * wait for the flag to change, indicating this kernel is going away but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)  * the slave code for the next one is at addresses 0 to 100.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)  * This is used by all slaves, even those that did not find a matching
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)  * paca in the secondary startup code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)  * Physical (hardware) cpu id should be in r3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) _GLOBAL(kexec_wait)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	bl	1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 1:	mflr	r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	addi	r5,r5,kexec_flag-1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 99:	HMT_LOW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #ifdef CONFIG_KEXEC_CORE	/* use no memory without kexec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	lwz	r4,0(r5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	cmpwi	0,r4,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	beq	99b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #ifdef CONFIG_PPC_BOOK3S_64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	li	r10,0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	mfmsr	r11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	clrrdi	r11,r11,1	/* Clear MSR_LE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	mtsrr0	r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	mtsrr1	r11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	rfid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	/* Create TLB entry in book3e_secondary_core_init */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	li	r4,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	ba	0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* this can be in text because we won't change it until we are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)  * running in real anyways
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) kexec_flag:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	.long	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #ifdef CONFIG_KEXEC_CORE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #ifdef CONFIG_PPC_BOOK3E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)  * BOOK3E has no real MMU mode, so we have to setup the initial TLB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)  * for a core to identity map v:0 to p:0.  This current implementation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)  * assumes that 1G is enough for kexec.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) kexec_create_tlb:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	 * Invalidate all non-IPROT TLB entries to avoid any TLB conflict.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	 * IPROT TLB entries should be >= PAGE_OFFSET and thus not conflict.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	PPC_TLBILX_ALL(0,R0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	mfspr	r10,SPRN_TLB1CFG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	andi.	r10,r10,TLBnCFG_N_ENTRY	/* Extract # entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	subi	r10,r10,1	/* Last entry: no conflict with kernel text */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	lis	r9,MAS0_TLBSEL(1)@h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	rlwimi	r9,r10,16,4,15		/* Setup MAS0 = TLBSEL | ESEL(r9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /* Set up a temp identity mapping v:0 to p:0 and return to it. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	mtspr	SPRN_MAS0,r9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	lis	r9,(MAS1_VALID|MAS1_IPROT)@h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	ori	r9,r9,(MAS1_TSIZE(BOOK3E_PAGESZ_1GB))@l
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	mtspr	SPRN_MAS1,r9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	LOAD_REG_IMMEDIATE(r9, 0x0 | MAS2_M_IF_NEEDED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	mtspr	SPRN_MAS2,r9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	LOAD_REG_IMMEDIATE(r9, 0x0 | MAS3_SR | MAS3_SW | MAS3_SX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	mtspr	SPRN_MAS3,r9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	li	r9,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	mtspr	SPRN_MAS7,r9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	tlbwe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	blr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /* kexec_smp_wait(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)  * call with interrupts off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)  * note: this is a terminal routine, it does not save lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)  * get phys id from paca
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)  * switch to real mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)  * mark the paca as no longer used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)  * join other cpus in kexec_wait(phys_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) _GLOBAL(kexec_smp_wait)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	lhz	r3,PACAHWCPUID(r13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	bl	real_mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	li	r4,KEXEC_STATE_REAL_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	stb	r4,PACAKEXECSTATE(r13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	b	kexec_wait
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)  * switch to real mode (turn mmu off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)  * we use the early kernel trick that the hardware ignores bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)  * 0 and 1 (big endian) of the effective address in real mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)  * don't overwrite r3 here, it is live for kexec_wait above.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) real_mode:	/* assume normal blr return */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #ifdef CONFIG_PPC_BOOK3E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	/* Create an identity mapping. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	b	kexec_create_tlb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 1:	li	r9,MSR_RI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	li	r10,MSR_DR|MSR_IR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	mflr	r11		/* return address to SRR0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	mfmsr	r12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	andc	r9,r12,r9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	andc	r10,r12,r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	mtmsrd	r9,1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	mtspr	SPRN_SRR1,r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	mtspr	SPRN_SRR0,r11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	rfid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)  * kexec_sequence(newstack, start, image, control, clear_all(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	          copy_with_mmu_off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)  * does the grungy work with stack switching and real mode switches
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)  * also does simple calls to other code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) _GLOBAL(kexec_sequence)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	mflr	r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	std	r0,16(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	/* switch stacks to newstack -- &kexec_stack.stack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	stdu	r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	mr	r1,r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	li	r0,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	std	r0,16(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	/* save regs for local vars on new stack.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	 * yes, we won't go back, but ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	std	r31,-8(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	std	r30,-16(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	std	r29,-24(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	std	r28,-32(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	std	r27,-40(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	std	r26,-48(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	std	r25,-56(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	stdu	r1,-STACK_FRAME_OVERHEAD-64(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	/* save args into preserved regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	mr	r31,r3			/* newstack (both) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	mr	r30,r4			/* start (real) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	mr	r29,r5			/* image (virt) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	mr	r28,r6			/* control, unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	mr	r27,r7			/* clear_all() fn desc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	mr	r26,r8			/* copy_with_mmu_off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	lhz	r25,PACAHWCPUID(r13)	/* get our phys cpu from paca */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	/* disable interrupts, we are overwriting kernel data next */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #ifdef CONFIG_PPC_BOOK3E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	wrteei	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	mfmsr	r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	rlwinm	r3,r3,0,17,15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	mtmsrd	r3,1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 	/* We need to turn the MMU off unless we are in hash mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 	 * under a hypervisor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	cmpdi	r26,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	beq	1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 	bl	real_mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 	/* copy dest pages, flush whole dest image */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 	mr	r3,r29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 	bl	kexec_copy_flush	/* (image) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 	/* turn off mmu now if not done earlier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	cmpdi	r26,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 	bne	1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 	bl	real_mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 	/* copy  0x100 bytes starting at start to 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 1:	li	r3,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 	mr	r4,r30		/* start, aka phys mem offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 	li	r5,0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 	li	r6,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 	bl	copy_and_flush	/* (dest, src, copy limit, start offset) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 1:	/* assume normal blr return */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 	/* release other cpus to the new kernel secondary start at 0x60 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 	mflr	r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 	li	r6,1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 	stw	r6,kexec_flag-1b(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 	cmpdi	r27,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 	beq	1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 	/* clear out hardware hash page table and tlb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #ifdef PPC64_ELF_ABI_v1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 	ld	r12,0(r27)		/* deref function descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 	mr	r12,r27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 	mtctr	r12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 	bctrl				/* mmu_hash_ops.hpte_clear_all(void); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)  *   kexec image calling is:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)  *      the first 0x100 bytes of the entry point are copied to 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)  *      all slaves branch to slave = 0x60 (absolute)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)  *              slave(phys_cpu_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)  *      master goes to start = entry point
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)  *              start(phys_cpu_id, start, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)  *   a wrapper is needed to call existing kernels, here is an approximate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)  *   description of one method:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)  * v2: (2.6.10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)  *   start will be near the boot_block (maybe 0x100 bytes before it?)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)  *   it will have a 0x60, which will b to boot_block, where it will wait
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)  *   and 0 will store phys into struct boot-block and load r3 from there,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)  *   copy kernel 0-0x100 and tell slaves to back down to 0x60 again
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)  * v1: (2.6.9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)  *    boot block will have all cpus scanning device tree to see if they
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)  *    are the boot cpu ?????
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)  *    other device tree differences (prop sizes, va vs pa, etc)...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 1:	mr	r3,r25	# my phys cpu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 	mr	r4,r30	# start, aka phys mem offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 	mtlr	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 	li	r5,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 	blr	/* image->start(physid, image->start, 0); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #endif /* CONFIG_KEXEC_CORE */