^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef __HEAD_BOOKE_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define __HEAD_BOOKE_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <asm/ptrace.h> /* for STACK_FRAME_REGS_MARKER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <asm/kvm_asm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <asm/kvm_booke_hv_asm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifdef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Macros used for common Book-e exception handling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define SET_IVOR(vector_number, vector_label) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) li r26,vector_label@l; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) mtspr SPRN_IVOR##vector_number,r26; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #if (THREAD_SHIFT < 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define ALLOC_STACK_FRAME(reg, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) addi reg,reg,val
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define ALLOC_STACK_FRAME(reg, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) addis reg,reg,val@ha; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) addi reg,reg,val@l
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * Macro used to get to thread save registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * Note that entries 0-3 are used for the prolog code, and the remaining
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * entries are available for specific exception use in the event a handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * requires more than 4 scratch registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define THREAD_NORMSAVE(offset) (THREAD_NORMSAVES + (offset * 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #ifdef CONFIG_PPC_FSL_BOOK3E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define BOOKE_CLEAR_BTB(reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) START_BTB_FLUSH_SECTION \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) BTB_FLUSH(reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) END_BTB_FLUSH_SECTION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define BOOKE_CLEAR_BTB(reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define NORMAL_EXCEPTION_PROLOG(intno) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) mtspr SPRN_SPRG_WSCRATCH0, r10; /* save one register */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) mfspr r10, SPRN_SPRG_THREAD; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) stw r11, THREAD_NORMSAVE(0)(r10); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) stw r13, THREAD_NORMSAVE(2)(r10); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) mfcr r13; /* save CR in r13 for now */\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) mfspr r11, SPRN_SRR1; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) DO_KVM BOOKE_INTERRUPT_##intno SPRN_SRR1; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) andi. r11, r11, MSR_PR; /* check whether user or kernel */\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) mr r11, r1; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) beq 1f; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) BOOKE_CLEAR_BTB(r11) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* if from user, start at top of this thread's kernel stack */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) lwz r11, TASK_STACK - THREAD(r10); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) ALLOC_STACK_FRAME(r11, THREAD_SIZE); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 1 : subi r11, r11, INT_FRAME_SIZE; /* Allocate exception frame */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) stw r13, _CCR(r11); /* save various registers */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) stw r12,GPR12(r11); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) stw r9,GPR9(r11); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) mfspr r13, SPRN_SPRG_RSCRATCH0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) stw r13, GPR10(r11); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) lwz r12, THREAD_NORMSAVE(0)(r10); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) stw r12,GPR11(r11); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) lwz r13, THREAD_NORMSAVE(2)(r10); /* restore r13 */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) mflr r10; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) stw r10,_LINK(r11); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) mfspr r12,SPRN_SRR0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) stw r1, GPR1(r11); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) mfspr r9,SPRN_SRR1; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) stw r1, 0(r11); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) mr r1, r11; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) stw r0,GPR0(r11); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) lis r10, STACK_FRAME_REGS_MARKER@ha;/* exception frame marker */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) addi r10, r10, STACK_FRAME_REGS_MARKER@l; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) stw r10, 8(r11); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) SAVE_4GPRS(3, r11); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) SAVE_2GPRS(7, r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .macro SYSCALL_ENTRY trapno intno srr1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) mfspr r10, SPRN_SPRG_THREAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #ifdef CONFIG_KVM_BOOKE_HV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) BEGIN_FTR_SECTION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) mtspr SPRN_SPRG_WSCRATCH0, r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) stw r11, THREAD_NORMSAVE(0)(r10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) stw r13, THREAD_NORMSAVE(2)(r10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) mfcr r13 /* save CR in r13 for now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) mfspr r11, SPRN_SRR1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) mtocrf 0x80, r11 /* check MSR[GS] without clobbering reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) bf 3, 1975f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) b kvmppc_handler_\intno\()_\srr1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) 1975:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) mr r12, r13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) lwz r13, THREAD_NORMSAVE(2)(r10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) FTR_SECTION_ELSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) mfcr r12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #ifdef CONFIG_KVM_BOOKE_HV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) ALT_FTR_SECTION_END_IFSET(CPU_FTR_EMB_HV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) mfspr r9, SPRN_SRR1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) BOOKE_CLEAR_BTB(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) andi. r11, r9, MSR_PR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) lwz r11, TASK_STACK - THREAD(r10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) rlwinm r12,r12,0,4,2 /* Clear SO bit in CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) beq- 99f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) ALLOC_STACK_FRAME(r11, THREAD_SIZE - INT_FRAME_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) stw r12, _CCR(r11) /* save various registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) mflr r12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) stw r12,_LINK(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) mfspr r12,SPRN_SRR0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) stw r1, GPR1(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) stw r1, 0(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) mr r1, r11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) stw r12,_NIP(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) rlwinm r9,r9,0,14,12 /* clear MSR_WE (necessary?) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) lis r12, STACK_FRAME_REGS_MARKER@ha /* exception frame marker */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) stw r2,GPR2(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) addi r12, r12, STACK_FRAME_REGS_MARKER@l
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) stw r9,_MSR(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) li r2, \trapno + 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) stw r12, 8(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) stw r2,_TRAP(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) SAVE_GPR(0, r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) SAVE_4GPRS(3, r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) SAVE_2GPRS(7, r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) addi r11,r1,STACK_FRAME_OVERHEAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) addi r2,r10,-THREAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) stw r11,PT_REGS(r10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* Check to see if the dbcr0 register is set up to debug. Use the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) internal debug mode bit to do this. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) lwz r12,THREAD_DBCR0(r10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) andis. r12,r12,DBCR0_IDM@h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) ACCOUNT_CPU_USER_ENTRY(r2, r11, r12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) beq+ 3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* From user and task is ptraced - load up global dbcr0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) li r12,-1 /* clear all pending debug events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) mtspr SPRN_DBSR,r12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) lis r11,global_dbcr0@ha
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) tophys(r11,r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) addi r11,r11,global_dbcr0@l
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) lwz r10, TASK_CPU(r2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) slwi r10, r10, 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) add r11, r11, r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) lwz r12,0(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) mtspr SPRN_DBCR0,r12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) lwz r12,4(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) addi r12,r12,-1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) stw r12,4(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) tovirt(r2, r2) /* set r2 to current */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) lis r11, transfer_to_syscall@h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) ori r11, r11, transfer_to_syscall@l
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #ifdef CONFIG_TRACE_IRQFLAGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * If MSR is changing we need to keep interrupts disabled at this point
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * otherwise we might risk taking an interrupt before we tell lockdep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * they are enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) lis r10, MSR_KERNEL@h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) ori r10, r10, MSR_KERNEL@l
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) rlwimi r10, r9, 0, MSR_EE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) lis r10, (MSR_KERNEL | MSR_EE)@h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) ori r10, r10, (MSR_KERNEL | MSR_EE)@l
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) mtspr SPRN_SRR1,r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) mtspr SPRN_SRR0,r11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) RFI /* jump to handler, enable MMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 99: b ret_from_kernel_syscall
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* To handle the additional exception priority levels on 40x and Book-E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * processors we allocate a stack per additional priority level.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * On 40x critical is the only additional level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * On 44x/e500 we have critical and machine check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * On e200 we have critical and debug (machine check occurs via critical)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * Additionally we reserve a SPRG for each priority level so we can free up a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * GPR to use as the base for indirect access to the exception stacks. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * is necessary since the MMU is always on, for Book-E parts, and the stacks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * are offset from KERNELBASE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * There is some space optimization to be had here if desired. However
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * to allow for a common kernel with support for debug exceptions either
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * going to critical or their own debug level we aren't currently
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * providing configurations that micro-optimize space usage.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define MC_STACK_BASE mcheckirq_ctx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define CRIT_STACK_BASE critirq_ctx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* only on e500mc/e200 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define DBG_STACK_BASE dbgirq_ctx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define EXC_LVL_FRAME_OVERHEAD (THREAD_SIZE - INT_FRAME_SIZE - EXC_LVL_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define BOOKE_LOAD_EXC_LEVEL_STACK(level) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) mfspr r8,SPRN_PIR; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) slwi r8,r8,2; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) addis r8,r8,level##_STACK_BASE@ha; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) lwz r8,level##_STACK_BASE@l(r8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) addi r8,r8,EXC_LVL_FRAME_OVERHEAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define BOOKE_LOAD_EXC_LEVEL_STACK(level) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) lis r8,level##_STACK_BASE@ha; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) lwz r8,level##_STACK_BASE@l(r8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) addi r8,r8,EXC_LVL_FRAME_OVERHEAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * Exception prolog for critical/machine check exceptions. This is a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * little different from the normal exception prolog above since a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * critical/machine check exception can potentially occur at any point
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * during normal exception processing. Thus we cannot use the same SPRG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * registers as the normal prolog above. Instead we use a portion of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * critical/machine check exception stack at low physical addresses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define EXC_LEVEL_EXCEPTION_PROLOG(exc_level, intno, exc_level_srr0, exc_level_srr1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) mtspr SPRN_SPRG_WSCRATCH_##exc_level,r8; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) BOOKE_LOAD_EXC_LEVEL_STACK(exc_level);/* r8 points to the exc_level stack*/ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) stw r9,GPR9(r8); /* save various registers */\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) mfcr r9; /* save CR in r9 for now */\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) stw r10,GPR10(r8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) stw r11,GPR11(r8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) stw r9,_CCR(r8); /* save CR on stack */\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) mfspr r11,exc_level_srr1; /* check whether user or kernel */\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) DO_KVM BOOKE_INTERRUPT_##intno exc_level_srr1; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) BOOKE_CLEAR_BTB(r10) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) andi. r11,r11,MSR_PR; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) mfspr r11,SPRN_SPRG_THREAD; /* if from user, start at top of */\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) lwz r11, TASK_STACK - THREAD(r11); /* this thread's kernel stack */\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) addi r11,r11,EXC_LVL_FRAME_OVERHEAD; /* allocate stack frame */\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) beq 1f; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* COMING FROM USER MODE */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) stw r9,_CCR(r11); /* save CR */\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) lwz r10,GPR10(r8); /* copy regs from exception stack */\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) lwz r9,GPR9(r8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) stw r10,GPR10(r11); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) lwz r10,GPR11(r8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) stw r9,GPR9(r11); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) stw r10,GPR11(r11); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) b 2f; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* COMING FROM PRIV MODE */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 1: mr r11, r8; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 2: mfspr r8,SPRN_SPRG_RSCRATCH_##exc_level; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) stw r12,GPR12(r11); /* save various registers */\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) mflr r10; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) stw r10,_LINK(r11); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) mfspr r12,SPRN_DEAR; /* save DEAR and ESR in the frame */\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) stw r12,_DEAR(r11); /* since they may have had stuff */\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) mfspr r9,SPRN_ESR; /* in them at the point where the */\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) stw r9,_ESR(r11); /* exception was taken */\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) mfspr r12,exc_level_srr0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) stw r1,GPR1(r11); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) mfspr r9,exc_level_srr1; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) stw r1,0(r11); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) mr r1,r11; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) stw r0,GPR0(r11); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) SAVE_4GPRS(3, r11); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) SAVE_2GPRS(7, r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define CRITICAL_EXCEPTION_PROLOG(intno) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) EXC_LEVEL_EXCEPTION_PROLOG(CRIT, intno, SPRN_CSRR0, SPRN_CSRR1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define DEBUG_EXCEPTION_PROLOG \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) EXC_LEVEL_EXCEPTION_PROLOG(DBG, DEBUG, SPRN_DSRR0, SPRN_DSRR1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define MCHECK_EXCEPTION_PROLOG \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) EXC_LEVEL_EXCEPTION_PROLOG(MC, MACHINE_CHECK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) SPRN_MCSRR0, SPRN_MCSRR1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * Guest Doorbell -- this is a bit odd in that uses GSRR0/1 despite
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * being delivered to the host. This exception can only happen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * inside a KVM guest -- so we just handle up to the DO_KVM rather
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * than try to fit this into one of the existing prolog macros.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define GUEST_DOORBELL_EXCEPTION \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) START_EXCEPTION(GuestDoorbell); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) mtspr SPRN_SPRG_WSCRATCH0, r10; /* save one register */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) mfspr r10, SPRN_SPRG_THREAD; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) stw r11, THREAD_NORMSAVE(0)(r10); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) mfspr r11, SPRN_SRR1; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) stw r13, THREAD_NORMSAVE(2)(r10); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) mfcr r13; /* save CR in r13 for now */\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) DO_KVM BOOKE_INTERRUPT_GUEST_DBELL SPRN_GSRR1; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) trap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * Exception vectors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define START_EXCEPTION(label) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .align 5; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) label:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define EXCEPTION(n, intno, label, hdlr, xfer) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) START_EXCEPTION(label); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) NORMAL_EXCEPTION_PROLOG(intno); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) addi r3,r1,STACK_FRAME_OVERHEAD; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) xfer(n, hdlr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define CRITICAL_EXCEPTION(n, intno, label, hdlr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) START_EXCEPTION(label); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) CRITICAL_EXCEPTION_PROLOG(intno); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) addi r3,r1,STACK_FRAME_OVERHEAD; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) EXC_XFER_TEMPLATE(hdlr, n+2, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) crit_transfer_to_handler, ret_from_crit_exc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define MCHECK_EXCEPTION(n, label, hdlr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) START_EXCEPTION(label); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) MCHECK_EXCEPTION_PROLOG; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) mfspr r5,SPRN_ESR; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) stw r5,_ESR(r11); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) addi r3,r1,STACK_FRAME_OVERHEAD; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) EXC_XFER_TEMPLATE(hdlr, n+4, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) mcheck_transfer_to_handler, ret_from_mcheck_exc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define EXC_XFER_TEMPLATE(hdlr, trap, msr, tfer, ret) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) li r10,trap; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) stw r10,_TRAP(r11); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) lis r10,msr@h; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) ori r10,r10,msr@l; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) bl tfer; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .long hdlr; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .long ret
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define EXC_XFER_STD(n, hdlr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, transfer_to_handler_full, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) ret_from_except_full)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define EXC_XFER_LITE(n, hdlr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, transfer_to_handler, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) ret_from_except)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) /* Check for a single step debug exception while in an exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * handler before state has been saved. This is to catch the case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * where an instruction that we are trying to single step causes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * an exception (eg ITLB/DTLB miss) and thus the first instruction of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * the exception handler generates a single step debug exception.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * If we get a debug trap on the first instruction of an exception handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * we reset the MSR_DE in the _exception handler's_ MSR (the debug trap is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * a critical exception, so we are using SPRN_CSRR1 to manipulate the MSR).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * The exception handler was handling a non-critical interrupt, so it will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * save (and later restore) the MSR via SPRN_CSRR1, which will still have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * the MSR_DE bit set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define DEBUG_DEBUG_EXCEPTION \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) START_EXCEPTION(DebugDebug); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) DEBUG_EXCEPTION_PROLOG; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /* \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * If there is a single step or branch-taken exception in an \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * exception entry sequence, it was probably meant to apply to \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * the code where the exception occurred (since exception entry \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * doesn't turn off DE automatically). We simulate the effect \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * of turning off DE on entry to an exception handler by turning \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * off DE in the DSRR1 value and clearing the debug status. \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) mfspr r10,SPRN_DBSR; /* check single-step/branch taken */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) andis. r10,r10,(DBSR_IC|DBSR_BT)@h; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) beq+ 2f; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) lis r10,interrupt_base@h; /* check if exception in vectors */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) ori r10,r10,interrupt_base@l; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) cmplw r12,r10; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) blt+ 2f; /* addr below exception vectors */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) lis r10,interrupt_end@h; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) ori r10,r10,interrupt_end@l; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) cmplw r12,r10; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) bgt+ 2f; /* addr above exception vectors */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* here it looks like we got an inappropriate debug exception. */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 1: rlwinm r9,r9,0,~MSR_DE; /* clear DE in the CDRR1 value */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) lis r10,(DBSR_IC|DBSR_BT)@h; /* clear the IC event */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) mtspr SPRN_DBSR,r10; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /* restore state and get out */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) lwz r10,_CCR(r11); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) lwz r0,GPR0(r11); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) lwz r1,GPR1(r11); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) mtcrf 0x80,r10; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) mtspr SPRN_DSRR0,r12; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) mtspr SPRN_DSRR1,r9; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) lwz r9,GPR9(r11); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) lwz r12,GPR12(r11); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) mtspr SPRN_SPRG_WSCRATCH_DBG,r8; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) BOOKE_LOAD_EXC_LEVEL_STACK(DBG); /* r8 points to the debug stack */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) lwz r10,GPR10(r8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) lwz r11,GPR11(r8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) mfspr r8,SPRN_SPRG_RSCRATCH_DBG; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) PPC_RFDI; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) b .; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /* continue normal handling for a debug exception... */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 2: mfspr r4,SPRN_DBSR; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) addi r3,r1,STACK_FRAME_OVERHEAD; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) EXC_XFER_TEMPLATE(DebugException, 0x2008, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), debug_transfer_to_handler, ret_from_debug_exc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define DEBUG_CRIT_EXCEPTION \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) START_EXCEPTION(DebugCrit); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) CRITICAL_EXCEPTION_PROLOG(DEBUG); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /* \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * If there is a single step or branch-taken exception in an \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * exception entry sequence, it was probably meant to apply to \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) * the code where the exception occurred (since exception entry \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) * doesn't turn off DE automatically). We simulate the effect \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) * of turning off DE on entry to an exception handler by turning \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) * off DE in the CSRR1 value and clearing the debug status. \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) mfspr r10,SPRN_DBSR; /* check single-step/branch taken */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) andis. r10,r10,(DBSR_IC|DBSR_BT)@h; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) beq+ 2f; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) lis r10,interrupt_base@h; /* check if exception in vectors */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) ori r10,r10,interrupt_base@l; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) cmplw r12,r10; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) blt+ 2f; /* addr below exception vectors */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) lis r10,interrupt_end@h; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) ori r10,r10,interrupt_end@l; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) cmplw r12,r10; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) bgt+ 2f; /* addr above exception vectors */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /* here it looks like we got an inappropriate debug exception. */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 1: rlwinm r9,r9,0,~MSR_DE; /* clear DE in the CSRR1 value */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) lis r10,(DBSR_IC|DBSR_BT)@h; /* clear the IC event */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) mtspr SPRN_DBSR,r10; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /* restore state and get out */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) lwz r10,_CCR(r11); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) lwz r0,GPR0(r11); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) lwz r1,GPR1(r11); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) mtcrf 0x80,r10; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) mtspr SPRN_CSRR0,r12; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) mtspr SPRN_CSRR1,r9; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) lwz r9,GPR9(r11); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) lwz r12,GPR12(r11); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) mtspr SPRN_SPRG_WSCRATCH_CRIT,r8; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) BOOKE_LOAD_EXC_LEVEL_STACK(CRIT); /* r8 points to the debug stack */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) lwz r10,GPR10(r8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) lwz r11,GPR11(r8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) mfspr r8,SPRN_SPRG_RSCRATCH_CRIT; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) rfci; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) b .; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) /* continue normal handling for a critical exception... */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 2: mfspr r4,SPRN_DBSR; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) addi r3,r1,STACK_FRAME_OVERHEAD; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) EXC_XFER_TEMPLATE(DebugException, 0x2002, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), crit_transfer_to_handler, ret_from_crit_exc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define DATA_STORAGE_EXCEPTION \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) START_EXCEPTION(DataStorage) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) NORMAL_EXCEPTION_PROLOG(DATA_STORAGE); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) mfspr r5,SPRN_ESR; /* Grab the ESR and save it */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) stw r5,_ESR(r11); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) mfspr r4,SPRN_DEAR; /* Grab the DEAR */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) stw r4, _DEAR(r11); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) EXC_XFER_LITE(0x0300, handle_page_fault)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define INSTRUCTION_STORAGE_EXCEPTION \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) START_EXCEPTION(InstructionStorage) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) NORMAL_EXCEPTION_PROLOG(INST_STORAGE); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) mfspr r5,SPRN_ESR; /* Grab the ESR and save it */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) stw r5,_ESR(r11); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) mr r4,r12; /* Pass SRR0 as arg2 */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) stw r4, _DEAR(r11); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) li r5,0; /* Pass zero as arg3 */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) EXC_XFER_LITE(0x0400, handle_page_fault)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define ALIGNMENT_EXCEPTION \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) START_EXCEPTION(Alignment) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) NORMAL_EXCEPTION_PROLOG(ALIGNMENT); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) mfspr r4,SPRN_DEAR; /* Grab the DEAR and save it */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) stw r4,_DEAR(r11); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) addi r3,r1,STACK_FRAME_OVERHEAD; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) EXC_XFER_STD(0x0600, alignment_exception)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define PROGRAM_EXCEPTION \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) START_EXCEPTION(Program) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) NORMAL_EXCEPTION_PROLOG(PROGRAM); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) mfspr r4,SPRN_ESR; /* Grab the ESR and save it */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) stw r4,_ESR(r11); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) addi r3,r1,STACK_FRAME_OVERHEAD; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) EXC_XFER_STD(0x0700, program_check_exception)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define DECREMENTER_EXCEPTION \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) START_EXCEPTION(Decrementer) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) NORMAL_EXCEPTION_PROLOG(DECREMENTER); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) lis r0,TSR_DIS@h; /* Setup the DEC interrupt mask */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) mtspr SPRN_TSR,r0; /* Clear the DEC interrupt */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) addi r3,r1,STACK_FRAME_OVERHEAD; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) EXC_XFER_LITE(0x0900, timer_interrupt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define FP_UNAVAILABLE_EXCEPTION \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) START_EXCEPTION(FloatingPointUnavailable) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) NORMAL_EXCEPTION_PROLOG(FP_UNAVAIL); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) beq 1f; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) bl load_up_fpu; /* if from user, just load it up */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) b fast_exception_return; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 1: addi r3,r1,STACK_FRAME_OVERHEAD; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) EXC_XFER_STD(0x800, kernel_fp_unavailable_exception)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #else /* __ASSEMBLY__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) struct exception_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) unsigned long mas0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) unsigned long mas1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) unsigned long mas2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) unsigned long mas3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) unsigned long mas6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) unsigned long mas7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) unsigned long srr0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) unsigned long srr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) unsigned long csrr0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) unsigned long csrr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) unsigned long dsrr0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) unsigned long dsrr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) unsigned long saved_ksp_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /* ensure this structure is always sized to a multiple of the stack alignment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define STACK_EXC_LVL_FRAME_SIZE ALIGN(sizeof (struct exception_regs), 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #endif /* __ASSEMBLY__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #endif /* __HEAD_BOOKE_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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