^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * PowerPC version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Low-level exception handlers and MMU support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * rewritten by Paul Mackerras.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 1996 Paul Mackerras.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * MPC8xx modifications by Dan Malek
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * This file contains low-level support and setup for PowerPC 8xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * embedded processors, including trap and interrupt dispatch.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/magic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/pgtable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/sizes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/processor.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/mmu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/cache.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/cputable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/thread_info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <asm/ppc_asm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <asm/asm-offsets.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <asm/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <asm/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <asm/code-patching-asm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include "head_32.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .macro compare_to_kernel_boundary scratch, addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #if CONFIG_TASK_SIZE <= 0x80000000 && CONFIG_PAGE_OFFSET >= 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* By simply checking Address >= 0x80000000, we know if its a kernel address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) not. \scratch, \addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) rlwinm \scratch, \addr, 16, 0xfff8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) cmpli cr0, \scratch, PAGE_OFFSET@h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * We need an ITLB miss handler for kernel addresses if:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * - Either we have modules
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * - Or we have not pinned the first 8M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #if defined(CONFIG_MODULES) || !defined(CONFIG_PIN_TLB_TEXT) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) defined(CONFIG_DEBUG_PAGEALLOC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define ITLB_MISS_KERNEL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * Value for the bits that have fixed value in RPN entries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * Also used for tagging DAR for DTLBerror.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define RPN_PATTERN 0x00f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define PAGE_SHIFT_512K 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define PAGE_SHIFT_8M 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) __HEAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) _ENTRY(_stext);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) _ENTRY(_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* MPC8xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * This port was done on an MBX board with an 860. Right now I only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * support an ELF compressed (zImage) boot from EPPC-Bug because the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * code there loads up some registers before calling us:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * r3: ptr to board info data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * r4: initrd_start or if no initrd then 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * r5: initrd_end - unused if r4 is 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * r6: Start of command line string
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * r7: End of command line string
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * I decided to use conditional compilation instead of checking PVR and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * adding more processor specific branches around code I don't need.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * Since this is an embedded processor, I also appreciate any memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * savings I can get.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * The MPC8xx does not have any BATs, but it supports large page sizes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * We first initialize the MMU to support 8M byte pages, then load one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * entry into each of the instruction and data TLBs to map the first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * 8M 1:1. I also mapped an additional I/O space 1:1 so we can get to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * the "internal" processor registers before MMU_init is called.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * -- Dan
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .globl __start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) __start:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) mr r31,r3 /* save device tree ptr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* We have to turn on the MMU right away so we get cache modes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * set correctly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) bl initial_mmu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* We now have the lower 8 Meg mapped into TLB entries, and the caches
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * ready to work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) turn_on_mmu:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) mfmsr r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) ori r0,r0,MSR_DR|MSR_IR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) mtspr SPRN_SRR1,r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) lis r0,start_here@h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) ori r0,r0,start_here@l
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) mtspr SPRN_SRR0,r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) rfi /* enables MMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #ifdef CONFIG_PERF_EVENTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .align 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .globl itlb_miss_counter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) itlb_miss_counter:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .space 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .globl dtlb_miss_counter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) dtlb_miss_counter:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .space 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .globl instruction_counter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) instruction_counter:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .space 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* System reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) EXCEPTION(0x100, Reset, system_reset_exception, EXC_XFER_STD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* Machine check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) . = 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) MachineCheck:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) EXCEPTION_PROLOG handle_dar_dsisr=1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) save_dar_dsisr_on_stack r4, r5, r11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) li r6, RPN_PATTERN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) mtspr SPRN_DAR, r6 /* Tag DAR, to be used in DTLB Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) addi r3,r1,STACK_FRAME_OVERHEAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) EXC_XFER_STD(0x200, machine_check_exception)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* External interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* Alignment exception */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) . = 0x600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) Alignment:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) EXCEPTION_PROLOG handle_dar_dsisr=1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) save_dar_dsisr_on_stack r4, r5, r11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) li r6, RPN_PATTERN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) mtspr SPRN_DAR, r6 /* Tag DAR, to be used in DTLB Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) addi r3,r1,STACK_FRAME_OVERHEAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) b .Lalignment_exception_ool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* Program check exception */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) EXCEPTION(0x700, ProgramCheck, program_check_exception, EXC_XFER_STD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* Decrementer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* With VMAP_STACK there's not enough room for this at 0x600 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) . = 0xa00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .Lalignment_exception_ool:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) EXC_XFER_STD(0x600, alignment_exception)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* System call */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) . = 0xc00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) SystemCall:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) SYSCALL_ENTRY 0xc00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* Single step - not used on 601 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) EXCEPTION(0xd00, SingleStep, single_step_exception, EXC_XFER_STD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* On the MPC8xx, this is a software emulation interrupt. It occurs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * for all unimplemented and illegal instructions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) EXCEPTION(0x1000, SoftEmu, emulation_assist_interrupt, EXC_XFER_STD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) . = 0x1100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * For the MPC8xx, this is a software tablewalk to load the instruction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * TLB. The task switch loads the M_TWB register with the pointer to the first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * level table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * If we discover there is no second level table (value is zero) or if there
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * is an invalid pte, we load that into the TLB, which causes another fault
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * into the TLB Error interrupt where we can handle such problems.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * We have to use the MD_xxx registers for the tablewalk because the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * equivalent MI_xxx registers only perform the attribute functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #ifdef CONFIG_8xx_CPU15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define INVALIDATE_ADJACENT_PAGES_CPU15(addr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) addi addr, addr, PAGE_SIZE; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) tlbie addr; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) addi addr, addr, -(PAGE_SIZE << 1); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) tlbie addr; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) addi addr, addr, PAGE_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define INVALIDATE_ADJACENT_PAGES_CPU15(addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) InstructionTLBMiss:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) mtspr SPRN_SPRG_SCRATCH0, r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) mtspr SPRN_SPRG_SCRATCH1, r11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* If we are faulting a kernel address, we have to use the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * kernel page tables.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) mfspr r10, SPRN_SRR0 /* Get effective address of fault */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) INVALIDATE_ADJACENT_PAGES_CPU15(r10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) mtspr SPRN_MD_EPN, r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #ifdef ITLB_MISS_KERNEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) mfcr r11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) compare_to_kernel_boundary r10, r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) mfspr r10, SPRN_M_TWB /* Get level 1 table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #ifdef ITLB_MISS_KERNEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) blt+ 3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) rlwinm r10, r10, 0, 20, 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) oris r10, r10, (swapper_pg_dir - PAGE_OFFSET)@ha
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) mtcr r11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r10) /* Get level 1 entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) mtspr SPRN_MD_TWC, r11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) mfspr r10, SPRN_MD_TWC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) lwz r10, 0(r10) /* Get the pte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) rlwimi r11, r10, 0, _PAGE_GUARDED | _PAGE_ACCESSED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) rlwimi r11, r10, 32 - 9, _PMD_PAGE_512K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) mtspr SPRN_MI_TWC, r11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* The Linux PTE won't go exactly into the MMU TLB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * Software indicator bits 20 and 23 must be clear.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * Software indicator bits 22, 24, 25, 26, and 27 must be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * set. All other Linux PTE bits control the behavior
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * of the MMU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) rlwinm r10, r10, 0, ~0x0f00 /* Clear bits 20-23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) rlwimi r10, r10, 4, 0x0400 /* Copy _PAGE_EXEC into bit 21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) ori r10, r10, RPN_PATTERN | 0x200 /* Set 22 and 24-27 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) mtspr SPRN_MI_RPN, r10 /* Update TLB entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* Restore registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 0: mfspr r10, SPRN_SPRG_SCRATCH0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) mfspr r11, SPRN_SPRG_SCRATCH1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) rfi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) patch_site 0b, patch__itlbmiss_exit_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #ifdef CONFIG_PERF_EVENTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) patch_site 0f, patch__itlbmiss_perf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 0: lwz r10, (itlb_miss_counter - PAGE_OFFSET)@l(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) addi r10, r10, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) stw r10, (itlb_miss_counter - PAGE_OFFSET)@l(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) mfspr r10, SPRN_SPRG_SCRATCH0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) mfspr r11, SPRN_SPRG_SCRATCH1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) rfi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) . = 0x1200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) DataStoreTLBMiss:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) mtspr SPRN_DAR, r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) mtspr SPRN_M_TW, r11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) mfcr r11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* If we are faulting a kernel address, we have to use the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * kernel page tables.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) mfspr r10, SPRN_MD_EPN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) compare_to_kernel_boundary r10, r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) mfspr r10, SPRN_M_TWB /* Get level 1 table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) blt+ 3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) rlwinm r10, r10, 0, 20, 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) oris r10, r10, (swapper_pg_dir - PAGE_OFFSET)@ha
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) mtcr r11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r10) /* Get level 1 entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) mtspr SPRN_MD_TWC, r11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) mfspr r10, SPRN_MD_TWC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) lwz r10, 0(r10) /* Get the pte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* Insert Guarded and Accessed flags into the TWC from the Linux PTE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * It is bit 27 of both the Linux PTE and the TWC (at least
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * I got that right :-). It will be better when we can put
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * this into the Linux pgd/pmd and load it in the operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * above.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) rlwimi r11, r10, 0, _PAGE_GUARDED | _PAGE_ACCESSED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) rlwimi r11, r10, 32 - 9, _PMD_PAGE_512K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) mtspr SPRN_MD_TWC, r11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* The Linux PTE won't go exactly into the MMU TLB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * Software indicator bits 24, 25, 26, and 27 must be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * set. All other Linux PTE bits control the behavior
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * of the MMU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) li r11, RPN_PATTERN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) rlwimi r10, r11, 0, 24, 27 /* Set 24-27 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) mtspr SPRN_MD_RPN, r10 /* Update TLB entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* Restore registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 0: mfspr r10, SPRN_DAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) mtspr SPRN_DAR, r11 /* Tag DAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) mfspr r11, SPRN_M_TW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) rfi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) patch_site 0b, patch__dtlbmiss_exit_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #ifdef CONFIG_PERF_EVENTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) patch_site 0f, patch__dtlbmiss_perf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 0: lwz r10, (dtlb_miss_counter - PAGE_OFFSET)@l(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) addi r10, r10, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) stw r10, (dtlb_miss_counter - PAGE_OFFSET)@l(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) mfspr r10, SPRN_DAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) mtspr SPRN_DAR, r11 /* Tag DAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) mfspr r11, SPRN_M_TW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) rfi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* This is an instruction TLB error on the MPC8xx. This could be due
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * to many reasons, such as executing guarded memory or illegal instruction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * addresses. There is nothing to do but handle a big time error fault.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) . = 0x1300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) InstructionTLBError:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) EXCEPTION_PROLOG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) mr r4,r12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) andis. r5,r9,DSISR_SRR1_MATCH_32S@h /* Filter relevant SRR1 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) andis. r10,r9,SRR1_ISI_NOPT@h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) beq+ .Litlbie
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) tlbie r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /* 0x400 is InstructionAccess exception, needed by bad_page_fault() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .Litlbie:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) stw r4, _DAR(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) EXC_XFER_LITE(0x400, handle_page_fault)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* This is the data TLB error on the MPC8xx. This could be due to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * many reasons, including a dirty update to a pte. We bail out to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * a higher level function that can handle it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) . = 0x1400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) DataTLBError:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) EXCEPTION_PROLOG_0 handle_dar_dsisr=1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) mfspr r11, SPRN_DAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) cmpwi cr1, r11, RPN_PATTERN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) beq- cr1, FixupDAR /* must be a buggy dcbX, icbi insn. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) DARFixed:/* Return from dcbx instruction bug workaround */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #ifdef CONFIG_VMAP_STACK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) li r11, RPN_PATTERN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) mtspr SPRN_DAR, r11 /* Tag DAR, to be used in DTLB Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) EXCEPTION_PROLOG_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) EXCEPTION_PROLOG_2 handle_dar_dsisr=1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) get_and_save_dar_dsisr_on_stack r4, r5, r11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) andis. r10,r5,DSISR_NOHPTE@h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) beq+ .Ldtlbie
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) tlbie r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .Ldtlbie:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #ifndef CONFIG_VMAP_STACK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) li r10,RPN_PATTERN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) mtspr SPRN_DAR,r10 /* Tag DAR, to be used in DTLB Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /* 0x300 is DataAccess exception, needed by bad_page_fault() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) EXC_XFER_LITE(0x300, handle_page_fault)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) stack_overflow:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) vmap_stack_overflow_exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /* On the MPC8xx, these next four traps are used for development
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * support of breakpoints and such. Someday I will get around to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) * using them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) do_databreakpoint:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) EXCEPTION_PROLOG_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) EXCEPTION_PROLOG_2 handle_dar_dsisr=1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) addi r3,r1,STACK_FRAME_OVERHEAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) mfspr r4,SPRN_BAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) stw r4,_DAR(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #ifdef CONFIG_VMAP_STACK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) lwz r5,_DSISR(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) mfspr r5,SPRN_DSISR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) EXC_XFER_STD(0x1c00, do_break)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) . = 0x1c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) DataBreakpoint:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) EXCEPTION_PROLOG_0 handle_dar_dsisr=1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) mfspr r11, SPRN_SRR0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) cmplwi cr1, r11, (.Ldtlbie - PAGE_OFFSET)@l
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) cmplwi cr7, r11, (.Litlbie - PAGE_OFFSET)@l
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) cror 4*cr1+eq, 4*cr1+eq, 4*cr7+eq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) bne cr1, do_databreakpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) mtcr r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) mfspr r10, SPRN_SPRG_SCRATCH0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) mfspr r11, SPRN_SPRG_SCRATCH1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) rfi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #ifdef CONFIG_PERF_EVENTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) . = 0x1d00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) InstructionBreakpoint:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) mtspr SPRN_SPRG_SCRATCH0, r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) lwz r10, (instruction_counter - PAGE_OFFSET)@l(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) addi r10, r10, -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) stw r10, (instruction_counter - PAGE_OFFSET)@l(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) lis r10, 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) ori r10, r10, 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) mtspr SPRN_COUNTA, r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) mfspr r10, SPRN_SPRG_SCRATCH0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) rfi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_STD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_STD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_STD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) . = 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /* This is the procedure to calculate the data EA for buggy dcbx,dcbi instructions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) * by decoding the registers used by the dcbx instruction and adding them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) * DAR is set to the calculated address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) FixupDAR:/* Entry point for dcbx workaround. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) mtspr SPRN_M_TW, r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /* fetch instruction from memory. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) mfspr r10, SPRN_SRR0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) mtspr SPRN_MD_EPN, r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) rlwinm r11, r10, 16, 0xfff8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) cmpli cr1, r11, PAGE_OFFSET@h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) mfspr r11, SPRN_M_TWB /* Get level 1 table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) blt+ cr1, 3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) /* create physical page address from effective address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) tophys(r11, r10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) mfspr r11, SPRN_M_TWB /* Get level 1 table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) rlwinm r11, r11, 0, 20, 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) oris r11, r11, (swapper_pg_dir - PAGE_OFFSET)@ha
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11) /* Get the level 1 entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) mtspr SPRN_MD_TWC, r11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) mtcrf 0x01, r11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) mfspr r11, SPRN_MD_TWC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) lwz r11, 0(r11) /* Get the pte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) bt 28,200f /* bit 28 = Large page (8M) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) /* concat physical page address(r11) and page offset(r10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) rlwimi r11, r10, 0, 32 - PAGE_SHIFT, 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 201: lwz r11,0(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /* Check if it really is a dcbx instruction. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) /* dcbt and dcbtst does not generate DTLB Misses/Errors,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) * no need to include them here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) xoris r10, r11, 0x7c00 /* check if major OP code is 31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) rlwinm r10, r10, 0, 21, 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) cmpwi cr1, r10, 2028 /* Is dcbz? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) beq+ cr1, 142f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) cmpwi cr1, r10, 940 /* Is dcbi? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) beq+ cr1, 142f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) cmpwi cr1, r10, 108 /* Is dcbst? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) beq+ cr1, 144f /* Fix up store bit! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) cmpwi cr1, r10, 172 /* Is dcbf? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) beq+ cr1, 142f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) cmpwi cr1, r10, 1964 /* Is icbi? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) beq+ cr1, 142f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 141: mfspr r10,SPRN_M_TW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) b DARFixed /* Nope, go back to normal TLB processing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 200:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) /* concat physical page address(r11) and page offset(r10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) rlwimi r11, r10, 0, 32 - PAGE_SHIFT_8M, 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) b 201b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 144: mfspr r10, SPRN_DSISR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) rlwinm r10, r10,0,7,5 /* Clear store bit for buggy dcbst insn */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) mtspr SPRN_DSISR, r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 142: /* continue, it was a dcbx, dcbi instruction. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) mfctr r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) mtdar r10 /* save ctr reg in DAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) rlwinm r10, r11, 24, 24, 28 /* offset into jump table for reg RB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) addi r10, r10, 150f@l /* add start of table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) mtctr r10 /* load ctr with jump address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) xor r10, r10, r10 /* sum starts at zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) bctr /* jump into table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 150:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) add r10, r10, r0 ;b 151f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) add r10, r10, r1 ;b 151f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) add r10, r10, r2 ;b 151f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) add r10, r10, r3 ;b 151f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) add r10, r10, r4 ;b 151f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) add r10, r10, r5 ;b 151f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) add r10, r10, r6 ;b 151f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) add r10, r10, r7 ;b 151f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) add r10, r10, r8 ;b 151f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) add r10, r10, r9 ;b 151f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) mtctr r11 ;b 154f /* r10 needs special handling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) mtctr r11 ;b 153f /* r11 needs special handling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) add r10, r10, r12 ;b 151f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) add r10, r10, r13 ;b 151f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) add r10, r10, r14 ;b 151f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) add r10, r10, r15 ;b 151f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) add r10, r10, r16 ;b 151f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) add r10, r10, r17 ;b 151f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) add r10, r10, r18 ;b 151f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) add r10, r10, r19 ;b 151f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) add r10, r10, r20 ;b 151f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) add r10, r10, r21 ;b 151f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) add r10, r10, r22 ;b 151f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) add r10, r10, r23 ;b 151f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) add r10, r10, r24 ;b 151f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) add r10, r10, r25 ;b 151f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) add r10, r10, r26 ;b 151f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) add r10, r10, r27 ;b 151f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) add r10, r10, r28 ;b 151f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) add r10, r10, r29 ;b 151f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) add r10, r10, r30 ;b 151f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) add r10, r10, r31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 151:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) rlwinm r11,r11,19,24,28 /* offset into jump table for reg RA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) cmpwi cr1, r11, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) beq cr1, 152f /* if reg RA is zero, don't add it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) addi r11, r11, 150b@l /* add start of table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) mtctr r11 /* load ctr with jump address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) rlwinm r11,r11,0,16,10 /* make sure we don't execute this more than once */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) bctr /* jump into table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 152:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) mfdar r11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) mtctr r11 /* restore ctr reg from DAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #ifdef CONFIG_VMAP_STACK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) mfspr r11, SPRN_SPRG_THREAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) stw r10, DAR(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) mfspr r10, SPRN_DSISR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) stw r10, DSISR(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) mtdar r10 /* save fault EA to DAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) mfspr r10,SPRN_M_TW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) b DARFixed /* Go back to normal TLB handling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) /* special handling for r10,r11 since these are modified already */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 153: mfspr r11, SPRN_SPRG_SCRATCH1 /* load r11 from SPRN_SPRG_SCRATCH1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) add r10, r10, r11 /* add it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) mfctr r11 /* restore r11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) b 151b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 154: mfspr r11, SPRN_SPRG_SCRATCH0 /* load r10 from SPRN_SPRG_SCRATCH0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) add r10, r10, r11 /* add it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) mfctr r11 /* restore r11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) b 151b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) * This is where the main kernel code starts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) start_here:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) /* ptr to current */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) lis r2,init_task@h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) ori r2,r2,init_task@l
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) /* ptr to phys current thread */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) tophys(r4,r2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) addi r4,r4,THREAD /* init task's THREAD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) mtspr SPRN_SPRG_THREAD,r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) /* stack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) lis r1,init_thread_union@ha
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) addi r1,r1,init_thread_union@l
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) lis r0, STACK_END_MAGIC@h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) ori r0, r0, STACK_END_MAGIC@l
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) stw r0, 0(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) li r0,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) lis r6, swapper_pg_dir@ha
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) tophys(r6,r6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) mtspr SPRN_M_TWB, r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) bl early_init /* We have to do this with MMU on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) * Decide what sort of machine this is and initialize the MMU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #ifdef CONFIG_KASAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) bl kasan_early_init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) li r3,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) mr r4,r31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) bl machine_init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) bl MMU_init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) * Go back to running unmapped so we can load up new values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) * and change to using our exception vectors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) * On the 8xx, all we have to do is invalidate the TLB to clear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) * the old 8M byte TLB mappings and load the page table base register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) /* The right way to do this would be to track it down through
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) * init's THREAD like the context switch code does, but this is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) * easier......until someone changes init's static structures.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) lis r4,2f@h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) ori r4,r4,2f@l
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) tophys(r4,r4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) mtspr SPRN_SRR0,r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) mtspr SPRN_SRR1,r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) rfi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) /* Load up the kernel context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #ifdef CONFIG_PIN_TLB_IMMR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) lis r0, MD_TWAM@h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) oris r0, r0, 0x1f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) mtspr SPRN_MD_CTR, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) LOAD_REG_IMMEDIATE(r0, VIRT_IMMR_BASE | MD_EVALID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) tlbie r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) mtspr SPRN_MD_EPN, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) LOAD_REG_IMMEDIATE(r0, MD_SVALID | MD_PS512K | MD_GUARDED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) mtspr SPRN_MD_TWC, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) mfspr r0, SPRN_IMMR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) rlwinm r0, r0, 0, 0xfff80000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) ori r0, r0, 0xf0 | _PAGE_DIRTY | _PAGE_SPS | _PAGE_SH | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) _PAGE_NO_CACHE | _PAGE_PRESENT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) mtspr SPRN_MD_RPN, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) lis r0, (MD_TWAM | MD_RSV4I)@h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) mtspr SPRN_MD_CTR, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #ifndef CONFIG_PIN_TLB_TEXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) li r0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) mtspr SPRN_MI_CTR, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #if !defined(CONFIG_PIN_TLB_DATA) && !defined(CONFIG_PIN_TLB_IMMR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) lis r0, MD_TWAM@h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) mtspr SPRN_MD_CTR, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) tlbia /* Clear all TLB entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) sync /* wait for tlbia/tlbie to finish */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) /* set up the PTE pointers for the Abatron bdiGDB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) lis r5, abatron_pteptrs@h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) ori r5, r5, abatron_pteptrs@l
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) stw r5, 0xf0(0) /* Must match your Abatron config file */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) tophys(r5,r5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) lis r6, swapper_pg_dir@h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) ori r6, r6, swapper_pg_dir@l
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) stw r6, 0(r5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) /* Now turn on the MMU for real! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) li r4,MSR_KERNEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) lis r3,start_kernel@h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) ori r3,r3,start_kernel@l
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) mtspr SPRN_SRR0,r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) mtspr SPRN_SRR1,r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) rfi /* enable MMU and jump to start_kernel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) /* Set up the initial MMU state so we can do the first level of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) * kernel initialization. This maps the first 8 MBytes of memory 1:1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) * virtual to physical. Also, set the cache mode since that is defined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) * by TLB entries and perform any additional mapping (like of the IMMR).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) * If configured to pin some TLBs, we pin the first 8 Mbytes of kernel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) * 24 Mbytes of data, and the 512k IMMR space. Anything not covered by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) * these mappings is mapped by page tables.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) initial_mmu:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) li r8, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) mtspr SPRN_MI_CTR, r8 /* remove PINNED ITLB entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) lis r10, MD_TWAM@h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) mtspr SPRN_MD_CTR, r10 /* remove PINNED DTLB entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) tlbia /* Invalidate all TLB entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) lis r8, MI_APG_INIT@h /* Set protection modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) ori r8, r8, MI_APG_INIT@l
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) mtspr SPRN_MI_AP, r8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) lis r8, MD_APG_INIT@h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) ori r8, r8, MD_APG_INIT@l
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) mtspr SPRN_MD_AP, r8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) /* Map the lower RAM (up to 32 Mbytes) into the ITLB and DTLB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) lis r8, MI_RSV4I@h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) ori r8, r8, 0x1c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) oris r12, r10, MD_RSV4I@h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) ori r12, r12, 0x1c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) li r9, 4 /* up to 4 pages of 8M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) mtctr r9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) lis r9, KERNELBASE@h /* Create vaddr for TLB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) li r10, MI_PS8MEG | _PMD_ACCESSED | MI_SVALID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) li r11, MI_BOOTINIT /* Create RPN for address 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) mtspr SPRN_MI_CTR, r8 /* Set instruction MMU control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) addi r8, r8, 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) ori r0, r9, MI_EVALID /* Mark it valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) mtspr SPRN_MI_EPN, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) mtspr SPRN_MI_TWC, r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) mtspr SPRN_MI_RPN, r11 /* Store TLB entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) mtspr SPRN_MD_CTR, r12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) addi r12, r12, 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) mtspr SPRN_MD_EPN, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) mtspr SPRN_MD_TWC, r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) mtspr SPRN_MD_RPN, r11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) addis r9, r9, 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) addis r11, r11, 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) bdnz 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) /* Since the cache is enabled according to the information we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) * just loaded into the TLB, invalidate and enable the caches here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) * We should probably check/set other modes....later.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) lis r8, IDC_INVALL@h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) mtspr SPRN_IC_CST, r8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) mtspr SPRN_DC_CST, r8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) lis r8, IDC_ENABLE@h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) mtspr SPRN_IC_CST, r8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) mtspr SPRN_DC_CST, r8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) /* Disable debug mode entry on breakpoints */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) mfspr r8, SPRN_DER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) #ifdef CONFIG_PERF_EVENTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) rlwinm r8, r8, 0, ~0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) rlwinm r8, r8, 0, ~0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) mtspr SPRN_DER, r8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) blr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) #ifdef CONFIG_PIN_TLB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) _GLOBAL(mmu_pin_tlb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) lis r9, (1f - PAGE_OFFSET)@h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) ori r9, r9, (1f - PAGE_OFFSET)@l
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) mfmsr r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) mflr r11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) li r12, MSR_KERNEL & ~(MSR_IR | MSR_DR | MSR_RI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) rlwinm r0, r10, 0, ~MSR_RI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) rlwinm r0, r0, 0, ~MSR_EE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) mtmsr r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) .align 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) mtspr SPRN_SRR0, r9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) mtspr SPRN_SRR1, r12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) rfi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) li r5, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) lis r6, MD_TWAM@h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) mtspr SPRN_MI_CTR, r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) mtspr SPRN_MD_CTR, r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) tlbia
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) #ifdef CONFIG_PIN_TLB_TEXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) LOAD_REG_IMMEDIATE(r5, 28 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) LOAD_REG_IMMEDIATE(r6, PAGE_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) LOAD_REG_IMMEDIATE(r7, MI_SVALID | MI_PS8MEG | _PMD_ACCESSED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) LOAD_REG_IMMEDIATE(r8, 0xf0 | _PAGE_RO | _PAGE_SPS | _PAGE_SH | _PAGE_PRESENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) LOAD_REG_ADDR(r9, _sinittext)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) li r0, 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) mtctr r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) 2: ori r0, r6, MI_EVALID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) mtspr SPRN_MI_CTR, r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) mtspr SPRN_MI_EPN, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) mtspr SPRN_MI_TWC, r7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) mtspr SPRN_MI_RPN, r8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) addi r5, r5, 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) addis r6, r6, SZ_8M@h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) addis r8, r8, SZ_8M@h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) cmplw r6, r9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) bdnzt lt, 2b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) lis r0, MI_RSV4I@h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) mtspr SPRN_MI_CTR, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) LOAD_REG_IMMEDIATE(r5, 28 << 8 | MD_TWAM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) #ifdef CONFIG_PIN_TLB_DATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) LOAD_REG_IMMEDIATE(r6, PAGE_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) LOAD_REG_IMMEDIATE(r7, MI_SVALID | MI_PS8MEG | _PMD_ACCESSED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) li r8, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) #ifdef CONFIG_PIN_TLB_IMMR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) li r0, 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) li r0, 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) mtctr r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) cmpwi r4, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) beq 4f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) LOAD_REG_ADDR(r9, _sinittext)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) 2: ori r0, r6, MD_EVALID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) ori r12, r8, 0xf0 | _PAGE_RO | _PAGE_SPS | _PAGE_SH | _PAGE_PRESENT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) mtspr SPRN_MD_CTR, r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) mtspr SPRN_MD_EPN, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) mtspr SPRN_MD_TWC, r7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) mtspr SPRN_MD_RPN, r12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) addi r5, r5, 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) addis r6, r6, SZ_8M@h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) addis r8, r8, SZ_8M@h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) cmplw r6, r9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) bdnzt lt, 2b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) 2: ori r0, r6, MD_EVALID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) ori r12, r8, 0xf0 | _PAGE_DIRTY | _PAGE_SPS | _PAGE_SH | _PAGE_PRESENT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) mtspr SPRN_MD_CTR, r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) mtspr SPRN_MD_EPN, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) mtspr SPRN_MD_TWC, r7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) mtspr SPRN_MD_RPN, r12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) addi r5, r5, 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) addis r6, r6, SZ_8M@h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) addis r8, r8, SZ_8M@h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) cmplw r6, r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) bdnzt lt, 2b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) #ifdef CONFIG_PIN_TLB_IMMR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) LOAD_REG_IMMEDIATE(r0, VIRT_IMMR_BASE | MD_EVALID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) LOAD_REG_IMMEDIATE(r7, MD_SVALID | MD_PS512K | MD_GUARDED | _PMD_ACCESSED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) mfspr r8, SPRN_IMMR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) rlwinm r8, r8, 0, 0xfff80000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) ori r8, r8, 0xf0 | _PAGE_DIRTY | _PAGE_SPS | _PAGE_SH | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) _PAGE_NO_CACHE | _PAGE_PRESENT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) mtspr SPRN_MD_CTR, r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) mtspr SPRN_MD_EPN, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) mtspr SPRN_MD_TWC, r7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) mtspr SPRN_MD_RPN, r8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) #if defined(CONFIG_PIN_TLB_IMMR) || defined(CONFIG_PIN_TLB_DATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) lis r0, (MD_RSV4I | MD_TWAM)@h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) mtspr SPRN_MD_CTR, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) mtspr SPRN_SRR1, r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) mtspr SPRN_SRR0, r11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) rfi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) #endif /* CONFIG_PIN_TLB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) * We put a few things here that have to be page-aligned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) * This stuff goes at the beginning of the data segment,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) * which is page-aligned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) .data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) .globl sdata
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) sdata:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) .globl empty_zero_page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) .align PAGE_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) empty_zero_page:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) .space PAGE_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) EXPORT_SYMBOL(empty_zero_page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) .globl swapper_pg_dir
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) swapper_pg_dir:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) .space PGD_TABLE_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) /* Room for two PTE table poiners, usually the kernel and current user
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) * pointer to their respective root page table (pgdir).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) .globl abatron_pteptrs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) abatron_pteptrs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) .space 8
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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