Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) #ifndef __HEAD_32_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) #define __HEAD_32_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) #include <asm/ptrace.h>	/* for STACK_FRAME_REGS_MARKER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Exception entry code.  This code runs with address translation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * turned off, i.e. using physical addresses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * We assume sprg3 has the physical address of the current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * task's thread_struct.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) .macro EXCEPTION_PROLOG handle_dar_dsisr=0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 	EXCEPTION_PROLOG_0	handle_dar_dsisr=\handle_dar_dsisr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 	EXCEPTION_PROLOG_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 	EXCEPTION_PROLOG_2	handle_dar_dsisr=\handle_dar_dsisr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) .macro EXCEPTION_PROLOG_0 handle_dar_dsisr=0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	mtspr	SPRN_SPRG_SCRATCH0,r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	mtspr	SPRN_SPRG_SCRATCH1,r11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #ifdef CONFIG_VMAP_STACK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	mfspr	r10, SPRN_SPRG_THREAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	.if	\handle_dar_dsisr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	mfspr	r11, SPRN_DAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	stw	r11, DAR(r10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	mfspr	r11, SPRN_DSISR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	stw	r11, DSISR(r10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	.endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	mfspr	r11, SPRN_SRR0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	stw	r11, SRR0(r10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	mfspr	r11, SPRN_SRR1		/* check whether user or kernel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #ifdef CONFIG_VMAP_STACK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	stw	r11, SRR1(r10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	mfcr	r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	andi.	r11, r11, MSR_PR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) .macro EXCEPTION_PROLOG_1 for_rtas=0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #ifdef CONFIG_VMAP_STACK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	mr	r11, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	subi	r1, r1, INT_FRAME_SIZE		/* use r1 if kernel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	beq	1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	mfspr	r1,SPRN_SPRG_THREAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	lwz	r1,TASK_STACK-THREAD(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	addi	r1, r1, THREAD_SIZE - INT_FRAME_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	subi	r11, r1, INT_FRAME_SIZE		/* use r1 if kernel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	beq	1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	mfspr	r11,SPRN_SPRG_THREAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	lwz	r11,TASK_STACK-THREAD(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	addi	r11, r11, THREAD_SIZE - INT_FRAME_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	tophys_novmstack r11, r11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #ifdef CONFIG_VMAP_STACK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	mtcrf	0x3f, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	bt	32 - THREAD_ALIGN_SHIFT, stack_overflow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) .macro EXCEPTION_PROLOG_2 handle_dar_dsisr=0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #ifdef CONFIG_VMAP_STACK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	mtcr	r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	li	r10, MSR_KERNEL & ~(MSR_IR | MSR_RI) /* can take DTLB miss */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	mtmsr	r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	stw	r10,_CCR(r11)		/* save registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	mfspr	r10, SPRN_SPRG_SCRATCH0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #ifdef CONFIG_VMAP_STACK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	stw	r11,GPR1(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	stw	r11,0(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	mr	r11, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	stw	r1,GPR1(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	stw	r1,0(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	tovirt(r1, r11)		/* set new kernel sp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	stw	r12,GPR12(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	stw	r9,GPR9(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	stw	r10,GPR10(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #ifdef CONFIG_VMAP_STACK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	mfcr	r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	stw	r10, _CCR(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	mfspr	r12,SPRN_SPRG_SCRATCH1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	stw	r12,GPR11(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	mflr	r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	stw	r10,_LINK(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #ifdef CONFIG_VMAP_STACK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	mfspr	r12, SPRN_SPRG_THREAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	tovirt(r12, r12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	.if	\handle_dar_dsisr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	lwz	r10, DAR(r12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	stw	r10, _DAR(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	lwz	r10, DSISR(r12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	stw	r10, _DSISR(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	.endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	lwz	r9, SRR1(r12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	andi.	r10, r9, MSR_PR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	lwz	r12, SRR0(r12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	mfspr	r12,SPRN_SRR0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	mfspr	r9,SPRN_SRR1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #ifdef CONFIG_40x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	rlwinm	r9,r9,0,14,12		/* clear MSR_WE (necessary?) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #ifdef CONFIG_VMAP_STACK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	li	r10, MSR_KERNEL & ~MSR_IR /* can take exceptions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	li	r10,MSR_KERNEL & ~(MSR_IR|MSR_DR) /* can take exceptions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	mtmsr	r10			/* (except for mach check in rtas) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	stw	r0,GPR0(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	lis	r10,STACK_FRAME_REGS_MARKER@ha /* exception frame marker */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	addi	r10,r10,STACK_FRAME_REGS_MARKER@l
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	stw	r10,8(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	SAVE_4GPRS(3, r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	SAVE_2GPRS(7, r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .macro SYSCALL_ENTRY trapno
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	mfspr	r12,SPRN_SPRG_THREAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	mfspr	r9, SPRN_SRR1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #ifdef CONFIG_VMAP_STACK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	mfspr	r11, SPRN_SRR0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	mtctr	r11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	andi.	r11, r9, MSR_PR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	mr	r11, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	lwz	r1,TASK_STACK-THREAD(r12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	beq-	99f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	addi	r1, r1, THREAD_SIZE - INT_FRAME_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	li	r10, MSR_KERNEL & ~(MSR_IR | MSR_RI) /* can take DTLB miss */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	mtmsr	r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	tovirt(r12, r12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	stw	r11,GPR1(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	stw	r11,0(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	mr	r11, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	andi.	r11, r9, MSR_PR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	lwz	r11,TASK_STACK-THREAD(r12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	beq-	99f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	addi	r11, r11, THREAD_SIZE - INT_FRAME_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	tophys(r11, r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	stw	r1,GPR1(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	stw	r1,0(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	tovirt(r1, r11)		/* set new kernel sp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	mflr	r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	stw	r10, _LINK(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #ifdef CONFIG_VMAP_STACK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	mfctr	r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	mfspr	r10,SPRN_SRR0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	stw	r10,_NIP(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	mfcr	r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	rlwinm	r10,r10,0,4,2	/* Clear SO bit in CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	stw	r10,_CCR(r11)		/* save registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #ifdef CONFIG_40x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	rlwinm	r9,r9,0,14,12		/* clear MSR_WE (necessary?) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #ifdef CONFIG_VMAP_STACK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	LOAD_REG_IMMEDIATE(r10, MSR_KERNEL & ~MSR_IR) /* can take exceptions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	LOAD_REG_IMMEDIATE(r10, MSR_KERNEL & ~(MSR_IR|MSR_DR)) /* can take exceptions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	mtmsr	r10			/* (except for mach check in rtas) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	lis	r10,STACK_FRAME_REGS_MARKER@ha /* exception frame marker */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	stw	r2,GPR2(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	addi	r10,r10,STACK_FRAME_REGS_MARKER@l
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	stw	r9,_MSR(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	li	r2, \trapno + 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	stw	r10,8(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	stw	r2,_TRAP(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	SAVE_GPR(0, r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	SAVE_4GPRS(3, r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	SAVE_2GPRS(7, r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	addi	r11,r1,STACK_FRAME_OVERHEAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	addi	r2,r12,-THREAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	stw	r11,PT_REGS(r12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #if defined(CONFIG_40x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	/* Check to see if the dbcr0 register is set up to debug.  Use the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	   internal debug mode bit to do this. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	lwz	r12,THREAD_DBCR0(r12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	andis.	r12,r12,DBCR0_IDM@h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	ACCOUNT_CPU_USER_ENTRY(r2, r11, r12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #if defined(CONFIG_40x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	beq+	3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	/* From user and task is ptraced - load up global dbcr0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	li	r12,-1			/* clear all pending debug events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	mtspr	SPRN_DBSR,r12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	lis	r11,global_dbcr0@ha
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	tophys(r11,r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	addi	r11,r11,global_dbcr0@l
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	lwz	r12,0(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	mtspr	SPRN_DBCR0,r12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	lwz	r12,4(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	addi	r12,r12,-1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	stw	r12,4(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	tovirt_novmstack r2, r2 	/* set r2 to current */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	lis	r11, transfer_to_syscall@h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	ori	r11, r11, transfer_to_syscall@l
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #ifdef CONFIG_TRACE_IRQFLAGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	 * If MSR is changing we need to keep interrupts disabled at this point
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	 * otherwise we might risk taking an interrupt before we tell lockdep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	 * they are enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	LOAD_REG_IMMEDIATE(r10, MSR_KERNEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	rlwimi	r10, r9, 0, MSR_EE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	LOAD_REG_IMMEDIATE(r10, MSR_KERNEL | MSR_EE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #if defined(CONFIG_PPC_8xx) && defined(CONFIG_PERF_EVENTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	mtspr	SPRN_NRI, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	mtspr	SPRN_SRR1,r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	mtspr	SPRN_SRR0,r11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	RFI				/* jump to handler, enable MMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 99:	b	ret_from_kernel_syscall
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .macro save_dar_dsisr_on_stack reg1, reg2, sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #ifndef CONFIG_VMAP_STACK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	mfspr	\reg1, SPRN_DAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	mfspr	\reg2, SPRN_DSISR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	stw	\reg1, _DAR(\sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	stw	\reg2, _DSISR(\sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .macro get_and_save_dar_dsisr_on_stack reg1, reg2, sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #ifdef CONFIG_VMAP_STACK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	lwz	\reg1, _DAR(\sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	lwz	\reg2, _DSISR(\sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	save_dar_dsisr_on_stack \reg1, \reg2, \sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .macro tovirt_vmstack dst, src
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #ifdef CONFIG_VMAP_STACK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	tovirt(\dst, \src)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	.ifnc	\dst, \src
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	mr	\dst, \src
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	.endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .macro tovirt_novmstack dst, src
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #ifndef CONFIG_VMAP_STACK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	tovirt(\dst, \src)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	.ifnc	\dst, \src
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	mr	\dst, \src
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	.endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .macro tophys_novmstack dst, src
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #ifndef CONFIG_VMAP_STACK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	tophys(\dst, \src)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	.ifnc	\dst, \src
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	mr	\dst, \src
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	.endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)  * Note: code which follows this uses cr0.eq (set if from kernel),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)  * r11, r12 (SRR0), and r9 (SRR1).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)  * Note2: once we have set r1 we are in a position to take exceptions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)  * again, and we could thus set MSR:RI at that point.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)  * Exception vectors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #ifdef CONFIG_PPC_BOOK3S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define	START_EXCEPTION(n, label)		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	. = n;					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	DO_KVM n;				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) label:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define	START_EXCEPTION(n, label)		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	. = n;					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) label:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define EXCEPTION(n, label, hdlr, xfer)		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	START_EXCEPTION(n, label)		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	EXCEPTION_PROLOG;			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	addi	r3,r1,STACK_FRAME_OVERHEAD;	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	xfer(n, hdlr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define EXC_XFER_TEMPLATE(hdlr, trap, msr, tfer, ret)		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	li	r10,trap;					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	stw	r10,_TRAP(r11);					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	LOAD_REG_IMMEDIATE(r10, msr);				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	bl	tfer;						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	.long	hdlr;						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	.long	ret
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define EXC_XFER_STD(n, hdlr)		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, transfer_to_handler_full,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 			  ret_from_except_full)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define EXC_XFER_LITE(n, hdlr)		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, transfer_to_handler, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 			  ret_from_except)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .macro vmap_stack_overflow_exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #ifdef CONFIG_VMAP_STACK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	mfspr	r1, SPRN_SPRG_THREAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	lwz	r1, TASK_CPU - THREAD(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	slwi	r1, r1, 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	addis	r1, r1, emergency_ctx-PAGE_OFFSET@ha
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	lis	r1, emergency_ctx-PAGE_OFFSET@ha
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	lwz	r1, emergency_ctx-PAGE_OFFSET@l(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	addi	r1, r1, THREAD_SIZE - INT_FRAME_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	EXCEPTION_PROLOG_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	SAVE_NVGPRS(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	addi	r3, r1, STACK_FRAME_OVERHEAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	EXC_XFER_STD(0, stack_overflow_exception)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #endif /* __HEAD_32_H__ */