^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Boot code and exception vectors for Book3E processors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2007 Ben. Herrenschmidt (benh@kernel.crashing.org), IBM Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/threads.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <asm/reg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/ppc_asm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/asm-offsets.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/cputable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/setup.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/thread_info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/reg_a2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/exception-64e.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/bug.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/irqflags.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/ppc-opcode.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/mmu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/hw_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/kvm_asm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/kvm_booke_hv_asm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/feature-fixups.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <asm/context_tracking.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* XXX This will ultimately add space for a special exception save
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * structure used to save things like SRR0/SRR1, SPRGs, MAS, etc...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * when taking special interrupts. For now we don't support that,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * special interrupts from within a non-standard level will probably
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * blow you up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SPECIAL_EXC_SRR0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SPECIAL_EXC_SRR1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SPECIAL_EXC_SPRG_GEN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SPECIAL_EXC_SPRG_TLB 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SPECIAL_EXC_MAS0 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SPECIAL_EXC_MAS1 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SPECIAL_EXC_MAS2 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SPECIAL_EXC_MAS3 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SPECIAL_EXC_MAS6 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SPECIAL_EXC_MAS7 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SPECIAL_EXC_MAS5 10 /* E.HV only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SPECIAL_EXC_MAS8 11 /* E.HV only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SPECIAL_EXC_IRQHAPPENED 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SPECIAL_EXC_DEAR 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SPECIAL_EXC_ESR 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SPECIAL_EXC_SOFTE 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SPECIAL_EXC_CSRR0 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SPECIAL_EXC_CSRR1 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* must be even to keep 16-byte stack alignment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SPECIAL_EXC_END 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SPECIAL_EXC_FRAME_SIZE (INT_FRAME_SIZE + SPECIAL_EXC_END * 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SPECIAL_EXC_FRAME_OFFS (INT_FRAME_SIZE - 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SPECIAL_EXC_STORE(reg, name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) std reg, (SPECIAL_EXC_##name * 8 + SPECIAL_EXC_FRAME_OFFS)(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SPECIAL_EXC_LOAD(reg, name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) ld reg, (SPECIAL_EXC_##name * 8 + SPECIAL_EXC_FRAME_OFFS)(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) special_reg_save:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) lbz r9,PACAIRQHAPPENED(r13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) RECONCILE_IRQ_STATE(r3,r4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * We only need (or have stack space) to save this stuff if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * we interrupted the kernel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) ld r3,_MSR(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) andi. r3,r3,MSR_PR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) bnelr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * Advance to the next TLB exception frame for handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * types that don't do it automatically.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) LOAD_REG_ADDR(r11,extlb_level_exc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) lwz r12,0(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) mfspr r10,SPRN_SPRG_TLB_EXFRAME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) add r10,r10,r12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) mtspr SPRN_SPRG_TLB_EXFRAME,r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * Save registers needed to allow nesting of certain exceptions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * (such as TLB misses) inside special exception levels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) mfspr r10,SPRN_SRR0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) SPECIAL_EXC_STORE(r10,SRR0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) mfspr r10,SPRN_SRR1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) SPECIAL_EXC_STORE(r10,SRR1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) mfspr r10,SPRN_SPRG_GEN_SCRATCH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) SPECIAL_EXC_STORE(r10,SPRG_GEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) mfspr r10,SPRN_SPRG_TLB_SCRATCH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) SPECIAL_EXC_STORE(r10,SPRG_TLB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) mfspr r10,SPRN_MAS0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) SPECIAL_EXC_STORE(r10,MAS0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) mfspr r10,SPRN_MAS1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) SPECIAL_EXC_STORE(r10,MAS1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) mfspr r10,SPRN_MAS2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) SPECIAL_EXC_STORE(r10,MAS2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) mfspr r10,SPRN_MAS3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) SPECIAL_EXC_STORE(r10,MAS3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) mfspr r10,SPRN_MAS6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) SPECIAL_EXC_STORE(r10,MAS6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) mfspr r10,SPRN_MAS7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) SPECIAL_EXC_STORE(r10,MAS7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) BEGIN_FTR_SECTION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) mfspr r10,SPRN_MAS5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) SPECIAL_EXC_STORE(r10,MAS5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) mfspr r10,SPRN_MAS8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) SPECIAL_EXC_STORE(r10,MAS8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* MAS5/8 could have inappropriate values if we interrupted KVM code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) li r10,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) mtspr SPRN_MAS5,r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) mtspr SPRN_MAS8,r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) SPECIAL_EXC_STORE(r9,IRQHAPPENED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) mfspr r10,SPRN_DEAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) SPECIAL_EXC_STORE(r10,DEAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) mfspr r10,SPRN_ESR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) SPECIAL_EXC_STORE(r10,ESR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) lbz r10,PACAIRQSOFTMASK(r13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) SPECIAL_EXC_STORE(r10,SOFTE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) ld r10,_NIP(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) SPECIAL_EXC_STORE(r10,CSRR0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) ld r10,_MSR(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) SPECIAL_EXC_STORE(r10,CSRR1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) blr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) ret_from_level_except:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) ld r3,_MSR(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) andi. r3,r3,MSR_PR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) beq 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) b ret_from_except
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) LOAD_REG_ADDR(r11,extlb_level_exc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) lwz r12,0(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) mfspr r10,SPRN_SPRG_TLB_EXFRAME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) sub r10,r10,r12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) mtspr SPRN_SPRG_TLB_EXFRAME,r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * It's possible that the special level exception interrupted a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * TLB miss handler, and inserted the same entry that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * interrupted handler was about to insert. On CPUs without TLB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * write conditional, this can result in a duplicate TLB entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * Wipe all non-bolted entries to be safe.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * Note that this doesn't protect against any TLB misses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * we may take accessing the stack from here to the end of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * the special level exception. It's not clear how we can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * reasonably protect against that, but only CPUs with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * neither TLB write conditional nor bolted kernel memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * are affected. Do any such CPUs even exist?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) PPC_TLBILX_ALL(0,R0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) REST_NVGPRS(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) SPECIAL_EXC_LOAD(r10,SRR0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) mtspr SPRN_SRR0,r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) SPECIAL_EXC_LOAD(r10,SRR1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) mtspr SPRN_SRR1,r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) SPECIAL_EXC_LOAD(r10,SPRG_GEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) mtspr SPRN_SPRG_GEN_SCRATCH,r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) SPECIAL_EXC_LOAD(r10,SPRG_TLB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) mtspr SPRN_SPRG_TLB_SCRATCH,r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) SPECIAL_EXC_LOAD(r10,MAS0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) mtspr SPRN_MAS0,r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) SPECIAL_EXC_LOAD(r10,MAS1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) mtspr SPRN_MAS1,r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) SPECIAL_EXC_LOAD(r10,MAS2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) mtspr SPRN_MAS2,r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) SPECIAL_EXC_LOAD(r10,MAS3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) mtspr SPRN_MAS3,r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) SPECIAL_EXC_LOAD(r10,MAS6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) mtspr SPRN_MAS6,r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) SPECIAL_EXC_LOAD(r10,MAS7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) mtspr SPRN_MAS7,r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) BEGIN_FTR_SECTION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) SPECIAL_EXC_LOAD(r10,MAS5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) mtspr SPRN_MAS5,r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) SPECIAL_EXC_LOAD(r10,MAS8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) mtspr SPRN_MAS8,r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) lbz r6,PACAIRQSOFTMASK(r13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) ld r5,SOFTE(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* Interrupts had better not already be enabled... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) tweqi r6,IRQS_ENABLED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) andi. r6,r5,IRQS_DISABLED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) bne 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) TRACE_ENABLE_INTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) stb r5,PACAIRQSOFTMASK(r13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * Restore PACAIRQHAPPENED rather than setting it based on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * the return MSR[EE], since we could have interrupted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * __check_irq_replay() or other inconsistent transitory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * states that must remain that way.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) SPECIAL_EXC_LOAD(r10,IRQHAPPENED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) stb r10,PACAIRQHAPPENED(r13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) SPECIAL_EXC_LOAD(r10,DEAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) mtspr SPRN_DEAR,r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) SPECIAL_EXC_LOAD(r10,ESR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) mtspr SPRN_ESR,r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) stdcx. r0,0,r1 /* to clear the reservation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) REST_4GPRS(2, r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) REST_4GPRS(6, r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) ld r10,_CTR(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) ld r11,_XER(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) mtctr r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) mtxer r11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) blr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .macro ret_from_level srr0 srr1 paca_ex scratch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) bl ret_from_level_except
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) ld r10,_LINK(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) ld r11,_CCR(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) ld r0,GPR13(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) mtlr r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) mtcr r11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) ld r10,GPR10(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) ld r11,GPR11(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) ld r12,GPR12(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) mtspr \scratch,r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) std r10,\paca_ex+EX_R10(r13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) std r11,\paca_ex+EX_R11(r13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) ld r10,_NIP(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) ld r11,_MSR(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) ld r0,GPR0(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) ld r1,GPR1(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) mtspr \srr0,r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) mtspr \srr1,r11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) ld r10,\paca_ex+EX_R10(r13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) ld r11,\paca_ex+EX_R11(r13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) mfspr r13,\scratch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) ret_from_crit_except:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) ret_from_level SPRN_CSRR0 SPRN_CSRR1 PACA_EXCRIT SPRN_SPRG_CRIT_SCRATCH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) rfci
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) ret_from_mc_except:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) ret_from_level SPRN_MCSRR0 SPRN_MCSRR1 PACA_EXMC SPRN_SPRG_MC_SCRATCH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) rfmci
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /* Exception prolog code for all exceptions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define EXCEPTION_PROLOG(n, intnum, type, addition) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) mtspr SPRN_SPRG_##type##_SCRATCH,r13; /* get spare registers */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) mfspr r13,SPRN_SPRG_PACA; /* get PACA */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) std r10,PACA_EX##type+EX_R10(r13); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) std r11,PACA_EX##type+EX_R11(r13); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) mfcr r10; /* save CR */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) mfspr r11,SPRN_##type##_SRR1;/* what are we coming from */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) DO_KVM intnum,SPRN_##type##_SRR1; /* KVM hook */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) stw r10,PACA_EX##type+EX_CR(r13); /* save old CR in the PACA */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) addition; /* additional code for that exc. */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) std r1,PACA_EX##type+EX_R1(r13); /* save old r1 in the PACA */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) type##_SET_KSTACK; /* get special stack if necessary */\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) andi. r10,r11,MSR_PR; /* save stack pointer */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) beq 1f; /* branch around if supervisor */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) ld r1,PACAKSAVE(r13); /* get kernel stack coming from usr */\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 1: type##_BTB_FLUSH \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) cmpdi cr1,r1,0; /* check if SP makes sense */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) bge- cr1,exc_##n##_bad_stack;/* bad stack (TODO: out of line) */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) mfspr r10,SPRN_##type##_SRR0; /* read SRR0 before touching stack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /* Exception type-specific macros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define GEN_SET_KSTACK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define SPRN_GEN_SRR0 SPRN_SRR0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define SPRN_GEN_SRR1 SPRN_SRR1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define GDBELL_SET_KSTACK GEN_SET_KSTACK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define SPRN_GDBELL_SRR0 SPRN_GSRR0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define SPRN_GDBELL_SRR1 SPRN_GSRR1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define CRIT_SET_KSTACK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) ld r1,PACA_CRIT_STACK(r13); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) subi r1,r1,SPECIAL_EXC_FRAME_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define SPRN_CRIT_SRR0 SPRN_CSRR0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define SPRN_CRIT_SRR1 SPRN_CSRR1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define DBG_SET_KSTACK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) ld r1,PACA_DBG_STACK(r13); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) subi r1,r1,SPECIAL_EXC_FRAME_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define SPRN_DBG_SRR0 SPRN_DSRR0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define SPRN_DBG_SRR1 SPRN_DSRR1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define MC_SET_KSTACK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) ld r1,PACA_MC_STACK(r13); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) subi r1,r1,SPECIAL_EXC_FRAME_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define SPRN_MC_SRR0 SPRN_MCSRR0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define SPRN_MC_SRR1 SPRN_MCSRR1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #ifdef CONFIG_PPC_FSL_BOOK3E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define GEN_BTB_FLUSH \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) START_BTB_FLUSH_SECTION \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) beq 1f; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) BTB_FLUSH(r10) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 1: \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) END_BTB_FLUSH_SECTION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define CRIT_BTB_FLUSH \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) START_BTB_FLUSH_SECTION \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) BTB_FLUSH(r10) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) END_BTB_FLUSH_SECTION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define DBG_BTB_FLUSH CRIT_BTB_FLUSH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define MC_BTB_FLUSH CRIT_BTB_FLUSH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define GDBELL_BTB_FLUSH GEN_BTB_FLUSH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define GEN_BTB_FLUSH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define CRIT_BTB_FLUSH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define DBG_BTB_FLUSH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define MC_BTB_FLUSH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define GDBELL_BTB_FLUSH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define NORMAL_EXCEPTION_PROLOG(n, intnum, addition) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) EXCEPTION_PROLOG(n, intnum, GEN, addition##_GEN(n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define CRIT_EXCEPTION_PROLOG(n, intnum, addition) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) EXCEPTION_PROLOG(n, intnum, CRIT, addition##_CRIT(n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define DBG_EXCEPTION_PROLOG(n, intnum, addition) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) EXCEPTION_PROLOG(n, intnum, DBG, addition##_DBG(n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define MC_EXCEPTION_PROLOG(n, intnum, addition) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) EXCEPTION_PROLOG(n, intnum, MC, addition##_MC(n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define GDBELL_EXCEPTION_PROLOG(n, intnum, addition) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) EXCEPTION_PROLOG(n, intnum, GDBELL, addition##_GDBELL(n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /* Variants of the "addition" argument for the prolog
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define PROLOG_ADDITION_NONE_GEN(n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define PROLOG_ADDITION_NONE_GDBELL(n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define PROLOG_ADDITION_NONE_CRIT(n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define PROLOG_ADDITION_NONE_DBG(n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define PROLOG_ADDITION_NONE_MC(n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define PROLOG_ADDITION_MASKABLE_GEN(n) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) lbz r10,PACAIRQSOFTMASK(r13); /* are irqs soft-masked? */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) andi. r10,r10,IRQS_DISABLED; /* yes -> go out of line */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) bne masked_interrupt_book3e_##n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define PROLOG_ADDITION_2REGS_GEN(n) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) std r14,PACA_EXGEN+EX_R14(r13); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) std r15,PACA_EXGEN+EX_R15(r13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define PROLOG_ADDITION_1REG_GEN(n) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) std r14,PACA_EXGEN+EX_R14(r13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define PROLOG_ADDITION_2REGS_CRIT(n) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) std r14,PACA_EXCRIT+EX_R14(r13); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) std r15,PACA_EXCRIT+EX_R15(r13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define PROLOG_ADDITION_2REGS_DBG(n) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) std r14,PACA_EXDBG+EX_R14(r13); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) std r15,PACA_EXDBG+EX_R15(r13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define PROLOG_ADDITION_2REGS_MC(n) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) std r14,PACA_EXMC+EX_R14(r13); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) std r15,PACA_EXMC+EX_R15(r13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /* Core exception code for all exceptions except TLB misses. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define EXCEPTION_COMMON_LVL(n, scratch, excf) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) exc_##n##_common: \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) std r0,GPR0(r1); /* save r0 in stackframe */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) std r2,GPR2(r1); /* save r2 in stackframe */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) std r9,GPR9(r1); /* save r9 in stackframe */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) std r10,_NIP(r1); /* save SRR0 to stackframe */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) std r11,_MSR(r1); /* save SRR1 to stackframe */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) beq 2f; /* if from kernel mode */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) ACCOUNT_CPU_USER_ENTRY(r13,r10,r11);/* accounting (uses cr0+eq) */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 2: ld r3,excf+EX_R10(r13); /* get back r10 */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) ld r4,excf+EX_R11(r13); /* get back r11 */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) mfspr r5,scratch; /* get back r13 */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) std r12,GPR12(r1); /* save r12 in stackframe */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) mflr r6; /* save LR in stackframe */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) mfctr r7; /* save CTR in stackframe */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) mfspr r8,SPRN_XER; /* save XER in stackframe */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) ld r9,excf+EX_R1(r13); /* load orig r1 back from PACA */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) lwz r10,excf+EX_CR(r13); /* load orig CR back from PACA */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) lbz r11,PACAIRQSOFTMASK(r13); /* get current IRQ softe */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) ld r12,exception_marker@toc(r2); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) li r0,0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) std r3,GPR10(r1); /* save r10 to stackframe */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) std r4,GPR11(r1); /* save r11 to stackframe */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) std r5,GPR13(r1); /* save it to stackframe */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) std r6,_LINK(r1); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) std r7,_CTR(r1); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) std r8,_XER(r1); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) li r3,(n)+1; /* indicate partial regs in trap */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) std r9,0(r1); /* store stack frame back link */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) std r10,_CCR(r1); /* store orig CR in stackframe */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) std r9,GPR1(r1); /* store stack frame back link */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) std r11,SOFTE(r1); /* and save it to stackframe */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) std r12,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) std r3,_TRAP(r1); /* set trap number */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) std r0,RESULT(r1); /* clear regs->result */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define EXCEPTION_COMMON(n) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) EXCEPTION_COMMON_LVL(n, SPRN_SPRG_GEN_SCRATCH, PACA_EXGEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define EXCEPTION_COMMON_CRIT(n) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) EXCEPTION_COMMON_LVL(n, SPRN_SPRG_CRIT_SCRATCH, PACA_EXCRIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define EXCEPTION_COMMON_MC(n) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) EXCEPTION_COMMON_LVL(n, SPRN_SPRG_MC_SCRATCH, PACA_EXMC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define EXCEPTION_COMMON_DBG(n) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) EXCEPTION_COMMON_LVL(n, SPRN_SPRG_DBG_SCRATCH, PACA_EXDBG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * This is meant for exceptions that don't immediately hard-enable. We
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * set a bit in paca->irq_happened to ensure that a subsequent call to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) * arch_local_irq_restore() will properly hard-enable and avoid the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * fast-path, and then reconcile irq state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define INTS_DISABLE RECONCILE_IRQ_STATE(r3,r4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) * This is called by exceptions that don't use INTS_DISABLE (that did not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) * touch irq indicators in the PACA). This will restore MSR:EE to it's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) * previous value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) * XXX In the long run, we may want to open-code it in order to separate the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) * load from the wrtee, thus limiting the latency caused by the dependency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) * but at this point, I'll favor code clarity until we have a near to final
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) * implementation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define INTS_RESTORE_HARD \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) ld r11,_MSR(r1); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) wrtee r11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) /* XXX FIXME: Restore r14/r15 when necessary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define BAD_STACK_TRAMPOLINE(n) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) exc_##n##_bad_stack: \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) li r1,(n); /* get exception number */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) sth r1,PACA_TRAP_SAVE(r13); /* store trap */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) b bad_stack_book3e; /* bad stack error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) /* WARNING: If you change the layout of this stub, make sure you check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) * the debug exception handler which handles single stepping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) * into exceptions from userspace, and the MM code in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) * arch/powerpc/mm/tlb_nohash.c which patches the branch here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) * and would need to be updated if that branch is moved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define EXCEPTION_STUB(loc, label) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) . = interrupt_base_book3e + loc; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) nop; /* To make debug interrupts happy */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) b exc_##label##_book3e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define ACK_NONE(r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define ACK_DEC(r) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) lis r,TSR_DIS@h; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) mtspr SPRN_TSR,r
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define ACK_FIT(r) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) lis r,TSR_FIS@h; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) mtspr SPRN_TSR,r
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) /* Used by asynchronous interrupt that may happen in the idle loop.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) * This check if the thread was in the idle loop, and if yes, returns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) * to the caller rather than the PC. This is to avoid a race if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) * interrupts happen before the wait instruction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define CHECK_NAPPING() \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) ld r11, PACA_THREAD_INFO(r13); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) ld r10,TI_LOCAL_FLAGS(r11); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) andi. r9,r10,_TLF_NAPPING; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) beq+ 1f; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) ld r8,_LINK(r1); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) rlwinm r7,r10,0,~_TLF_NAPPING; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) std r8,_NIP(r1); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) std r7,TI_LOCAL_FLAGS(r11); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define MASKABLE_EXCEPTION(trapnum, intnum, label, hdlr, ack) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) START_EXCEPTION(label); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) NORMAL_EXCEPTION_PROLOG(trapnum, intnum, PROLOG_ADDITION_MASKABLE)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) EXCEPTION_COMMON(trapnum) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) INTS_DISABLE; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) ack(r8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) CHECK_NAPPING(); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) addi r3,r1,STACK_FRAME_OVERHEAD; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) bl hdlr; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) b ret_from_except_lite;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) /* This value is used to mark exception frames on the stack. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .section ".toc","aw"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) exception_marker:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .tc ID_EXC_MARKER[TC],STACK_FRAME_REGS_MARKER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) * And here we have the exception vectors !
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .text
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .balign 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .globl interrupt_base_book3e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) interrupt_base_book3e: /* fake trap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) EXCEPTION_STUB(0x000, machine_check)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) EXCEPTION_STUB(0x020, critical_input) /* 0x0100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) EXCEPTION_STUB(0x040, debug_crit) /* 0x0d00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) EXCEPTION_STUB(0x060, data_storage) /* 0x0300 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) EXCEPTION_STUB(0x080, instruction_storage) /* 0x0400 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) EXCEPTION_STUB(0x0a0, external_input) /* 0x0500 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) EXCEPTION_STUB(0x0c0, alignment) /* 0x0600 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) EXCEPTION_STUB(0x0e0, program) /* 0x0700 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) EXCEPTION_STUB(0x100, fp_unavailable) /* 0x0800 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) EXCEPTION_STUB(0x120, system_call) /* 0x0c00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) EXCEPTION_STUB(0x140, ap_unavailable) /* 0x0f20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) EXCEPTION_STUB(0x160, decrementer) /* 0x0900 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) EXCEPTION_STUB(0x180, fixed_interval) /* 0x0980 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) EXCEPTION_STUB(0x1a0, watchdog) /* 0x09f0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) EXCEPTION_STUB(0x1c0, data_tlb_miss)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) EXCEPTION_STUB(0x1e0, instruction_tlb_miss)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) EXCEPTION_STUB(0x200, altivec_unavailable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) EXCEPTION_STUB(0x220, altivec_assist)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) EXCEPTION_STUB(0x260, perfmon)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) EXCEPTION_STUB(0x280, doorbell)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) EXCEPTION_STUB(0x2a0, doorbell_crit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) EXCEPTION_STUB(0x2c0, guest_doorbell)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) EXCEPTION_STUB(0x2e0, guest_doorbell_crit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) EXCEPTION_STUB(0x300, hypercall)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) EXCEPTION_STUB(0x320, ehpriv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) EXCEPTION_STUB(0x340, lrat_error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .globl __end_interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) __end_interrupts:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) /* Critical Input Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) START_EXCEPTION(critical_input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) CRIT_EXCEPTION_PROLOG(0x100, BOOKE_INTERRUPT_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) PROLOG_ADDITION_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) EXCEPTION_COMMON_CRIT(0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) bl save_nvgprs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) bl special_reg_save
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) CHECK_NAPPING();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) addi r3,r1,STACK_FRAME_OVERHEAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) bl unknown_exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) b ret_from_crit_except
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) /* Machine Check Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) START_EXCEPTION(machine_check);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) MC_EXCEPTION_PROLOG(0x000, BOOKE_INTERRUPT_MACHINE_CHECK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) PROLOG_ADDITION_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) EXCEPTION_COMMON_MC(0x000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) bl save_nvgprs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) bl special_reg_save
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) CHECK_NAPPING();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) addi r3,r1,STACK_FRAME_OVERHEAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) bl machine_check_exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) b ret_from_mc_except
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) /* Data Storage Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) START_EXCEPTION(data_storage)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) NORMAL_EXCEPTION_PROLOG(0x300, BOOKE_INTERRUPT_DATA_STORAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) PROLOG_ADDITION_2REGS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) mfspr r14,SPRN_DEAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) mfspr r15,SPRN_ESR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) EXCEPTION_COMMON(0x300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) INTS_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) b storage_fault_common
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) /* Instruction Storage Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) START_EXCEPTION(instruction_storage);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) NORMAL_EXCEPTION_PROLOG(0x400, BOOKE_INTERRUPT_INST_STORAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) PROLOG_ADDITION_2REGS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) li r15,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) mr r14,r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) EXCEPTION_COMMON(0x400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) INTS_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) b storage_fault_common
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) /* External Input Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) MASKABLE_EXCEPTION(0x500, BOOKE_INTERRUPT_EXTERNAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) external_input, do_IRQ, ACK_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) /* Alignment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) START_EXCEPTION(alignment);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) NORMAL_EXCEPTION_PROLOG(0x600, BOOKE_INTERRUPT_ALIGNMENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) PROLOG_ADDITION_2REGS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) mfspr r14,SPRN_DEAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) mfspr r15,SPRN_ESR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) EXCEPTION_COMMON(0x600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) b alignment_more /* no room, go out of line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) /* Program Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) START_EXCEPTION(program);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) NORMAL_EXCEPTION_PROLOG(0x700, BOOKE_INTERRUPT_PROGRAM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) PROLOG_ADDITION_1REG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) mfspr r14,SPRN_ESR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) EXCEPTION_COMMON(0x700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) INTS_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) std r14,_DSISR(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) addi r3,r1,STACK_FRAME_OVERHEAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) ld r14,PACA_EXGEN+EX_R14(r13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) bl save_nvgprs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) bl program_check_exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) b ret_from_except
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) /* Floating Point Unavailable Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) START_EXCEPTION(fp_unavailable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) NORMAL_EXCEPTION_PROLOG(0x800, BOOKE_INTERRUPT_FP_UNAVAIL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) PROLOG_ADDITION_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) /* we can probably do a shorter exception entry for that one... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) EXCEPTION_COMMON(0x800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) ld r12,_MSR(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) andi. r0,r12,MSR_PR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) beq- 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) bl load_up_fpu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) b fast_exception_return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) 1: INTS_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) bl save_nvgprs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) addi r3,r1,STACK_FRAME_OVERHEAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) bl kernel_fp_unavailable_exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) b ret_from_except
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) /* Altivec Unavailable Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) START_EXCEPTION(altivec_unavailable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) NORMAL_EXCEPTION_PROLOG(0x200, BOOKE_INTERRUPT_ALTIVEC_UNAVAIL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) PROLOG_ADDITION_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) /* we can probably do a shorter exception entry for that one... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) EXCEPTION_COMMON(0x200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) #ifdef CONFIG_ALTIVEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) BEGIN_FTR_SECTION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) ld r12,_MSR(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) andi. r0,r12,MSR_PR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) beq- 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) bl load_up_altivec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) b fast_exception_return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) INTS_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) bl save_nvgprs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) addi r3,r1,STACK_FRAME_OVERHEAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) bl altivec_unavailable_exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) b ret_from_except
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) /* AltiVec Assist */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) START_EXCEPTION(altivec_assist);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) NORMAL_EXCEPTION_PROLOG(0x220,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) BOOKE_INTERRUPT_ALTIVEC_ASSIST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) PROLOG_ADDITION_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) EXCEPTION_COMMON(0x220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) INTS_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) bl save_nvgprs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) addi r3,r1,STACK_FRAME_OVERHEAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) #ifdef CONFIG_ALTIVEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) BEGIN_FTR_SECTION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) bl altivec_assist_exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) bl unknown_exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) b ret_from_except
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) /* Decrementer Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) MASKABLE_EXCEPTION(0x900, BOOKE_INTERRUPT_DECREMENTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) decrementer, timer_interrupt, ACK_DEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) /* Fixed Interval Timer Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) MASKABLE_EXCEPTION(0x980, BOOKE_INTERRUPT_FIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) fixed_interval, unknown_exception, ACK_FIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) /* Watchdog Timer Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) START_EXCEPTION(watchdog);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) CRIT_EXCEPTION_PROLOG(0x9f0, BOOKE_INTERRUPT_WATCHDOG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) PROLOG_ADDITION_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) EXCEPTION_COMMON_CRIT(0x9f0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) bl save_nvgprs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) bl special_reg_save
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) CHECK_NAPPING();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) addi r3,r1,STACK_FRAME_OVERHEAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) #ifdef CONFIG_BOOKE_WDT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) bl WatchdogException
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) bl unknown_exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) b ret_from_crit_except
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) /* System Call Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) START_EXCEPTION(system_call)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) mr r9,r13 /* keep a copy of userland r13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) mfspr r11,SPRN_SRR0 /* get return address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) mfspr r12,SPRN_SRR1 /* get previous MSR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) mfspr r13,SPRN_SPRG_PACA /* get our PACA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) b system_call_common
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) /* Auxiliary Processor Unavailable Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) START_EXCEPTION(ap_unavailable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) NORMAL_EXCEPTION_PROLOG(0xf20, BOOKE_INTERRUPT_AP_UNAVAIL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) PROLOG_ADDITION_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) EXCEPTION_COMMON(0xf20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) INTS_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) bl save_nvgprs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) addi r3,r1,STACK_FRAME_OVERHEAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) bl unknown_exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) b ret_from_except
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) /* Debug exception as a critical interrupt*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) START_EXCEPTION(debug_crit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) CRIT_EXCEPTION_PROLOG(0xd00, BOOKE_INTERRUPT_DEBUG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) PROLOG_ADDITION_2REGS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) * If there is a single step or branch-taken exception in an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) * exception entry sequence, it was probably meant to apply to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) * the code where the exception occurred (since exception entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) * doesn't turn off DE automatically). We simulate the effect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) * of turning off DE on entry to an exception handler by turning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) * off DE in the CSRR1 value and clearing the debug status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) mfspr r14,SPRN_DBSR /* check single-step/branch taken */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) andis. r15,r14,(DBSR_IC|DBSR_BT)@h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) beq+ 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) #ifdef CONFIG_RELOCATABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) ld r15,PACATOC(r13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) ld r14,interrupt_base_book3e@got(r15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) ld r15,__end_interrupts@got(r15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) cmpld cr0,r10,r14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) cmpld cr1,r10,r15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) LOAD_REG_IMMEDIATE_SYM(r14, r15, interrupt_base_book3e)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) cmpld cr0, r10, r14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) LOAD_REG_IMMEDIATE_SYM(r14, r15, __end_interrupts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) cmpld cr1, r10, r14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) blt+ cr0,1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) bge+ cr1,1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) /* here it looks like we got an inappropriate debug exception. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) lis r14,(DBSR_IC|DBSR_BT)@h /* clear the event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) rlwinm r11,r11,0,~MSR_DE /* clear DE in the CSRR1 value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) mtspr SPRN_DBSR,r14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) mtspr SPRN_CSRR1,r11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) lwz r10,PACA_EXCRIT+EX_CR(r13) /* restore registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) ld r1,PACA_EXCRIT+EX_R1(r13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) ld r14,PACA_EXCRIT+EX_R14(r13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) ld r15,PACA_EXCRIT+EX_R15(r13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) mtcr r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) ld r10,PACA_EXCRIT+EX_R10(r13) /* restore registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) ld r11,PACA_EXCRIT+EX_R11(r13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) mfspr r13,SPRN_SPRG_CRIT_SCRATCH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) rfci
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) /* Normal debug exception */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) /* XXX We only handle coming from userspace for now since we can't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) * quite save properly an interrupted kernel state yet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) 1: andi. r14,r11,MSR_PR; /* check for userspace again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) beq kernel_dbg_exc; /* if from kernel mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) /* Now we mash up things to make it look like we are coming on a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) * normal exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) mfspr r14,SPRN_DBSR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) EXCEPTION_COMMON_CRIT(0xd00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) std r14,_DSISR(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) addi r3,r1,STACK_FRAME_OVERHEAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) mr r4,r14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) ld r14,PACA_EXCRIT+EX_R14(r13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) ld r15,PACA_EXCRIT+EX_R15(r13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) bl save_nvgprs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) bl DebugException
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) b ret_from_except
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) kernel_dbg_exc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) b . /* NYI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) /* Debug exception as a debug interrupt*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) START_EXCEPTION(debug_debug);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) DBG_EXCEPTION_PROLOG(0xd00, BOOKE_INTERRUPT_DEBUG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) PROLOG_ADDITION_2REGS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) * If there is a single step or branch-taken exception in an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) * exception entry sequence, it was probably meant to apply to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) * the code where the exception occurred (since exception entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) * doesn't turn off DE automatically). We simulate the effect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) * of turning off DE on entry to an exception handler by turning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) * off DE in the DSRR1 value and clearing the debug status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) mfspr r14,SPRN_DBSR /* check single-step/branch taken */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) andis. r15,r14,(DBSR_IC|DBSR_BT)@h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) beq+ 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) #ifdef CONFIG_RELOCATABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) ld r15,PACATOC(r13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) ld r14,interrupt_base_book3e@got(r15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) ld r15,__end_interrupts@got(r15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) cmpld cr0,r10,r14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) cmpld cr1,r10,r15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) LOAD_REG_IMMEDIATE_SYM(r14, r15, interrupt_base_book3e)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) cmpld cr0, r10, r14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) LOAD_REG_IMMEDIATE_SYM(r14, r15,__end_interrupts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) cmpld cr1, r10, r14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) blt+ cr0,1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) bge+ cr1,1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) /* here it looks like we got an inappropriate debug exception. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) lis r14,(DBSR_IC|DBSR_BT)@h /* clear the event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) rlwinm r11,r11,0,~MSR_DE /* clear DE in the DSRR1 value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) mtspr SPRN_DBSR,r14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) mtspr SPRN_DSRR1,r11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) lwz r10,PACA_EXDBG+EX_CR(r13) /* restore registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) ld r1,PACA_EXDBG+EX_R1(r13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) ld r14,PACA_EXDBG+EX_R14(r13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) ld r15,PACA_EXDBG+EX_R15(r13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) mtcr r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) ld r10,PACA_EXDBG+EX_R10(r13) /* restore registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) ld r11,PACA_EXDBG+EX_R11(r13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) mfspr r13,SPRN_SPRG_DBG_SCRATCH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) rfdi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) /* Normal debug exception */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) /* XXX We only handle coming from userspace for now since we can't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) * quite save properly an interrupted kernel state yet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) 1: andi. r14,r11,MSR_PR; /* check for userspace again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) beq kernel_dbg_exc; /* if from kernel mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) /* Now we mash up things to make it look like we are coming on a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) * normal exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) mfspr r14,SPRN_DBSR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) EXCEPTION_COMMON_DBG(0xd08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) INTS_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) std r14,_DSISR(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) addi r3,r1,STACK_FRAME_OVERHEAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) mr r4,r14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) ld r14,PACA_EXDBG+EX_R14(r13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) ld r15,PACA_EXDBG+EX_R15(r13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) bl save_nvgprs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) bl DebugException
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) b ret_from_except
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) START_EXCEPTION(perfmon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) NORMAL_EXCEPTION_PROLOG(0x260, BOOKE_INTERRUPT_PERFORMANCE_MONITOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) PROLOG_ADDITION_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) EXCEPTION_COMMON(0x260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) INTS_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) CHECK_NAPPING()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) addi r3,r1,STACK_FRAME_OVERHEAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) bl performance_monitor_exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) b ret_from_except_lite
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) /* Doorbell interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) MASKABLE_EXCEPTION(0x280, BOOKE_INTERRUPT_DOORBELL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) doorbell, doorbell_exception, ACK_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) /* Doorbell critical Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) START_EXCEPTION(doorbell_crit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) CRIT_EXCEPTION_PROLOG(0x2a0, BOOKE_INTERRUPT_DOORBELL_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) PROLOG_ADDITION_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) EXCEPTION_COMMON_CRIT(0x2a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) bl save_nvgprs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) bl special_reg_save
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) CHECK_NAPPING();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) addi r3,r1,STACK_FRAME_OVERHEAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) bl unknown_exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) b ret_from_crit_except
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) * Guest doorbell interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) * This general exception use GSRRx save/restore registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) START_EXCEPTION(guest_doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) GDBELL_EXCEPTION_PROLOG(0x2c0, BOOKE_INTERRUPT_GUEST_DBELL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) PROLOG_ADDITION_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) EXCEPTION_COMMON(0x2c0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) addi r3,r1,STACK_FRAME_OVERHEAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) bl save_nvgprs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) INTS_RESTORE_HARD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) bl unknown_exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) b ret_from_except
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) /* Guest Doorbell critical Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) START_EXCEPTION(guest_doorbell_crit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) CRIT_EXCEPTION_PROLOG(0x2e0, BOOKE_INTERRUPT_GUEST_DBELL_CRIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) PROLOG_ADDITION_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) EXCEPTION_COMMON_CRIT(0x2e0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) bl save_nvgprs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) bl special_reg_save
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) CHECK_NAPPING();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) addi r3,r1,STACK_FRAME_OVERHEAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) bl unknown_exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) b ret_from_crit_except
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) /* Hypervisor call */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) START_EXCEPTION(hypercall);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) NORMAL_EXCEPTION_PROLOG(0x310, BOOKE_INTERRUPT_HV_SYSCALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) PROLOG_ADDITION_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) EXCEPTION_COMMON(0x310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) addi r3,r1,STACK_FRAME_OVERHEAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) bl save_nvgprs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) INTS_RESTORE_HARD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) bl unknown_exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) b ret_from_except
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) /* Embedded Hypervisor priviledged */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) START_EXCEPTION(ehpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) NORMAL_EXCEPTION_PROLOG(0x320, BOOKE_INTERRUPT_HV_PRIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) PROLOG_ADDITION_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) EXCEPTION_COMMON(0x320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) addi r3,r1,STACK_FRAME_OVERHEAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) bl save_nvgprs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) INTS_RESTORE_HARD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) bl unknown_exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) b ret_from_except
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) /* LRAT Error interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) START_EXCEPTION(lrat_error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) NORMAL_EXCEPTION_PROLOG(0x340, BOOKE_INTERRUPT_LRAT_ERROR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) PROLOG_ADDITION_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) EXCEPTION_COMMON(0x340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) addi r3,r1,STACK_FRAME_OVERHEAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) bl save_nvgprs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) INTS_RESTORE_HARD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) bl unknown_exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) b ret_from_except
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) * An interrupt came in while soft-disabled; We mark paca->irq_happened
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) * accordingly and if the interrupt is level sensitive, we hard disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) * hard disable (full_mask) corresponds to PACA_IRQ_MUST_HARD_MASK, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) * keep these in synch.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) .macro masked_interrupt_book3e paca_irq full_mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) lbz r10,PACAIRQHAPPENED(r13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) .if \full_mask == 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) ori r10,r10,\paca_irq | PACA_IRQ_HARD_DIS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) .else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) ori r10,r10,\paca_irq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) .endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) stb r10,PACAIRQHAPPENED(r13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) .if \full_mask == 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) rldicl r10,r11,48,1 /* clear MSR_EE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) rotldi r11,r10,16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) mtspr SPRN_SRR1,r11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) .endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) lwz r11,PACA_EXGEN+EX_CR(r13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) mtcr r11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) ld r10,PACA_EXGEN+EX_R10(r13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) ld r11,PACA_EXGEN+EX_R11(r13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) mfspr r13,SPRN_SPRG_GEN_SCRATCH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) rfi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) b .
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) masked_interrupt_book3e_0x500:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) masked_interrupt_book3e PACA_IRQ_EE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) masked_interrupt_book3e_0x900:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) ACK_DEC(r10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) masked_interrupt_book3e PACA_IRQ_DEC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) masked_interrupt_book3e_0x980:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) ACK_FIT(r10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) masked_interrupt_book3e PACA_IRQ_DEC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) masked_interrupt_book3e_0x280:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) masked_interrupt_book3e_0x2c0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) masked_interrupt_book3e PACA_IRQ_DBELL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) * This is called from 0x300 and 0x400 handlers after the prologs with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) * r14 and r15 containing the fault address and error code, with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) * original values stashed away in the PACA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) storage_fault_common:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) std r14,_DAR(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) std r15,_DSISR(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) addi r3,r1,STACK_FRAME_OVERHEAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) mr r4,r14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) mr r5,r15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) ld r14,PACA_EXGEN+EX_R14(r13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) ld r15,PACA_EXGEN+EX_R15(r13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) bl do_page_fault
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) cmpdi r3,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) bne- 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) b ret_from_except_lite
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) 1: bl save_nvgprs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) mr r5,r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) addi r3,r1,STACK_FRAME_OVERHEAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) ld r4,_DAR(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) bl bad_page_fault
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) b ret_from_except
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) * Alignment exception doesn't fit entirely in the 0x100 bytes so it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) * continues here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) alignment_more:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) std r14,_DAR(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) std r15,_DSISR(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) addi r3,r1,STACK_FRAME_OVERHEAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) ld r14,PACA_EXGEN+EX_R14(r13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) ld r15,PACA_EXGEN+EX_R15(r13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) bl save_nvgprs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) INTS_RESTORE_HARD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) bl alignment_exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) b ret_from_except
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) .align 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) _GLOBAL(ret_from_except)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) ld r11,_TRAP(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) andi. r0,r11,1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) bne ret_from_except_lite
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) REST_NVGPRS(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) _GLOBAL(ret_from_except_lite)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) * Disable interrupts so that current_thread_info()->flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) * can't change between when we test it and when we return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) * from the interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) wrteei 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) ld r9, PACA_THREAD_INFO(r13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) ld r3,_MSR(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) ld r10,PACACURRENT(r13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) ld r4,TI_FLAGS(r9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) andi. r3,r3,MSR_PR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) beq resume_kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) lwz r3,(THREAD+THREAD_DBCR0)(r10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) /* Check current_thread_info()->flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) andi. r0,r4,_TIF_USER_WORK_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) bne 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) * Check to see if the dbcr0 register is set up to debug.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) * Use the internal debug mode bit to do this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) andis. r0,r3,DBCR0_IDM@h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) beq restore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) mfmsr r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) rlwinm r0,r0,0,~MSR_DE /* Clear MSR.DE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) mtmsr r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) mtspr SPRN_DBCR0,r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) li r10, -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) mtspr SPRN_DBSR,r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) b restore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) 1: andi. r0,r4,_TIF_NEED_RESCHED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) beq 2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) bl restore_interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) SCHEDULE_USER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) b ret_from_except_lite
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) bl save_nvgprs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) * Use a non volatile GPR to save and restore our thread_info flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) * across the call to restore_interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) mr r30,r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) bl restore_interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) mr r4,r30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) addi r3,r1,STACK_FRAME_OVERHEAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) bl do_notify_resume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) b ret_from_except
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) resume_kernel:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) /* check current_thread_info, _TIF_EMULATE_STACK_STORE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) andis. r8,r4,_TIF_EMULATE_STACK_STORE@h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) beq+ 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) addi r8,r1,INT_FRAME_SIZE /* Get the kprobed function entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) ld r3,GPR1(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) subi r3,r3,INT_FRAME_SIZE /* dst: Allocate a trampoline exception frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) mr r4,r1 /* src: current exception frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) mr r1,r3 /* Reroute the trampoline frame to r1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) /* Copy from the original to the trampoline. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) li r5,INT_FRAME_SIZE/8 /* size: INT_FRAME_SIZE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) li r6,0 /* start offset: 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) mtctr r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) 2: ldx r0,r6,r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) stdx r0,r6,r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) addi r6,r6,8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) bdnz 2b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) /* Do real store operation to complete stdu */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) ld r5,GPR1(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) std r8,0(r5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) /* Clear _TIF_EMULATE_STACK_STORE flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) lis r11,_TIF_EMULATE_STACK_STORE@h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) addi r5,r9,TI_FLAGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) 0: ldarx r4,0,r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) andc r4,r4,r11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) stdcx. r4,0,r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) bne- 0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) #ifdef CONFIG_PREEMPT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) /* Check if we need to preempt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) andi. r0,r4,_TIF_NEED_RESCHED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) beq+ restore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) /* Check that preempt_count() == 0 and interrupts are enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) lwz r8,TI_PREEMPT(r9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) cmpwi cr0,r8,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) bne restore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) ld r0,SOFTE(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) andi. r0,r0,IRQS_DISABLED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) bne restore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) * Here we are preempting the current task. We want to make
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) * sure we are soft-disabled first and reconcile irq state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) RECONCILE_IRQ_STATE(r3,r4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) bl preempt_schedule_irq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) * arch_local_irq_restore() from preempt_schedule_irq above may
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) * enable hard interrupt but we really should disable interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) * when we return from the interrupt, and so that we don't get
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) * interrupted after loading SRR0/1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) wrteei 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) #endif /* CONFIG_PREEMPT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) restore:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) * This is the main kernel exit path. First we check if we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) * are about to re-enable interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) ld r5,SOFTE(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) lbz r6,PACAIRQSOFTMASK(r13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) andi. r5,r5,IRQS_DISABLED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) bne .Lrestore_irq_off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) /* We are enabling, were we already enabled ? Yes, just return */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) andi. r6,r6,IRQS_DISABLED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) beq cr0,fast_exception_return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) * We are about to soft-enable interrupts (we are hard disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) * at this point). We check if there's anything that needs to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) * be replayed first.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) lbz r0,PACAIRQHAPPENED(r13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) cmpwi cr0,r0,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) bne- .Lrestore_check_irq_replay
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) * Get here when nothing happened while soft-disabled, just
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) * soft-enable and move-on. We will hard-enable as a side
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) * effect of rfi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) .Lrestore_no_replay:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) TRACE_ENABLE_INTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) li r0,IRQS_ENABLED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) stb r0,PACAIRQSOFTMASK(r13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) /* This is the return from load_up_fpu fast path which could do with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) * less GPR restores in fact, but for now we have a single return path
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) fast_exception_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) wrteei 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) 1: mr r0,r13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) ld r10,_MSR(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) REST_4GPRS(2, r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) andi. r6,r10,MSR_PR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) REST_2GPRS(6, r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) beq 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) ACCOUNT_CPU_USER_EXIT(r13, r10, r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) ld r0,GPR13(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) 1: stdcx. r0,0,r1 /* to clear the reservation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) ld r8,_CCR(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) ld r9,_LINK(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) ld r10,_CTR(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) ld r11,_XER(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) mtcr r8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) mtlr r9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) mtctr r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) mtxer r11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) REST_2GPRS(8, r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) ld r10,GPR10(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) ld r11,GPR11(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) ld r12,GPR12(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) mtspr SPRN_SPRG_GEN_SCRATCH,r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) std r10,PACA_EXGEN+EX_R10(r13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) std r11,PACA_EXGEN+EX_R11(r13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) ld r10,_NIP(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) ld r11,_MSR(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) ld r0,GPR0(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) ld r1,GPR1(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) mtspr SPRN_SRR0,r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) mtspr SPRN_SRR1,r11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) ld r10,PACA_EXGEN+EX_R10(r13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) ld r11,PACA_EXGEN+EX_R11(r13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) mfspr r13,SPRN_SPRG_GEN_SCRATCH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) rfi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) * We are returning to a context with interrupts soft disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) * However, we may also about to hard enable, so we need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) * make sure that in this case, we also clear PACA_IRQ_HARD_DIS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) * or that bit can get out of sync and bad things will happen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) .Lrestore_irq_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) ld r3,_MSR(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) lbz r7,PACAIRQHAPPENED(r13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) andi. r0,r3,MSR_EE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) beq 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) rlwinm r7,r7,0,~PACA_IRQ_HARD_DIS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) stb r7,PACAIRQHAPPENED(r13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) #if defined(CONFIG_PPC_IRQ_SOFT_MASK_DEBUG) && defined(CONFIG_BUG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) /* The interrupt should not have soft enabled. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) lbz r7,PACAIRQSOFTMASK(r13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) 1: tdeqi r7,IRQS_ENABLED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,BUGFLAG_WARNING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) b fast_exception_return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) * Something did happen, check if a re-emit is needed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) * (this also clears paca->irq_happened)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) .Lrestore_check_irq_replay:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) /* XXX: We could implement a fast path here where we check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) * for irq_happened being just 0x01, in which case we can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) * clear it and return. That means that we would potentially
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) * miss a decrementer having wrapped all the way around.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) * Still, this might be useful for things like hash_page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) bl __check_irq_replay
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) cmpwi cr0,r3,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) beq .Lrestore_no_replay
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) * We need to re-emit an interrupt. We do so by re-using our
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) * existing exception frame. We first change the trap value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) * but we need to ensure we preserve the low nibble of it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) ld r4,_TRAP(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) clrldi r4,r4,60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) or r4,r4,r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) std r4,_TRAP(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) * PACA_IRQ_HARD_DIS won't always be set here, so set it now
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) * to reconcile the IRQ state. Tracing is already accounted for.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) lbz r4,PACAIRQHAPPENED(r13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) ori r4,r4,PACA_IRQ_HARD_DIS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) stb r4,PACAIRQHAPPENED(r13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) * Then find the right handler and call it. Interrupts are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) * still soft-disabled and we keep them that way.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) cmpwi cr0,r3,0x500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) bne 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) addi r3,r1,STACK_FRAME_OVERHEAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) bl do_IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) b ret_from_except
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) 1: cmpwi cr0,r3,0x900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) bne 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) addi r3,r1,STACK_FRAME_OVERHEAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) bl timer_interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) b ret_from_except
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) #ifdef CONFIG_PPC_DOORBELL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) cmpwi cr0,r3,0x280
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) bne 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) addi r3,r1,STACK_FRAME_OVERHEAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) bl doorbell_exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) #endif /* CONFIG_PPC_DOORBELL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) 1: b ret_from_except /* What else to do here ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) _ASM_NOKPROBE_SYMBOL(ret_from_except);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) _ASM_NOKPROBE_SYMBOL(ret_from_except_lite);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) _ASM_NOKPROBE_SYMBOL(resume_kernel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) _ASM_NOKPROBE_SYMBOL(restore);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) _ASM_NOKPROBE_SYMBOL(fast_exception_return);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) * Trampolines used when spotting a bad kernel stack pointer in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) * the exception entry code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) * TODO: move some bits like SRR0 read to trampoline, pass PACA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) * index around, etc... to handle crit & mcheck
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) BAD_STACK_TRAMPOLINE(0x000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) BAD_STACK_TRAMPOLINE(0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) BAD_STACK_TRAMPOLINE(0x200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) BAD_STACK_TRAMPOLINE(0x220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) BAD_STACK_TRAMPOLINE(0x260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) BAD_STACK_TRAMPOLINE(0x280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) BAD_STACK_TRAMPOLINE(0x2a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) BAD_STACK_TRAMPOLINE(0x2c0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) BAD_STACK_TRAMPOLINE(0x2e0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) BAD_STACK_TRAMPOLINE(0x300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) BAD_STACK_TRAMPOLINE(0x310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) BAD_STACK_TRAMPOLINE(0x320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) BAD_STACK_TRAMPOLINE(0x340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) BAD_STACK_TRAMPOLINE(0x400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) BAD_STACK_TRAMPOLINE(0x500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) BAD_STACK_TRAMPOLINE(0x600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) BAD_STACK_TRAMPOLINE(0x700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) BAD_STACK_TRAMPOLINE(0x800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) BAD_STACK_TRAMPOLINE(0x900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) BAD_STACK_TRAMPOLINE(0x980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) BAD_STACK_TRAMPOLINE(0x9f0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) BAD_STACK_TRAMPOLINE(0xa00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) BAD_STACK_TRAMPOLINE(0xb00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) BAD_STACK_TRAMPOLINE(0xc00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) BAD_STACK_TRAMPOLINE(0xd00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) BAD_STACK_TRAMPOLINE(0xd08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) BAD_STACK_TRAMPOLINE(0xe00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) BAD_STACK_TRAMPOLINE(0xf00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) BAD_STACK_TRAMPOLINE(0xf20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) .globl bad_stack_book3e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) bad_stack_book3e:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) /* XXX: Needs to make SPRN_SPRG_GEN depend on exception type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) mfspr r10,SPRN_SRR0; /* read SRR0 before touching stack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) ld r1,PACAEMERGSP(r13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) subi r1,r1,64+INT_FRAME_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) std r10,_NIP(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) std r11,_MSR(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) ld r10,PACA_EXGEN+EX_R1(r13) /* FIXME for crit & mcheck */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) lwz r11,PACA_EXGEN+EX_CR(r13) /* FIXME for crit & mcheck */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) std r10,GPR1(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) std r11,_CCR(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) mfspr r10,SPRN_DEAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) mfspr r11,SPRN_ESR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) std r10,_DAR(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) std r11,_DSISR(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) std r0,GPR0(r1); /* save r0 in stackframe */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) std r2,GPR2(r1); /* save r2 in stackframe */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) std r9,GPR9(r1); /* save r9 in stackframe */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) ld r3,PACA_EXGEN+EX_R10(r13);/* get back r10 */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) ld r4,PACA_EXGEN+EX_R11(r13);/* get back r11 */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) mfspr r5,SPRN_SPRG_GEN_SCRATCH;/* get back r13 XXX can be wrong */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) std r3,GPR10(r1); /* save r10 to stackframe */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) std r4,GPR11(r1); /* save r11 to stackframe */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) std r12,GPR12(r1); /* save r12 in stackframe */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) std r5,GPR13(r1); /* save it to stackframe */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) mflr r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) mfctr r11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) mfxer r12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) std r10,_LINK(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) std r11,_CTR(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) std r12,_XER(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) SAVE_10GPRS(14,r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) SAVE_8GPRS(24,r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) lhz r12,PACA_TRAP_SAVE(r13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) std r12,_TRAP(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) addi r11,r1,INT_FRAME_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) std r11,0(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) li r12,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) std r12,0(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) ld r2,PACATOC(r13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) 1: addi r3,r1,STACK_FRAME_OVERHEAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) bl kernel_bad_stack
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) b 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) * Setup the initial TLB for a core. This current implementation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) * assume that whatever we are running off will not conflict with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) * the new mapping at PAGE_OFFSET.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) _GLOBAL(initial_tlb_book3e)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) /* Look for the first TLB with IPROT set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) mfspr r4,SPRN_TLB0CFG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) andi. r3,r4,TLBnCFG_IPROT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) lis r3,MAS0_TLBSEL(0)@h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) bne found_iprot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) mfspr r4,SPRN_TLB1CFG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) andi. r3,r4,TLBnCFG_IPROT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) lis r3,MAS0_TLBSEL(1)@h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) bne found_iprot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) mfspr r4,SPRN_TLB2CFG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) andi. r3,r4,TLBnCFG_IPROT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) lis r3,MAS0_TLBSEL(2)@h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) bne found_iprot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) lis r3,MAS0_TLBSEL(3)@h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) mfspr r4,SPRN_TLB3CFG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) /* fall through */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) found_iprot:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) andi. r5,r4,TLBnCFG_HES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) bne have_hes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) mflr r8 /* save LR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) /* 1. Find the index of the entry we're executing in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) * r3 = MAS0_TLBSEL (for the iprot array)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) * r4 = SPRN_TLBnCFG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) bl invstr /* Find our address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) invstr: mflr r6 /* Make it accessible */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) mfmsr r7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) rlwinm r5,r7,27,31,31 /* extract MSR[IS] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) mfspr r7,SPRN_PID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) slwi r7,r7,16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) or r7,r7,r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) mtspr SPRN_MAS6,r7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) tlbsx 0,r6 /* search MSR[IS], SPID=PID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) mfspr r3,SPRN_MAS0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) rlwinm r5,r3,16,20,31 /* Extract MAS0(Entry) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) mfspr r7,SPRN_MAS1 /* Insure IPROT set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) oris r7,r7,MAS1_IPROT@h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) mtspr SPRN_MAS1,r7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) tlbwe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) /* 2. Invalidate all entries except the entry we're executing in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) * r3 = MAS0 w/TLBSEL & ESEL for the entry we are running in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) * r4 = SPRN_TLBnCFG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) * r5 = ESEL of entry we are running in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) andi. r4,r4,TLBnCFG_N_ENTRY /* Extract # entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) li r6,0 /* Set Entry counter to 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) 1: mr r7,r3 /* Set MAS0(TLBSEL) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) rlwimi r7,r6,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) mtspr SPRN_MAS0,r7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) tlbre
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) mfspr r7,SPRN_MAS1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) rlwinm r7,r7,0,2,31 /* Clear MAS1 Valid and IPROT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) cmpw r5,r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) beq skpinv /* Dont update the current execution TLB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) mtspr SPRN_MAS1,r7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) tlbwe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) skpinv: addi r6,r6,1 /* Increment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) cmpw r6,r4 /* Are we done? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) bne 1b /* If not, repeat */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) /* Invalidate all TLBs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) PPC_TLBILX_ALL(0,R0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) /* 3. Setup a temp mapping and jump to it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) * r3 = MAS0 w/TLBSEL & ESEL for the entry we are running in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) * r5 = ESEL of entry we are running in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) andi. r7,r5,0x1 /* Find an entry not used and is non-zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) addi r7,r7,0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) mr r4,r3 /* Set MAS0(TLBSEL) = 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) mtspr SPRN_MAS0,r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) tlbre
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) rlwimi r4,r7,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) mtspr SPRN_MAS0,r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) mfspr r7,SPRN_MAS1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) xori r6,r7,MAS1_TS /* Setup TMP mapping in the other Address space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) mtspr SPRN_MAS1,r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) tlbwe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) mfmsr r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) xori r6,r6,MSR_IS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) mtspr SPRN_SRR1,r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) bl 1f /* Find our address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) 1: mflr r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) addi r6,r6,(2f - 1b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) mtspr SPRN_SRR0,r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) rfi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) /* 4. Clear out PIDs & Search info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) * r5 = MAS3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) li r6,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) mtspr SPRN_MAS6,r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) mtspr SPRN_PID,r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) /* 5. Invalidate mapping we started in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) * r5 = MAS3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) mtspr SPRN_MAS0,r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) tlbre
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) mfspr r6,SPRN_MAS1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) rlwinm r6,r6,0,2,31 /* clear IPROT and VALID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) mtspr SPRN_MAS1,r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) tlbwe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) /* 6. Setup KERNELBASE mapping in TLB[0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) * r5 = MAS3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) rlwinm r3,r3,0,16,3 /* clear ESEL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) mtspr SPRN_MAS0,r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) lis r6,(MAS1_VALID|MAS1_IPROT)@h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) ori r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_1GB))@l
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) mtspr SPRN_MAS1,r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) LOAD_REG_IMMEDIATE(r6, PAGE_OFFSET | MAS2_M_IF_NEEDED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) mtspr SPRN_MAS2,r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) rlwinm r5,r5,0,0,25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) ori r5,r5,MAS3_SR | MAS3_SW | MAS3_SX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) mtspr SPRN_MAS3,r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) li r5,-1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) rlwinm r5,r5,0,0,25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) tlbwe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) /* 7. Jump to KERNELBASE mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) /* Now we branch the new virtual address mapped by this entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) bl 1f /* Find our address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) 1: mflr r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) addi r6,r6,(2f - 1b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) tovirt(r6,r6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) lis r7,MSR_KERNEL@h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) ori r7,r7,MSR_KERNEL@l
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) mtspr SPRN_SRR0,r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) mtspr SPRN_SRR1,r7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) rfi /* start execution out of TLB1[0] entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) /* 8. Clear out the temp mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) * r4 = MAS0 w/TLBSEL & ESEL for the entry we are running in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) mtspr SPRN_MAS0,r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) tlbre
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) mfspr r5,SPRN_MAS1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) rlwinm r5,r5,0,2,31 /* clear IPROT and VALID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) mtspr SPRN_MAS1,r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) tlbwe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) /* We translate LR and return */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) tovirt(r8,r8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) mtlr r8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) blr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) have_hes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) /* Setup MAS 0,1,2,3 and 7 for tlbwe of a 1G entry that maps the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) * kernel linear mapping. We also set MAS8 once for all here though
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) * that will have to be made dependent on whether we are running under
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) * a hypervisor I suppose.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) /* BEWARE, MAGIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) * This code is called as an ordinary function on the boot CPU. But to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) * avoid duplication, this code is also used in SCOM bringup of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) * secondary CPUs. We read the code between the initial_tlb_code_start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) * and initial_tlb_code_end labels one instruction at a time and RAM it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) * into the new core via SCOM. That doesn't process branches, so there
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) * must be none between those two labels. It also means if this code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) * ever takes any parameters, the SCOM code must also be updated to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) * provide them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) .globl a2_tlbinit_code_start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) a2_tlbinit_code_start:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) ori r11,r3,MAS0_WQ_ALLWAYS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) oris r11,r11,MAS0_ESEL(3)@h /* Use way 3: workaround A2 erratum 376 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) mtspr SPRN_MAS0,r11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) lis r3,(MAS1_VALID | MAS1_IPROT)@h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) ori r3,r3,BOOK3E_PAGESZ_1GB << MAS1_TSIZE_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) mtspr SPRN_MAS1,r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) LOAD_REG_IMMEDIATE(r3, PAGE_OFFSET | MAS2_M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) mtspr SPRN_MAS2,r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) li r3,MAS3_SR | MAS3_SW | MAS3_SX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) mtspr SPRN_MAS7_MAS3,r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) li r3,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) mtspr SPRN_MAS8,r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) /* Write the TLB entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) tlbwe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) .globl a2_tlbinit_after_linear_map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) a2_tlbinit_after_linear_map:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) /* Now we branch the new virtual address mapped by this entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) LOAD_REG_IMMEDIATE_SYM(r3, r5, 1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) mtctr r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) bctr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) 1: /* We are now running at PAGE_OFFSET, clean the TLB of everything
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) * else (including IPROTed things left by firmware)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) * r4 = TLBnCFG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) * r3 = current address (more or less)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) li r5,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) mtspr SPRN_MAS6,r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) tlbsx 0,r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) rlwinm r9,r4,0,TLBnCFG_N_ENTRY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) rlwinm r10,r4,8,0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) addi r10,r10,-1 /* Get inner loop mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) li r3,1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) mfspr r5,SPRN_MAS1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) rlwinm r5,r5,0,(~(MAS1_VALID|MAS1_IPROT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) mfspr r6,SPRN_MAS2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) rldicr r6,r6,0,51 /* Extract EPN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) mfspr r7,SPRN_MAS0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) rlwinm r7,r7,0,0xffff0fff /* Clear HES and WQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) rlwinm r8,r7,16,0xfff /* Extract ESEL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) 2: add r4,r3,r8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) and r4,r4,r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) rlwimi r7,r4,16,MAS0_ESEL_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) mtspr SPRN_MAS0,r7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) mtspr SPRN_MAS1,r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) mtspr SPRN_MAS2,r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) tlbwe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) addi r3,r3,1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) and. r4,r3,r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) bne 3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) addis r6,r6,(1<<30)@h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) cmpw r3,r9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) blt 2b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) .globl a2_tlbinit_after_iprot_flush
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) a2_tlbinit_after_iprot_flush:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) PPC_TLBILX(0,0,R0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) .globl a2_tlbinit_code_end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) a2_tlbinit_code_end:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) /* We translate LR and return */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) mflr r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) tovirt(r3,r3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) mtlr r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) blr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) * Main entry (boot CPU, thread 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) * We enter here from head_64.S, possibly after the prom_init trampoline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) * with r3 and r4 already saved to r31 and 30 respectively and in 64 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) * mode. Anything else is as it was left by the bootloader
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) * Initial requirements of this port:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) * - Kernel loaded at 0 physical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) * - A good lump of memory mapped 0:0 by UTLB entry 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) * - MSR:IS & MSR:DS set to 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) * Note that some of the above requirements will be relaxed in the future
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) * as the kernel becomes smarter at dealing with different initial conditions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) * but for now you have to be careful
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) _GLOBAL(start_initialization_book3e)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) mflr r28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) /* First, we need to setup some initial TLBs to map the kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) * text, data and bss at PAGE_OFFSET. We don't have a real mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) * and always use AS 0, so we just set it up to match our link
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) * address and never use 0 based addresses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) bl initial_tlb_book3e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) /* Init global core bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) bl init_core_book3e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) /* Init per-thread bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) bl init_thread_book3e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) /* Return to common init code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) tovirt(r28,r28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) mtlr r28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) blr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) * Secondary core/processor entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) * This is entered for thread 0 of a secondary core, all other threads
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) * are expected to be stopped. It's similar to start_initialization_book3e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) * except that it's generally entered from the holding loop in head_64.S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) * after CPUs have been gathered by Open Firmware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) * We assume we are in 32 bits mode running with whatever TLB entry was
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) * set for us by the firmware or POR engine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) _GLOBAL(book3e_secondary_core_init_tlb_set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) li r4,1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) b generic_secondary_smp_init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) _GLOBAL(book3e_secondary_core_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) mflr r28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) /* Do we need to setup initial TLB entry ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) cmplwi r4,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) bne 2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) /* Setup TLB for this core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) bl initial_tlb_book3e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) /* We can return from the above running at a different
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) * address, so recalculate r2 (TOC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) bl relative_toc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) /* Init global core bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) 2: bl init_core_book3e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) /* Init per-thread bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) 3: bl init_thread_book3e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) /* Return to common init code at proper virtual address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) * Due to various previous assumptions, we know we entered this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) * function at either the final PAGE_OFFSET mapping or using a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) * 1:1 mapping at 0, so we don't bother doing a complicated check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) * here, we just ensure the return address has the right top bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) * Note that if we ever want to be smarter about where we can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) * started from, we have to be careful that by the time we reach
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) * the code below we may already be running at a different location
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) * than the one we were called from since initial_tlb_book3e can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) * have moved us already.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) cmpdi cr0,r28,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) blt 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) lis r3,PAGE_OFFSET@highest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) sldi r3,r3,32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) or r28,r28,r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) 1: mtlr r28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) blr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) _GLOBAL(book3e_secondary_thread_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) mflr r28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) b 3b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) .globl init_core_book3e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) init_core_book3e:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) /* Establish the interrupt vector base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) tovirt(r2,r2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) LOAD_REG_ADDR(r3, interrupt_base_book3e)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) mtspr SPRN_IVPR,r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) blr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) init_thread_book3e:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) lis r3,(SPRN_EPCR_ICM | SPRN_EPCR_GICM)@h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) mtspr SPRN_EPCR,r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) /* Make sure interrupts are off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) wrteei 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) /* disable all timers and clear out status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) li r3,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) mtspr SPRN_TCR,r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) mfspr r3,SPRN_TSR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) mtspr SPRN_TSR,r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) blr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) _GLOBAL(__setup_base_ivors)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) SET_IVOR(0, 0x020) /* Critical Input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) SET_IVOR(1, 0x000) /* Machine Check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) SET_IVOR(2, 0x060) /* Data Storage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) SET_IVOR(3, 0x080) /* Instruction Storage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) SET_IVOR(4, 0x0a0) /* External Input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) SET_IVOR(5, 0x0c0) /* Alignment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) SET_IVOR(6, 0x0e0) /* Program */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) SET_IVOR(7, 0x100) /* FP Unavailable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) SET_IVOR(8, 0x120) /* System Call */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) SET_IVOR(9, 0x140) /* Auxiliary Processor Unavailable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) SET_IVOR(10, 0x160) /* Decrementer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) SET_IVOR(11, 0x180) /* Fixed Interval Timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) SET_IVOR(12, 0x1a0) /* Watchdog Timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) SET_IVOR(13, 0x1c0) /* Data TLB Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) SET_IVOR(14, 0x1e0) /* Instruction TLB Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) SET_IVOR(15, 0x040) /* Debug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) blr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) _GLOBAL(setup_altivec_ivors)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) SET_IVOR(32, 0x200) /* AltiVec Unavailable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) SET_IVOR(33, 0x220) /* AltiVec Assist */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) blr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) _GLOBAL(setup_perfmon_ivor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) SET_IVOR(35, 0x260) /* Performance Monitor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) blr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) _GLOBAL(setup_doorbell_ivors)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) SET_IVOR(36, 0x280) /* Processor Doorbell */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) SET_IVOR(37, 0x2a0) /* Processor Doorbell Crit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) blr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) _GLOBAL(setup_ehv_ivors)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) SET_IVOR(40, 0x300) /* Embedded Hypervisor System Call */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) SET_IVOR(41, 0x320) /* Embedded Hypervisor Privilege */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) SET_IVOR(38, 0x2c0) /* Guest Processor Doorbell */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) SET_IVOR(39, 0x2e0) /* Guest Processor Doorbell Crit/MC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) blr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) _GLOBAL(setup_lrat_ivor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) SET_IVOR(42, 0x340) /* LRAT Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) blr
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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