Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * PCI address cache; allows the lookup of PCI devices based on I/O address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright IBM Corporation 2004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright Linas Vepstas <linas@austin.ibm.com> 2004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/rbtree.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/atomic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <asm/pci-bridge.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <asm/debugfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <asm/ppc-pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  * DOC: Overview
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  * The pci address cache subsystem.  This subsystem places
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  * PCI device address resources into a red-black tree, sorted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  * according to the address range, so that given only an i/o
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  * address, the corresponding PCI device can be **quickly**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  * found. It is safe to perform an address lookup in an interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  * context; this ability is an important feature.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  * Currently, the only customer of this code is the EEH subsystem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  * thus, this code has been somewhat tailored to suit EEH better.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  * In particular, the cache does *not* hold the addresses of devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  * for which EEH is not enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)  * (Implementation Note: The RB tree seems to be better/faster
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)  * than any hash algo I could think of for this problem, even
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  * with the penalty of slow pointer chases for d-cache misses).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) struct pci_io_addr_range {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	struct rb_node rb_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	resource_size_t addr_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	resource_size_t addr_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	struct eeh_dev *edev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	struct pci_dev *pcidev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) static struct pci_io_addr_cache {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	struct rb_root rb_root;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	spinlock_t piar_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) } pci_io_addr_cache_root;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) static inline struct eeh_dev *__eeh_addr_cache_get_device(unsigned long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	struct rb_node *n = pci_io_addr_cache_root.rb_root.rb_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	while (n) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 		struct pci_io_addr_range *piar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		piar = rb_entry(n, struct pci_io_addr_range, rb_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		if (addr < piar->addr_lo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 			n = n->rb_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		else if (addr > piar->addr_hi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 			n = n->rb_right;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 			return piar->edev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74)  * eeh_addr_cache_get_dev - Get device, given only address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75)  * @addr: mmio (PIO) phys address or i/o port number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77)  * Given an mmio phys address, or a port number, find a pci device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78)  * that implements this address.  I/O port numbers are assumed to be offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79)  * from zero (that is, they do *not* have pci_io_addr added in).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80)  * It is safe to call this function within an interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) struct eeh_dev *eeh_addr_cache_get_dev(unsigned long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	struct eeh_dev *edev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	spin_lock_irqsave(&pci_io_addr_cache_root.piar_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	edev = __eeh_addr_cache_get_device(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	spin_unlock_irqrestore(&pci_io_addr_cache_root.piar_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	return edev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95)  * Handy-dandy debug print routine, does nothing more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96)  * than print out the contents of our addr cache.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) static void eeh_addr_cache_print(struct pci_io_addr_cache *cache)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	struct rb_node *n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	int cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	n = rb_first(&cache->rb_root);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	while (n) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		struct pci_io_addr_range *piar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		piar = rb_entry(n, struct pci_io_addr_range, rb_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		pr_info("PCI: %s addr range %d [%pap-%pap]: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		       (piar->flags & IORESOURCE_IO) ? "i/o" : "mem", cnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		       &piar->addr_lo, &piar->addr_hi, pci_name(piar->pcidev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		cnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		n = rb_next(n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* Insert address range into the rb tree. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static struct pci_io_addr_range *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) eeh_addr_cache_insert(struct pci_dev *dev, resource_size_t alo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		      resource_size_t ahi, unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	struct rb_node **p = &pci_io_addr_cache_root.rb_root.rb_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	struct rb_node *parent = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	struct pci_io_addr_range *piar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	/* Walk tree, find a place to insert into tree */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	while (*p) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		parent = *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		piar = rb_entry(parent, struct pci_io_addr_range, rb_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		if (ahi < piar->addr_lo) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 			p = &parent->rb_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		} else if (alo > piar->addr_hi) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 			p = &parent->rb_right;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 			if (dev != piar->pcidev ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 			    alo != piar->addr_lo || ahi != piar->addr_hi) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 				pr_warn("PIAR: overlapping address range\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 			return piar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	piar = kzalloc(sizeof(struct pci_io_addr_range), GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	if (!piar)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	piar->addr_lo = alo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	piar->addr_hi = ahi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	piar->edev = pci_dev_to_eeh_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	piar->pcidev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	piar->flags = flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	eeh_edev_dbg(piar->edev, "PIAR: insert range=[%pap:%pap]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		 &alo, &ahi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	rb_link_node(&piar->rb_node, parent, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	rb_insert_color(&piar->rb_node, &pci_io_addr_cache_root.rb_root);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	return piar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static void __eeh_addr_cache_insert_dev(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	struct eeh_dev *edev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	edev = pci_dev_to_eeh_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	if (!edev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		pr_warn("PCI: no EEH dev found for %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 			pci_name(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	/* Skip any devices for which EEH is not enabled. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	if (!edev->pe) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		dev_dbg(&dev->dev, "EEH: Skip building address cache\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	 * Walk resources on this device, poke the first 7 (6 normal BAR and 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	 * ROM BAR) into the tree.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		resource_size_t start = pci_resource_start(dev,i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		resource_size_t end = pci_resource_end(dev,i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		unsigned long flags = pci_resource_flags(dev,i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		/* We are interested only bus addresses, not dma or other stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		if (0 == (flags & (IORESOURCE_IO | IORESOURCE_MEM)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		if (start == 0 || ~start == 0 || end == 0 || ~end == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 			 continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		eeh_addr_cache_insert(dev, start, end, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)  * eeh_addr_cache_insert_dev - Add a device to the address cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)  * @dev: PCI device whose I/O addresses we are interested in.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)  * In order to support the fast lookup of devices based on addresses,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)  * we maintain a cache of devices that can be quickly searched.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)  * This routine adds a device to that cache.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) void eeh_addr_cache_insert_dev(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	spin_lock_irqsave(&pci_io_addr_cache_root.piar_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	__eeh_addr_cache_insert_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	spin_unlock_irqrestore(&pci_io_addr_cache_root.piar_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static inline void __eeh_addr_cache_rmv_dev(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	struct rb_node *n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) restart:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	n = rb_first(&pci_io_addr_cache_root.rb_root);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	while (n) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		struct pci_io_addr_range *piar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		piar = rb_entry(n, struct pci_io_addr_range, rb_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		if (piar->pcidev == dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 			eeh_edev_dbg(piar->edev, "PIAR: remove range=[%pap:%pap]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 				 &piar->addr_lo, &piar->addr_hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 			rb_erase(n, &pci_io_addr_cache_root.rb_root);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 			kfree(piar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 			goto restart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		n = rb_next(n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)  * eeh_addr_cache_rmv_dev - remove pci device from addr cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)  * @dev: device to remove
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)  * Remove a device from the addr-cache tree.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)  * This is potentially expensive, since it will walk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)  * the tree multiple times (once per resource).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)  * But so what; device removal doesn't need to be that fast.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) void eeh_addr_cache_rmv_dev(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	spin_lock_irqsave(&pci_io_addr_cache_root.piar_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	__eeh_addr_cache_rmv_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	spin_unlock_irqrestore(&pci_io_addr_cache_root.piar_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)  * eeh_addr_cache_init - Initialize a cache of I/O addresses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)  * Initialize a cache of pci i/o addresses.  This cache will be used to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)  * find the pci device that corresponds to a given address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) void eeh_addr_cache_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	spin_lock_init(&pci_io_addr_cache_root.piar_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static int eeh_addr_cache_show(struct seq_file *s, void *v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	struct pci_io_addr_range *piar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	struct rb_node *n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	spin_lock_irqsave(&pci_io_addr_cache_root.piar_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	for (n = rb_first(&pci_io_addr_cache_root.rb_root); n; n = rb_next(n)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		piar = rb_entry(n, struct pci_io_addr_range, rb_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		seq_printf(s, "%s addr range [%pap-%pap]: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		       (piar->flags & IORESOURCE_IO) ? "i/o" : "mem",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		       &piar->addr_lo, &piar->addr_hi, pci_name(piar->pcidev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	spin_unlock_irqrestore(&pci_io_addr_cache_root.piar_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) DEFINE_SHOW_ATTRIBUTE(eeh_addr_cache);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) void eeh_cache_debugfs_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	debugfs_create_file_unsafe("eeh_address_cache", 0400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 			powerpc_debugfs_root, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 			&eeh_addr_cache_fops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }