^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2006 Benjamin Herrenschmidt, IBM Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Provide default implementations of the DMA mapping callbacks for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * busses using the iommu infrastructure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/dma-direct.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/iommu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Generic iommu implementation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* Allocates a contiguous real buffer and creates mappings over it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * Returns the virtual address of the buffer and sets dma_handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * to the dma address (mapping) of the first page.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) static void *dma_iommu_alloc_coherent(struct device *dev, size_t size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) dma_addr_t *dma_handle, gfp_t flag,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) unsigned long attrs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) return iommu_alloc_coherent(dev, get_iommu_table_base(dev), size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) dma_handle, dev->coherent_dma_mask, flag,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) dev_to_node(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static void dma_iommu_free_coherent(struct device *dev, size_t size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) void *vaddr, dma_addr_t dma_handle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) unsigned long attrs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) iommu_free_coherent(get_iommu_table_base(dev), size, vaddr, dma_handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* Creates TCEs for a user provided buffer. The user buffer must be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * contiguous real kernel storage (not vmalloc). The address passed here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * comprises a page address and offset into that page. The dma_addr_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * returned will point to the same byte within the page as was passed in.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static dma_addr_t dma_iommu_map_page(struct device *dev, struct page *page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) unsigned long offset, size_t size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) enum dma_data_direction direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) unsigned long attrs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) return iommu_map_page(dev, get_iommu_table_base(dev), page, offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) size, dma_get_mask(dev), direction, attrs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static void dma_iommu_unmap_page(struct device *dev, dma_addr_t dma_handle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) size_t size, enum dma_data_direction direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) unsigned long attrs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) iommu_unmap_page(get_iommu_table_base(dev), dma_handle, size, direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) attrs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static int dma_iommu_map_sg(struct device *dev, struct scatterlist *sglist,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) int nelems, enum dma_data_direction direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) unsigned long attrs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) return ppc_iommu_map_sg(dev, get_iommu_table_base(dev), sglist, nelems,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) dma_get_mask(dev), direction, attrs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static void dma_iommu_unmap_sg(struct device *dev, struct scatterlist *sglist,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) int nelems, enum dma_data_direction direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) unsigned long attrs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) ppc_iommu_unmap_sg(get_iommu_table_base(dev), sglist, nelems,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) direction, attrs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static bool dma_iommu_bypass_supported(struct device *dev, u64 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct pci_dev *pdev = to_pci_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct pci_controller *phb = pci_bus_to_host(pdev->bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if (iommu_fixed_is_weak || !phb->controller_ops.iommu_bypass_supported)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return phb->controller_ops.iommu_bypass_supported(pdev, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* We support DMA to/from any memory page via the iommu */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) int dma_iommu_dma_supported(struct device *dev, u64 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct iommu_table *tbl = get_iommu_table_base(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if (dev_is_pci(dev) && dma_iommu_bypass_supported(dev, mask)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) dev->dma_ops_bypass = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) dev_dbg(dev, "iommu: 64-bit OK, using fixed ops\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (!tbl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) dev_err(dev, "Warning: IOMMU dma not supported: mask 0x%08llx, table unavailable\n", mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (tbl->it_offset > (mask >> tbl->it_page_shift)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) dev_info(dev, "Warning: IOMMU offset too big for device mask\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) dev_info(dev, "mask: 0x%08llx, table offset: 0x%08lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) mask, tbl->it_offset << tbl->it_page_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) dev_dbg(dev, "iommu: not 64-bit, using default ops\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) dev->dma_ops_bypass = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) u64 dma_iommu_get_required_mask(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct iommu_table *tbl = get_iommu_table_base(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u64 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (dev_is_pci(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u64 bypass_mask = dma_direct_get_required_mask(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if (dma_iommu_dma_supported(dev, bypass_mask)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) dev_info(dev, "%s: returning bypass mask 0x%llx\n", __func__, bypass_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return bypass_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (!tbl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) mask = 1ULL << (fls_long(tbl->it_offset + tbl->it_size) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) tbl->it_page_shift - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) mask += mask - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) const struct dma_map_ops dma_iommu_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .alloc = dma_iommu_alloc_coherent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .free = dma_iommu_free_coherent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .map_sg = dma_iommu_map_sg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .unmap_sg = dma_iommu_unmap_sg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .dma_supported = dma_iommu_dma_supported,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .map_page = dma_iommu_map_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .unmap_page = dma_iommu_unmap_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .get_required_mask = dma_iommu_get_required_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .mmap = dma_common_mmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .get_sgtable = dma_common_get_sgtable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .alloc_pages = dma_common_alloc_pages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .free_pages = dma_common_free_pages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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