^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * This program is used to generate definitions needed by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * assembly language modules.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * We use the technique used in the OSF Mach kernel code:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * generate asm statements containing #defines,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * compile this file to assembler, and then extract the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * #defines from the assembly-language output.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define GENERATING_ASM_OFFSETS /* asm/smp.h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/compat.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/signal.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/mman.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/suspend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/hrtimer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #ifdef CONFIG_PPC64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/hardirq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/kbuild.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <asm/processor.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <asm/cputable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <asm/thread_info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <asm/rtas.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <asm/vdso_datapage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <asm/dbell.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #ifdef CONFIG_PPC64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <asm/paca.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <asm/lppaca.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <asm/cache.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <asm/mmu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <asm/hvcall.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <asm/xics.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #ifdef CONFIG_PPC_POWERNV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <asm/opal.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #if defined(CONFIG_KVM) || defined(CONFIG_KVM_GUEST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #include <linux/kvm_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #if defined(CONFIG_KVM) && defined(CONFIG_PPC_BOOK3S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #include <asm/kvm_book3s.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #include <asm/kvm_ppc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #ifdef CONFIG_PPC32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #include "head_booke.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #if defined(CONFIG_PPC_FSL_BOOK3E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #include "../mm/mmu_decl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #ifdef CONFIG_PPC_8xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #include <asm/fixmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #ifdef CONFIG_XMON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #include "../xmon/xmon_bpts.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define STACK_PT_REGS_OFFSET(sym, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) DEFINE(sym, STACK_FRAME_OVERHEAD + offsetof(struct pt_regs, val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) int main(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) OFFSET(THREAD, task_struct, thread);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) OFFSET(MM, task_struct, mm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #ifdef CONFIG_STACKPROTECTOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) OFFSET(TASK_CANARY, task_struct, stack_canary);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #ifdef CONFIG_PPC64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) OFFSET(PACA_CANARY, paca_struct, canary);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) OFFSET(MMCONTEXTID, mm_struct, context.id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #ifdef CONFIG_PPC64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) DEFINE(SIGSEGV, SIGSEGV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) DEFINE(NMI_MASK, NMI_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) OFFSET(KSP_LIMIT, thread_struct, ksp_limit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #ifdef CONFIG_PPC_RTAS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) OFFSET(RTAS_SP, thread_struct, rtas_sp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #endif /* CONFIG_PPC64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) OFFSET(TASK_STACK, task_struct, stack);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) OFFSET(TASK_CPU, task_struct, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #ifdef CONFIG_LIVEPATCH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) OFFSET(TI_livepatch_sp, thread_info, livepatch_sp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) OFFSET(KSP, thread_struct, ksp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) OFFSET(PT_REGS, thread_struct, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #ifdef CONFIG_BOOKE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) OFFSET(THREAD_NORMSAVES, thread_struct, normsave[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) OFFSET(THREAD_FPEXC_MODE, thread_struct, fpexc_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) OFFSET(THREAD_FPSTATE, thread_struct, fp_state.fpr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) OFFSET(THREAD_FPSAVEAREA, thread_struct, fp_save_area);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) OFFSET(FPSTATE_FPSCR, thread_fp_state, fpscr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) OFFSET(THREAD_LOAD_FP, thread_struct, load_fp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #ifdef CONFIG_ALTIVEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) OFFSET(THREAD_VRSTATE, thread_struct, vr_state.vr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) OFFSET(THREAD_VRSAVEAREA, thread_struct, vr_save_area);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) OFFSET(THREAD_VRSAVE, thread_struct, vrsave);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) OFFSET(THREAD_USED_VR, thread_struct, used_vr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) OFFSET(VRSTATE_VSCR, thread_vr_state, vscr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) OFFSET(THREAD_LOAD_VEC, thread_struct, load_vec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #endif /* CONFIG_ALTIVEC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #ifdef CONFIG_VSX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) OFFSET(THREAD_USED_VSR, thread_struct, used_vsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #endif /* CONFIG_VSX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #ifdef CONFIG_PPC64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) OFFSET(KSP_VSID, thread_struct, ksp_vsid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #else /* CONFIG_PPC64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) OFFSET(PGDIR, thread_struct, pgdir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #ifdef CONFIG_VMAP_STACK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) OFFSET(SRR0, thread_struct, srr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) OFFSET(SRR1, thread_struct, srr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) OFFSET(DAR, thread_struct, dar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) OFFSET(DSISR, thread_struct, dsisr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #ifdef CONFIG_PPC_BOOK3S_32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) OFFSET(THR0, thread_struct, r0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) OFFSET(THR3, thread_struct, r3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) OFFSET(THR4, thread_struct, r4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) OFFSET(THR5, thread_struct, r5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) OFFSET(THR6, thread_struct, r6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) OFFSET(THR8, thread_struct, r8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) OFFSET(THR9, thread_struct, r9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) OFFSET(THR11, thread_struct, r11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) OFFSET(THLR, thread_struct, lr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) OFFSET(THCTR, thread_struct, ctr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #ifdef CONFIG_SPE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) OFFSET(THREAD_EVR0, thread_struct, evr[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) OFFSET(THREAD_ACC, thread_struct, acc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) OFFSET(THREAD_SPEFSCR, thread_struct, spefscr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) OFFSET(THREAD_USED_SPE, thread_struct, used_spe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #endif /* CONFIG_SPE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #endif /* CONFIG_PPC64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) OFFSET(THREAD_DBCR0, thread_struct, debug.dbcr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #ifdef CONFIG_KVM_BOOK3S_32_HANDLER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) OFFSET(THREAD_KVM_SVCPU, thread_struct, kvm_shadow_vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #if defined(CONFIG_KVM) && defined(CONFIG_BOOKE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) OFFSET(THREAD_KVM_VCPU, thread_struct, kvm_vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #if defined(CONFIG_PPC_BOOK3S_32) && defined(CONFIG_PPC_KUAP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) OFFSET(KUAP, thread_struct, kuap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) OFFSET(PACATMSCRATCH, paca_struct, tm_scratch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) OFFSET(THREAD_TM_TFHAR, thread_struct, tm_tfhar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) OFFSET(THREAD_TM_TEXASR, thread_struct, tm_texasr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) OFFSET(THREAD_TM_TFIAR, thread_struct, tm_tfiar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) OFFSET(THREAD_TM_TAR, thread_struct, tm_tar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) OFFSET(THREAD_TM_PPR, thread_struct, tm_ppr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) OFFSET(THREAD_TM_DSCR, thread_struct, tm_dscr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) OFFSET(THREAD_TM_AMR, thread_struct, tm_amr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) OFFSET(PT_CKPT_REGS, thread_struct, ckpt_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) OFFSET(THREAD_CKVRSTATE, thread_struct, ckvr_state.vr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) OFFSET(THREAD_CKVRSAVE, thread_struct, ckvrsave);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) OFFSET(THREAD_CKFPSTATE, thread_struct, ckfp_state.fpr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* Local pt_regs on stack for Transactional Memory funcs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) DEFINE(TM_FRAME_SIZE, STACK_FRAME_OVERHEAD +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) sizeof(struct pt_regs) + 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) OFFSET(TI_FLAGS, thread_info, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) OFFSET(TI_LOCAL_FLAGS, thread_info, local_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) OFFSET(TI_PREEMPT, thread_info, preempt_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #ifdef CONFIG_PPC64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) OFFSET(DCACHEL1BLOCKSIZE, ppc64_caches, l1d.block_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) OFFSET(DCACHEL1LOGBLOCKSIZE, ppc64_caches, l1d.log_block_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) OFFSET(DCACHEL1BLOCKSPERPAGE, ppc64_caches, l1d.blocks_per_page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) OFFSET(ICACHEL1BLOCKSIZE, ppc64_caches, l1i.block_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) OFFSET(ICACHEL1LOGBLOCKSIZE, ppc64_caches, l1i.log_block_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) OFFSET(ICACHEL1BLOCKSPERPAGE, ppc64_caches, l1i.blocks_per_page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* paca */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) DEFINE(PACA_SIZE, sizeof(struct paca_struct));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) OFFSET(PACAPACAINDEX, paca_struct, paca_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) OFFSET(PACAPROCSTART, paca_struct, cpu_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) OFFSET(PACAKSAVE, paca_struct, kstack);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) OFFSET(PACACURRENT, paca_struct, __current);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) DEFINE(PACA_THREAD_INFO, offsetof(struct paca_struct, __current) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) offsetof(struct task_struct, thread_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) OFFSET(PACASAVEDMSR, paca_struct, saved_msr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) OFFSET(PACAR1, paca_struct, saved_r1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) OFFSET(PACATOC, paca_struct, kernel_toc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) OFFSET(PACAKBASE, paca_struct, kernelbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) OFFSET(PACAKMSR, paca_struct, kernel_msr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) OFFSET(PACAIRQSOFTMASK, paca_struct, irq_soft_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) OFFSET(PACAIRQHAPPENED, paca_struct, irq_happened);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) OFFSET(PACA_FTRACE_ENABLED, paca_struct, ftrace_enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #ifdef CONFIG_PPC_BOOK3S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) OFFSET(PACACONTEXTID, paca_struct, mm_ctx_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #ifdef CONFIG_PPC_MM_SLICES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) OFFSET(PACALOWSLICESPSIZE, paca_struct, mm_ctx_low_slices_psize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) OFFSET(PACAHIGHSLICEPSIZE, paca_struct, mm_ctx_high_slices_psize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) OFFSET(PACA_SLB_ADDR_LIMIT, paca_struct, mm_ctx_slb_addr_limit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) DEFINE(MMUPSIZEDEFSIZE, sizeof(struct mmu_psize_def));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #endif /* CONFIG_PPC_MM_SLICES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #ifdef CONFIG_PPC_BOOK3E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) OFFSET(PACAPGD, paca_struct, pgd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) OFFSET(PACA_KERNELPGD, paca_struct, kernel_pgd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) OFFSET(PACA_EXGEN, paca_struct, exgen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) OFFSET(PACA_EXTLB, paca_struct, extlb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) OFFSET(PACA_EXMC, paca_struct, exmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) OFFSET(PACA_EXCRIT, paca_struct, excrit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) OFFSET(PACA_EXDBG, paca_struct, exdbg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) OFFSET(PACA_MC_STACK, paca_struct, mc_kstack);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) OFFSET(PACA_CRIT_STACK, paca_struct, crit_kstack);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) OFFSET(PACA_DBG_STACK, paca_struct, dbg_kstack);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) OFFSET(PACA_TCD_PTR, paca_struct, tcd_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) OFFSET(TCD_ESEL_NEXT, tlb_core_data, esel_next);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) OFFSET(TCD_ESEL_MAX, tlb_core_data, esel_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) OFFSET(TCD_ESEL_FIRST, tlb_core_data, esel_first);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #endif /* CONFIG_PPC_BOOK3E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #ifdef CONFIG_PPC_BOOK3S_64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) OFFSET(PACASLBCACHE, paca_struct, slb_cache);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) OFFSET(PACASLBCACHEPTR, paca_struct, slb_cache_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) OFFSET(PACASTABRR, paca_struct, stab_rr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) OFFSET(PACAVMALLOCSLLP, paca_struct, vmalloc_sllp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #ifdef CONFIG_PPC_MM_SLICES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) OFFSET(MMUPSIZESLLP, mmu_psize_def, sllp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) OFFSET(PACACONTEXTSLLP, paca_struct, mm_ctx_sllp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #endif /* CONFIG_PPC_MM_SLICES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) OFFSET(PACA_EXGEN, paca_struct, exgen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) OFFSET(PACA_EXMC, paca_struct, exmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) OFFSET(PACA_EXSLB, paca_struct, exslb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) OFFSET(PACA_EXNMI, paca_struct, exnmi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #ifdef CONFIG_PPC_PSERIES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) OFFSET(PACALPPACAPTR, paca_struct, lppaca_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) OFFSET(PACA_SLBSHADOWPTR, paca_struct, slb_shadow_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) OFFSET(SLBSHADOW_STACKVSID, slb_shadow, save_area[SLB_NUM_BOLTED - 1].vsid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) OFFSET(SLBSHADOW_STACKESID, slb_shadow, save_area[SLB_NUM_BOLTED - 1].esid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) OFFSET(SLBSHADOW_SAVEAREA, slb_shadow, save_area);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) OFFSET(LPPACA_PMCINUSE, lppaca, pmcregs_in_use);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) OFFSET(PACA_PMCINUSE, paca_struct, pmcregs_in_use);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) OFFSET(LPPACA_DTLIDX, lppaca, dtl_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) OFFSET(LPPACA_YIELDCOUNT, lppaca, yield_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) OFFSET(PACA_DTL_RIDX, paca_struct, dtl_ridx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #endif /* CONFIG_PPC_BOOK3S_64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) OFFSET(PACAEMERGSP, paca_struct, emergency_sp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #ifdef CONFIG_PPC_BOOK3S_64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) OFFSET(PACAMCEMERGSP, paca_struct, mc_emergency_sp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) OFFSET(PACA_NMI_EMERG_SP, paca_struct, nmi_emergency_sp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) OFFSET(PACA_IN_MCE, paca_struct, in_mce);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) OFFSET(PACA_IN_NMI, paca_struct, in_nmi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) OFFSET(PACA_RFI_FLUSH_FALLBACK_AREA, paca_struct, rfi_flush_fallback_area);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) OFFSET(PACA_EXRFI, paca_struct, exrfi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) OFFSET(PACA_L1D_FLUSH_SIZE, paca_struct, l1d_flush_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) OFFSET(PACAHWCPUID, paca_struct, hw_cpu_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) OFFSET(PACAKEXECSTATE, paca_struct, kexec_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) OFFSET(PACA_DSCR_DEFAULT, paca_struct, dscr_default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) OFFSET(ACCOUNT_STARTTIME, paca_struct, accounting.starttime);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) OFFSET(ACCOUNT_STARTTIME_USER, paca_struct, accounting.starttime_user);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) OFFSET(ACCOUNT_USER_TIME, paca_struct, accounting.utime);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) OFFSET(ACCOUNT_SYSTEM_TIME, paca_struct, accounting.stime);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #ifdef CONFIG_PPC_BOOK3E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) OFFSET(PACA_TRAP_SAVE, paca_struct, trap_save);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) OFFSET(PACA_SPRG_VDSO, paca_struct, sprg_vdso);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #else /* CONFIG_PPC64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) OFFSET(ACCOUNT_STARTTIME, thread_info, accounting.starttime);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) OFFSET(ACCOUNT_STARTTIME_USER, thread_info, accounting.starttime_user);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) OFFSET(ACCOUNT_USER_TIME, thread_info, accounting.utime);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) OFFSET(ACCOUNT_SYSTEM_TIME, thread_info, accounting.stime);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #endif /* CONFIG_PPC64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* RTAS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) OFFSET(RTASBASE, rtas_t, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) OFFSET(RTASENTRY, rtas_t, entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /* Interrupt register frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) DEFINE(INT_FRAME_SIZE, STACK_INT_FRAME_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) DEFINE(SWITCH_FRAME_SIZE, STACK_FRAME_WITH_PT_REGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) STACK_PT_REGS_OFFSET(GPR0, gpr[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) STACK_PT_REGS_OFFSET(GPR1, gpr[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) STACK_PT_REGS_OFFSET(GPR2, gpr[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) STACK_PT_REGS_OFFSET(GPR3, gpr[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) STACK_PT_REGS_OFFSET(GPR4, gpr[4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) STACK_PT_REGS_OFFSET(GPR5, gpr[5]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) STACK_PT_REGS_OFFSET(GPR6, gpr[6]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) STACK_PT_REGS_OFFSET(GPR7, gpr[7]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) STACK_PT_REGS_OFFSET(GPR8, gpr[8]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) STACK_PT_REGS_OFFSET(GPR9, gpr[9]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) STACK_PT_REGS_OFFSET(GPR10, gpr[10]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) STACK_PT_REGS_OFFSET(GPR11, gpr[11]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) STACK_PT_REGS_OFFSET(GPR12, gpr[12]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) STACK_PT_REGS_OFFSET(GPR13, gpr[13]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #ifndef CONFIG_PPC64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) STACK_PT_REGS_OFFSET(GPR14, gpr[14]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #endif /* CONFIG_PPC64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * Note: these symbols include _ because they overlap with special
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * register names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) STACK_PT_REGS_OFFSET(_NIP, nip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) STACK_PT_REGS_OFFSET(_MSR, msr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) STACK_PT_REGS_OFFSET(_CTR, ctr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) STACK_PT_REGS_OFFSET(_LINK, link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) STACK_PT_REGS_OFFSET(_CCR, ccr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) STACK_PT_REGS_OFFSET(_XER, xer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) STACK_PT_REGS_OFFSET(_DAR, dar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) STACK_PT_REGS_OFFSET(_DSISR, dsisr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) STACK_PT_REGS_OFFSET(ORIG_GPR3, orig_gpr3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) STACK_PT_REGS_OFFSET(RESULT, result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) STACK_PT_REGS_OFFSET(_TRAP, trap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #ifndef CONFIG_PPC64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * The PowerPC 400-class & Book-E processors have neither the DAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * nor the DSISR SPRs. Hence, we overload them to hold the similar
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * DEAR and ESR SPRs for such processors. For critical interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * we use them to hold SRR0 and SRR1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) STACK_PT_REGS_OFFSET(_DEAR, dar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) STACK_PT_REGS_OFFSET(_ESR, dsisr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #else /* CONFIG_PPC64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) STACK_PT_REGS_OFFSET(SOFTE, softe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) STACK_PT_REGS_OFFSET(_PPR, ppr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #endif /* CONFIG_PPC64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #ifdef CONFIG_PPC_KUAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) STACK_PT_REGS_OFFSET(STACK_REGS_KUAP, kuap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #if defined(CONFIG_PPC32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) DEFINE(EXC_LVL_SIZE, STACK_EXC_LVL_FRAME_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) DEFINE(MAS0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /* we overload MMUCR for 44x on MAS0 since they are mutually exclusive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) DEFINE(MMUCR, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) DEFINE(MAS1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) DEFINE(MAS2, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) DEFINE(MAS3, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) DEFINE(MAS6, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) DEFINE(MAS7, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) DEFINE(_SRR0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, srr0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) DEFINE(_SRR1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, srr1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) DEFINE(_CSRR0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, csrr0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) DEFINE(_CSRR1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, csrr1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) DEFINE(_DSRR0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, dsrr0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) DEFINE(_DSRR1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, dsrr1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) DEFINE(SAVED_KSP_LIMIT, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, saved_ksp_limit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #ifndef CONFIG_PPC64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) OFFSET(MM_PGD, mm_struct, pgd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #endif /* ! CONFIG_PPC64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* About the CPU features table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) OFFSET(CPU_SPEC_FEATURES, cpu_spec, cpu_features);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) OFFSET(CPU_SPEC_SETUP, cpu_spec, cpu_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) OFFSET(CPU_SPEC_RESTORE, cpu_spec, cpu_restore);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) OFFSET(pbe_address, pbe, address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) OFFSET(pbe_orig_address, pbe, orig_address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) OFFSET(pbe_next, pbe, next);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #ifndef CONFIG_PPC64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) DEFINE(TASK_SIZE, TASK_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) DEFINE(NUM_USER_SEGMENTS, TASK_SIZE>>28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #endif /* ! CONFIG_PPC64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* datapage offsets for use by vdso */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) OFFSET(CFG_TB_ORIG_STAMP, vdso_data, tb_orig_stamp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) OFFSET(CFG_TB_TICKS_PER_SEC, vdso_data, tb_ticks_per_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) OFFSET(CFG_TB_TO_XS, vdso_data, tb_to_xs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) OFFSET(CFG_TB_UPDATE_COUNT, vdso_data, tb_update_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) OFFSET(CFG_TZ_MINUTEWEST, vdso_data, tz_minuteswest);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) OFFSET(CFG_TZ_DSTTIME, vdso_data, tz_dsttime);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) OFFSET(CFG_SYSCALL_MAP32, vdso_data, syscall_map_32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) OFFSET(WTOM_CLOCK_SEC, vdso_data, wtom_clock_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) OFFSET(WTOM_CLOCK_NSEC, vdso_data, wtom_clock_nsec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) OFFSET(STAMP_XTIME_SEC, vdso_data, stamp_xtime_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) OFFSET(STAMP_XTIME_NSEC, vdso_data, stamp_xtime_nsec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) OFFSET(STAMP_SEC_FRAC, vdso_data, stamp_sec_fraction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) OFFSET(CLOCK_HRTIMER_RES, vdso_data, hrtimer_res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #ifdef CONFIG_PPC64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) OFFSET(CFG_ICACHE_BLOCKSZ, vdso_data, icache_block_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) OFFSET(CFG_DCACHE_BLOCKSZ, vdso_data, dcache_block_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) OFFSET(CFG_ICACHE_LOGBLOCKSZ, vdso_data, icache_log_block_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) OFFSET(CFG_DCACHE_LOGBLOCKSZ, vdso_data, dcache_log_block_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) OFFSET(CFG_SYSCALL_MAP64, vdso_data, syscall_map_64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) OFFSET(TVAL64_TV_SEC, __kernel_old_timeval, tv_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) OFFSET(TVAL64_TV_USEC, __kernel_old_timeval, tv_usec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) OFFSET(TSPC64_TV_SEC, __kernel_timespec, tv_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) OFFSET(TSPC64_TV_NSEC, __kernel_timespec, tv_nsec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) OFFSET(TVAL32_TV_SEC, old_timeval32, tv_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) OFFSET(TVAL32_TV_USEC, old_timeval32, tv_usec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) OFFSET(TSPC32_TV_SEC, old_timespec32, tv_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) OFFSET(TSPC32_TV_NSEC, old_timespec32, tv_nsec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /* timeval/timezone offsets for use by vdso */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) OFFSET(TZONE_TZ_MINWEST, timezone, tz_minuteswest);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) OFFSET(TZONE_TZ_DSTTIME, timezone, tz_dsttime);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) /* Other bits used by the vdso */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) DEFINE(CLOCK_REALTIME, CLOCK_REALTIME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) DEFINE(CLOCK_MONOTONIC, CLOCK_MONOTONIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) DEFINE(CLOCK_REALTIME_COARSE, CLOCK_REALTIME_COARSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) DEFINE(CLOCK_MONOTONIC_COARSE, CLOCK_MONOTONIC_COARSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) DEFINE(CLOCK_MAX, CLOCK_TAI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) DEFINE(NSEC_PER_SEC, NSEC_PER_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) DEFINE(EINVAL, EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) DEFINE(KTIME_LOW_RES, KTIME_LOW_RES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #ifdef CONFIG_BUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) DEFINE(BUG_ENTRY_SIZE, sizeof(struct bug_entry));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #ifdef CONFIG_PPC_BOOK3S_64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) DEFINE(PGD_TABLE_SIZE, (sizeof(pgd_t) << max(RADIX_PGD_INDEX_SIZE, H_PGD_INDEX_SIZE)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) DEFINE(PGD_TABLE_SIZE, PGD_TABLE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) DEFINE(PTE_SIZE, sizeof(pte_t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #ifdef CONFIG_KVM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) OFFSET(VCPU_HOST_STACK, kvm_vcpu, arch.host_stack);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) OFFSET(VCPU_HOST_PID, kvm_vcpu, arch.host_pid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) OFFSET(VCPU_GUEST_PID, kvm_vcpu, arch.pid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) OFFSET(VCPU_GPRS, kvm_vcpu, arch.regs.gpr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) OFFSET(VCPU_VRSAVE, kvm_vcpu, arch.vrsave);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) OFFSET(VCPU_FPRS, kvm_vcpu, arch.fp.fpr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #ifdef CONFIG_ALTIVEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) OFFSET(VCPU_VRS, kvm_vcpu, arch.vr.vr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) OFFSET(VCPU_XER, kvm_vcpu, arch.regs.xer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) OFFSET(VCPU_CTR, kvm_vcpu, arch.regs.ctr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) OFFSET(VCPU_LR, kvm_vcpu, arch.regs.link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #ifdef CONFIG_PPC_BOOK3S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) OFFSET(VCPU_TAR, kvm_vcpu, arch.tar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) OFFSET(VCPU_CR, kvm_vcpu, arch.regs.ccr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) OFFSET(VCPU_PC, kvm_vcpu, arch.regs.nip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) OFFSET(VCPU_MSR, kvm_vcpu, arch.shregs.msr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) OFFSET(VCPU_SRR0, kvm_vcpu, arch.shregs.srr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) OFFSET(VCPU_SRR1, kvm_vcpu, arch.shregs.srr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) OFFSET(VCPU_SPRG0, kvm_vcpu, arch.shregs.sprg0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) OFFSET(VCPU_SPRG1, kvm_vcpu, arch.shregs.sprg1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) OFFSET(VCPU_SPRG2, kvm_vcpu, arch.shregs.sprg2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) OFFSET(VCPU_SPRG3, kvm_vcpu, arch.shregs.sprg3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) OFFSET(VCPU_TB_RMENTRY, kvm_vcpu, arch.rm_entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) OFFSET(VCPU_TB_RMINTR, kvm_vcpu, arch.rm_intr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) OFFSET(VCPU_TB_RMEXIT, kvm_vcpu, arch.rm_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) OFFSET(VCPU_TB_GUEST, kvm_vcpu, arch.guest_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) OFFSET(VCPU_TB_CEDE, kvm_vcpu, arch.cede_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) OFFSET(VCPU_CUR_ACTIVITY, kvm_vcpu, arch.cur_activity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) OFFSET(VCPU_ACTIVITY_START, kvm_vcpu, arch.cur_tb_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) OFFSET(TAS_SEQCOUNT, kvmhv_tb_accumulator, seqcount);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) OFFSET(TAS_TOTAL, kvmhv_tb_accumulator, tb_total);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) OFFSET(TAS_MIN, kvmhv_tb_accumulator, tb_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) OFFSET(TAS_MAX, kvmhv_tb_accumulator, tb_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) OFFSET(VCPU_SHARED_SPRG3, kvm_vcpu_arch_shared, sprg3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) OFFSET(VCPU_SHARED_SPRG4, kvm_vcpu_arch_shared, sprg4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) OFFSET(VCPU_SHARED_SPRG5, kvm_vcpu_arch_shared, sprg5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) OFFSET(VCPU_SHARED_SPRG6, kvm_vcpu_arch_shared, sprg6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) OFFSET(VCPU_SHARED_SPRG7, kvm_vcpu_arch_shared, sprg7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) OFFSET(VCPU_SHADOW_PID, kvm_vcpu, arch.shadow_pid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) OFFSET(VCPU_SHADOW_PID1, kvm_vcpu, arch.shadow_pid1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) OFFSET(VCPU_SHARED, kvm_vcpu, arch.shared);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) OFFSET(VCPU_SHARED_MSR, kvm_vcpu_arch_shared, msr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) OFFSET(VCPU_SHADOW_MSR, kvm_vcpu, arch.shadow_msr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #if defined(CONFIG_PPC_BOOK3S_64) && defined(CONFIG_KVM_BOOK3S_PR_POSSIBLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) OFFSET(VCPU_SHAREDBE, kvm_vcpu, arch.shared_big_endian);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) OFFSET(VCPU_SHARED_MAS0, kvm_vcpu_arch_shared, mas0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) OFFSET(VCPU_SHARED_MAS1, kvm_vcpu_arch_shared, mas1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) OFFSET(VCPU_SHARED_MAS2, kvm_vcpu_arch_shared, mas2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) OFFSET(VCPU_SHARED_MAS7_3, kvm_vcpu_arch_shared, mas7_3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) OFFSET(VCPU_SHARED_MAS4, kvm_vcpu_arch_shared, mas4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) OFFSET(VCPU_SHARED_MAS6, kvm_vcpu_arch_shared, mas6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) OFFSET(VCPU_KVM, kvm_vcpu, kvm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) OFFSET(KVM_LPID, kvm, arch.lpid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) /* book3s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) OFFSET(KVM_TLB_SETS, kvm, arch.tlb_sets);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) OFFSET(KVM_SDR1, kvm, arch.sdr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) OFFSET(KVM_HOST_LPID, kvm, arch.host_lpid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) OFFSET(KVM_HOST_LPCR, kvm, arch.host_lpcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) OFFSET(KVM_HOST_SDR1, kvm, arch.host_sdr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) OFFSET(KVM_NEED_FLUSH, kvm, arch.need_tlb_flush.bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) OFFSET(KVM_ENABLED_HCALLS, kvm, arch.enabled_hcalls);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) OFFSET(KVM_VRMA_SLB_V, kvm, arch.vrma_slb_v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) OFFSET(KVM_RADIX, kvm, arch.radix);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) OFFSET(KVM_FWNMI, kvm, arch.fwnmi_enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) OFFSET(KVM_SECURE_GUEST, kvm, arch.secure_guest);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) OFFSET(VCPU_DSISR, kvm_vcpu, arch.shregs.dsisr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) OFFSET(VCPU_DAR, kvm_vcpu, arch.shregs.dar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) OFFSET(VCPU_VPA, kvm_vcpu, arch.vpa.pinned_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) OFFSET(VCPU_VPA_DIRTY, kvm_vcpu, arch.vpa.dirty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) OFFSET(VCPU_HEIR, kvm_vcpu, arch.emul_inst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) OFFSET(VCPU_NESTED, kvm_vcpu, arch.nested);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) OFFSET(VCPU_CPU, kvm_vcpu, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) OFFSET(VCPU_THREAD_CPU, kvm_vcpu, arch.thread_cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #ifdef CONFIG_PPC_BOOK3S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) OFFSET(VCPU_PURR, kvm_vcpu, arch.purr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) OFFSET(VCPU_SPURR, kvm_vcpu, arch.spurr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) OFFSET(VCPU_IC, kvm_vcpu, arch.ic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) OFFSET(VCPU_DSCR, kvm_vcpu, arch.dscr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) OFFSET(VCPU_AMR, kvm_vcpu, arch.amr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) OFFSET(VCPU_UAMOR, kvm_vcpu, arch.uamor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) OFFSET(VCPU_IAMR, kvm_vcpu, arch.iamr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) OFFSET(VCPU_CTRL, kvm_vcpu, arch.ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) OFFSET(VCPU_DABR, kvm_vcpu, arch.dabr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) OFFSET(VCPU_DABRX, kvm_vcpu, arch.dabrx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) OFFSET(VCPU_DAWR, kvm_vcpu, arch.dawr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) OFFSET(VCPU_DAWRX, kvm_vcpu, arch.dawrx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) OFFSET(VCPU_CIABR, kvm_vcpu, arch.ciabr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) OFFSET(VCPU_HFLAGS, kvm_vcpu, arch.hflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) OFFSET(VCPU_DEC, kvm_vcpu, arch.dec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) OFFSET(VCPU_DEC_EXPIRES, kvm_vcpu, arch.dec_expires);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) OFFSET(VCPU_PENDING_EXC, kvm_vcpu, arch.pending_exceptions);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) OFFSET(VCPU_CEDED, kvm_vcpu, arch.ceded);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) OFFSET(VCPU_PRODDED, kvm_vcpu, arch.prodded);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) OFFSET(VCPU_IRQ_PENDING, kvm_vcpu, arch.irq_pending);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) OFFSET(VCPU_DBELL_REQ, kvm_vcpu, arch.doorbell_request);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) OFFSET(VCPU_MMCR, kvm_vcpu, arch.mmcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) OFFSET(VCPU_MMCRA, kvm_vcpu, arch.mmcra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) OFFSET(VCPU_MMCRS, kvm_vcpu, arch.mmcrs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) OFFSET(VCPU_PMC, kvm_vcpu, arch.pmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) OFFSET(VCPU_SPMC, kvm_vcpu, arch.spmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) OFFSET(VCPU_SIAR, kvm_vcpu, arch.siar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) OFFSET(VCPU_SDAR, kvm_vcpu, arch.sdar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) OFFSET(VCPU_SIER, kvm_vcpu, arch.sier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) OFFSET(VCPU_SLB, kvm_vcpu, arch.slb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) OFFSET(VCPU_SLB_MAX, kvm_vcpu, arch.slb_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) OFFSET(VCPU_SLB_NR, kvm_vcpu, arch.slb_nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) OFFSET(VCPU_FAULT_DSISR, kvm_vcpu, arch.fault_dsisr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) OFFSET(VCPU_FAULT_DAR, kvm_vcpu, arch.fault_dar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) OFFSET(VCPU_FAULT_GPA, kvm_vcpu, arch.fault_gpa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) OFFSET(VCPU_INTR_MSR, kvm_vcpu, arch.intr_msr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) OFFSET(VCPU_LAST_INST, kvm_vcpu, arch.last_inst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) OFFSET(VCPU_TRAP, kvm_vcpu, arch.trap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) OFFSET(VCPU_CFAR, kvm_vcpu, arch.cfar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) OFFSET(VCPU_PPR, kvm_vcpu, arch.ppr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) OFFSET(VCPU_FSCR, kvm_vcpu, arch.fscr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) OFFSET(VCPU_PSPB, kvm_vcpu, arch.pspb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) OFFSET(VCPU_EBBHR, kvm_vcpu, arch.ebbhr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) OFFSET(VCPU_EBBRR, kvm_vcpu, arch.ebbrr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) OFFSET(VCPU_BESCR, kvm_vcpu, arch.bescr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) OFFSET(VCPU_CSIGR, kvm_vcpu, arch.csigr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) OFFSET(VCPU_TACR, kvm_vcpu, arch.tacr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) OFFSET(VCPU_TCSCR, kvm_vcpu, arch.tcscr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) OFFSET(VCPU_ACOP, kvm_vcpu, arch.acop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) OFFSET(VCPU_WORT, kvm_vcpu, arch.wort);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) OFFSET(VCPU_TID, kvm_vcpu, arch.tid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) OFFSET(VCPU_PSSCR, kvm_vcpu, arch.psscr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) OFFSET(VCPU_HFSCR, kvm_vcpu, arch.hfscr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) OFFSET(VCORE_ENTRY_EXIT, kvmppc_vcore, entry_exit_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) OFFSET(VCORE_IN_GUEST, kvmppc_vcore, in_guest);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) OFFSET(VCORE_NAPPING_THREADS, kvmppc_vcore, napping_threads);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) OFFSET(VCORE_KVM, kvmppc_vcore, kvm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) OFFSET(VCORE_TB_OFFSET, kvmppc_vcore, tb_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) OFFSET(VCORE_TB_OFFSET_APPL, kvmppc_vcore, tb_offset_applied);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) OFFSET(VCORE_LPCR, kvmppc_vcore, lpcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) OFFSET(VCORE_PCR, kvmppc_vcore, pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) OFFSET(VCORE_DPDES, kvmppc_vcore, dpdes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) OFFSET(VCORE_VTB, kvmppc_vcore, vtb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) OFFSET(VCPU_SLB_E, kvmppc_slb, orige);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) OFFSET(VCPU_SLB_V, kvmppc_slb, origv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) DEFINE(VCPU_SLB_SIZE, sizeof(struct kvmppc_slb));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) OFFSET(VCPU_TFHAR, kvm_vcpu, arch.tfhar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) OFFSET(VCPU_TFIAR, kvm_vcpu, arch.tfiar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) OFFSET(VCPU_TEXASR, kvm_vcpu, arch.texasr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) OFFSET(VCPU_ORIG_TEXASR, kvm_vcpu, arch.orig_texasr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) OFFSET(VCPU_GPR_TM, kvm_vcpu, arch.gpr_tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) OFFSET(VCPU_FPRS_TM, kvm_vcpu, arch.fp_tm.fpr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) OFFSET(VCPU_VRS_TM, kvm_vcpu, arch.vr_tm.vr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) OFFSET(VCPU_VRSAVE_TM, kvm_vcpu, arch.vrsave_tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) OFFSET(VCPU_CR_TM, kvm_vcpu, arch.cr_tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) OFFSET(VCPU_XER_TM, kvm_vcpu, arch.xer_tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) OFFSET(VCPU_LR_TM, kvm_vcpu, arch.lr_tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) OFFSET(VCPU_CTR_TM, kvm_vcpu, arch.ctr_tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) OFFSET(VCPU_AMR_TM, kvm_vcpu, arch.amr_tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) OFFSET(VCPU_PPR_TM, kvm_vcpu, arch.ppr_tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) OFFSET(VCPU_DSCR_TM, kvm_vcpu, arch.dscr_tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) OFFSET(VCPU_TAR_TM, kvm_vcpu, arch.tar_tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #ifdef CONFIG_PPC_BOOK3S_64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) OFFSET(PACA_SVCPU, paca_struct, shadow_vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) # define SVCPU_FIELD(x, f) DEFINE(x, offsetof(struct paca_struct, shadow_vcpu.f))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) # define SVCPU_FIELD(x, f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) # define HSTATE_FIELD(x, f) DEFINE(x, offsetof(struct paca_struct, kvm_hstate.f))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) #else /* 32-bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) # define SVCPU_FIELD(x, f) DEFINE(x, offsetof(struct kvmppc_book3s_shadow_vcpu, f))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) # define HSTATE_FIELD(x, f) DEFINE(x, offsetof(struct kvmppc_book3s_shadow_vcpu, hstate.f))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) SVCPU_FIELD(SVCPU_CR, cr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) SVCPU_FIELD(SVCPU_XER, xer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) SVCPU_FIELD(SVCPU_CTR, ctr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) SVCPU_FIELD(SVCPU_LR, lr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) SVCPU_FIELD(SVCPU_PC, pc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) SVCPU_FIELD(SVCPU_R0, gpr[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) SVCPU_FIELD(SVCPU_R1, gpr[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) SVCPU_FIELD(SVCPU_R2, gpr[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) SVCPU_FIELD(SVCPU_R3, gpr[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) SVCPU_FIELD(SVCPU_R4, gpr[4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) SVCPU_FIELD(SVCPU_R5, gpr[5]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) SVCPU_FIELD(SVCPU_R6, gpr[6]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) SVCPU_FIELD(SVCPU_R7, gpr[7]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) SVCPU_FIELD(SVCPU_R8, gpr[8]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) SVCPU_FIELD(SVCPU_R9, gpr[9]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) SVCPU_FIELD(SVCPU_R10, gpr[10]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) SVCPU_FIELD(SVCPU_R11, gpr[11]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) SVCPU_FIELD(SVCPU_R12, gpr[12]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) SVCPU_FIELD(SVCPU_R13, gpr[13]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) SVCPU_FIELD(SVCPU_FAULT_DSISR, fault_dsisr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) SVCPU_FIELD(SVCPU_FAULT_DAR, fault_dar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) SVCPU_FIELD(SVCPU_LAST_INST, last_inst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) SVCPU_FIELD(SVCPU_SHADOW_SRR1, shadow_srr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) #ifdef CONFIG_PPC_BOOK3S_32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) SVCPU_FIELD(SVCPU_SR, sr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) #ifdef CONFIG_PPC64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) SVCPU_FIELD(SVCPU_SLB, slb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) SVCPU_FIELD(SVCPU_SLB_MAX, slb_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) SVCPU_FIELD(SVCPU_SHADOW_FSCR, shadow_fscr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) HSTATE_FIELD(HSTATE_HOST_R1, host_r1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) HSTATE_FIELD(HSTATE_HOST_R2, host_r2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) HSTATE_FIELD(HSTATE_HOST_MSR, host_msr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) HSTATE_FIELD(HSTATE_VMHANDLER, vmhandler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) HSTATE_FIELD(HSTATE_SCRATCH0, scratch0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) HSTATE_FIELD(HSTATE_SCRATCH1, scratch1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) HSTATE_FIELD(HSTATE_SCRATCH2, scratch2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) HSTATE_FIELD(HSTATE_IN_GUEST, in_guest);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) HSTATE_FIELD(HSTATE_RESTORE_HID5, restore_hid5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) HSTATE_FIELD(HSTATE_NAPPING, napping);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) HSTATE_FIELD(HSTATE_HWTHREAD_REQ, hwthread_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) HSTATE_FIELD(HSTATE_HWTHREAD_STATE, hwthread_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) HSTATE_FIELD(HSTATE_KVM_VCPU, kvm_vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) HSTATE_FIELD(HSTATE_KVM_VCORE, kvm_vcore);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) HSTATE_FIELD(HSTATE_XICS_PHYS, xics_phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) HSTATE_FIELD(HSTATE_XIVE_TIMA_PHYS, xive_tima_phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) HSTATE_FIELD(HSTATE_XIVE_TIMA_VIRT, xive_tima_virt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) HSTATE_FIELD(HSTATE_SAVED_XIRR, saved_xirr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) HSTATE_FIELD(HSTATE_HOST_IPI, host_ipi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) HSTATE_FIELD(HSTATE_PTID, ptid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) HSTATE_FIELD(HSTATE_TID, tid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) HSTATE_FIELD(HSTATE_FAKE_SUSPEND, fake_suspend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) HSTATE_FIELD(HSTATE_MMCR0, host_mmcr[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) HSTATE_FIELD(HSTATE_MMCR1, host_mmcr[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) HSTATE_FIELD(HSTATE_MMCRA, host_mmcr[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) HSTATE_FIELD(HSTATE_SIAR, host_mmcr[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) HSTATE_FIELD(HSTATE_SDAR, host_mmcr[4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) HSTATE_FIELD(HSTATE_MMCR2, host_mmcr[5]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) HSTATE_FIELD(HSTATE_SIER, host_mmcr[6]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) HSTATE_FIELD(HSTATE_MMCR3, host_mmcr[7]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) HSTATE_FIELD(HSTATE_SIER2, host_mmcr[8]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) HSTATE_FIELD(HSTATE_SIER3, host_mmcr[9]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) HSTATE_FIELD(HSTATE_PMC1, host_pmc[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) HSTATE_FIELD(HSTATE_PMC2, host_pmc[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) HSTATE_FIELD(HSTATE_PMC3, host_pmc[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) HSTATE_FIELD(HSTATE_PMC4, host_pmc[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) HSTATE_FIELD(HSTATE_PMC5, host_pmc[4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) HSTATE_FIELD(HSTATE_PMC6, host_pmc[5]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) HSTATE_FIELD(HSTATE_PURR, host_purr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) HSTATE_FIELD(HSTATE_SPURR, host_spurr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) HSTATE_FIELD(HSTATE_DSCR, host_dscr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) HSTATE_FIELD(HSTATE_DABR, dabr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) HSTATE_FIELD(HSTATE_DECEXP, dec_expires);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) HSTATE_FIELD(HSTATE_SPLIT_MODE, kvm_split_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) DEFINE(IPI_PRIORITY, IPI_PRIORITY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) OFFSET(KVM_SPLIT_RPR, kvm_split_mode, rpr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) OFFSET(KVM_SPLIT_PMMAR, kvm_split_mode, pmmar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) OFFSET(KVM_SPLIT_LDBAR, kvm_split_mode, ldbar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) OFFSET(KVM_SPLIT_DO_NAP, kvm_split_mode, do_nap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) OFFSET(KVM_SPLIT_NAPPED, kvm_split_mode, napped);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) OFFSET(KVM_SPLIT_DO_SET, kvm_split_mode, do_set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) OFFSET(KVM_SPLIT_DO_RESTORE, kvm_split_mode, do_restore);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) #endif /* CONFIG_KVM_BOOK3S_HV_POSSIBLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) #ifdef CONFIG_PPC_BOOK3S_64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) HSTATE_FIELD(HSTATE_CFAR, cfar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) HSTATE_FIELD(HSTATE_PPR, ppr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) HSTATE_FIELD(HSTATE_HOST_FSCR, host_fscr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) #endif /* CONFIG_PPC_BOOK3S_64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) #else /* CONFIG_PPC_BOOK3S */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) OFFSET(VCPU_CR, kvm_vcpu, arch.regs.ccr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) OFFSET(VCPU_XER, kvm_vcpu, arch.regs.xer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) OFFSET(VCPU_LR, kvm_vcpu, arch.regs.link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) OFFSET(VCPU_CTR, kvm_vcpu, arch.regs.ctr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) OFFSET(VCPU_PC, kvm_vcpu, arch.regs.nip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) OFFSET(VCPU_SPRG9, kvm_vcpu, arch.sprg9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) OFFSET(VCPU_LAST_INST, kvm_vcpu, arch.last_inst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) OFFSET(VCPU_FAULT_DEAR, kvm_vcpu, arch.fault_dear);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) OFFSET(VCPU_FAULT_ESR, kvm_vcpu, arch.fault_esr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) OFFSET(VCPU_CRIT_SAVE, kvm_vcpu, arch.crit_save);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) #endif /* CONFIG_PPC_BOOK3S */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) #endif /* CONFIG_KVM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) #ifdef CONFIG_KVM_GUEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) OFFSET(KVM_MAGIC_SCRATCH1, kvm_vcpu_arch_shared, scratch1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) OFFSET(KVM_MAGIC_SCRATCH2, kvm_vcpu_arch_shared, scratch2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) OFFSET(KVM_MAGIC_SCRATCH3, kvm_vcpu_arch_shared, scratch3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) OFFSET(KVM_MAGIC_INT, kvm_vcpu_arch_shared, int_pending);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) OFFSET(KVM_MAGIC_MSR, kvm_vcpu_arch_shared, msr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) OFFSET(KVM_MAGIC_CRITICAL, kvm_vcpu_arch_shared, critical);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) OFFSET(KVM_MAGIC_SR, kvm_vcpu_arch_shared, sr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) #ifdef CONFIG_44x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) DEFINE(PGD_T_LOG2, PGD_T_LOG2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) DEFINE(PTE_T_LOG2, PTE_T_LOG2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) #ifdef CONFIG_PPC_FSL_BOOK3E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) DEFINE(TLBCAM_SIZE, sizeof(struct tlbcam));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) OFFSET(TLBCAM_MAS0, tlbcam, MAS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) OFFSET(TLBCAM_MAS1, tlbcam, MAS1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) OFFSET(TLBCAM_MAS2, tlbcam, MAS2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) OFFSET(TLBCAM_MAS3, tlbcam, MAS3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) OFFSET(TLBCAM_MAS7, tlbcam, MAS7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) #if defined(CONFIG_KVM) && defined(CONFIG_SPE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) OFFSET(VCPU_EVR, kvm_vcpu, arch.evr[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) OFFSET(VCPU_ACC, kvm_vcpu, arch.acc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) OFFSET(VCPU_SPEFSCR, kvm_vcpu, arch.spefscr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) OFFSET(VCPU_HOST_SPEFSCR, kvm_vcpu, arch.host_spefscr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) #ifdef CONFIG_KVM_BOOKE_HV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) OFFSET(VCPU_HOST_MAS4, kvm_vcpu, arch.host_mas4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) OFFSET(VCPU_HOST_MAS6, kvm_vcpu, arch.host_mas6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) #ifdef CONFIG_KVM_XICS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) DEFINE(VCPU_XIVE_SAVED_STATE, offsetof(struct kvm_vcpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) arch.xive_saved_state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) DEFINE(VCPU_XIVE_CAM_WORD, offsetof(struct kvm_vcpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) arch.xive_cam_word));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) DEFINE(VCPU_XIVE_PUSHED, offsetof(struct kvm_vcpu, arch.xive_pushed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) DEFINE(VCPU_XIVE_ESC_ON, offsetof(struct kvm_vcpu, arch.xive_esc_on));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) DEFINE(VCPU_XIVE_ESC_RADDR, offsetof(struct kvm_vcpu, arch.xive_esc_raddr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) DEFINE(VCPU_XIVE_ESC_VADDR, offsetof(struct kvm_vcpu, arch.xive_esc_vaddr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) #ifdef CONFIG_KVM_EXIT_TIMING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) OFFSET(VCPU_TIMING_EXIT_TBU, kvm_vcpu, arch.timing_exit.tv32.tbu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) OFFSET(VCPU_TIMING_EXIT_TBL, kvm_vcpu, arch.timing_exit.tv32.tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) OFFSET(VCPU_TIMING_LAST_ENTER_TBU, kvm_vcpu, arch.timing_last_enter.tv32.tbu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) OFFSET(VCPU_TIMING_LAST_ENTER_TBL, kvm_vcpu, arch.timing_last_enter.tv32.tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) DEFINE(PPC_DBELL_SERVER, PPC_DBELL_SERVER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) DEFINE(PPC_DBELL_MSGTYPE, PPC_DBELL_MSGTYPE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) #ifdef CONFIG_PPC_8xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) DEFINE(VIRT_IMMR_BASE, (u64)__fix_to_virt(FIX_IMMR_BASE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) #ifdef CONFIG_XMON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) DEFINE(BPT_SIZE, BPT_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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