Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /* align.c - handle alignment exceptions for the Power PC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (c) 1998-1999 TiVo, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *   PowerPC 403GCX modifications.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *   PowerPC 403GCX/405GP modifications.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Copyright (c) 2001-2002 PPC64 team, IBM Corp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *   64-bit and Power4 support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * Copyright (c) 2005 Benjamin Herrenschmidt, IBM Corp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  *                    <benh@kernel.crashing.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  *   Merge ppc32 and ppc64 implementations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <asm/processor.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <asm/cache.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <asm/cputable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <asm/emulated_ops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <asm/switch_to.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <asm/disassemble.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <asm/cpu_has_feature.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <asm/sstep.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include <asm/inst.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) struct aligninfo {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	unsigned char len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	unsigned char flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define INVALID	{ 0, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) /* Bits in the flags field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define LD	0	/* load */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define ST	1	/* store */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define SE	2	/* sign-extend value, or FP ld/st as word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define SW	0x20	/* byte swap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define E4	0x40	/* SPE endianness is word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define E8	0x80	/* SPE endianness is double word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #ifdef CONFIG_SPE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) static struct aligninfo spe_aligninfo[32] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	{ 8, LD+E8 },		/* 0 00 00: evldd[x] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	{ 8, LD+E4 },		/* 0 00 01: evldw[x] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	{ 8, LD },		/* 0 00 10: evldh[x] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	INVALID,		/* 0 00 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	{ 2, LD },		/* 0 01 00: evlhhesplat[x] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	INVALID,		/* 0 01 01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	{ 2, LD },		/* 0 01 10: evlhhousplat[x] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	{ 2, LD+SE },		/* 0 01 11: evlhhossplat[x] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	{ 4, LD },		/* 0 10 00: evlwhe[x] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	INVALID,		/* 0 10 01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	{ 4, LD },		/* 0 10 10: evlwhou[x] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	{ 4, LD+SE },		/* 0 10 11: evlwhos[x] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	{ 4, LD+E4 },		/* 0 11 00: evlwwsplat[x] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	INVALID,		/* 0 11 01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	{ 4, LD },		/* 0 11 10: evlwhsplat[x] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	INVALID,		/* 0 11 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	{ 8, ST+E8 },		/* 1 00 00: evstdd[x] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	{ 8, ST+E4 },		/* 1 00 01: evstdw[x] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	{ 8, ST },		/* 1 00 10: evstdh[x] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	INVALID,		/* 1 00 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	INVALID,		/* 1 01 00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	INVALID,		/* 1 01 01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	INVALID,		/* 1 01 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	INVALID,		/* 1 01 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	{ 4, ST },		/* 1 10 00: evstwhe[x] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	INVALID,		/* 1 10 01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	{ 4, ST },		/* 1 10 10: evstwho[x] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	INVALID,		/* 1 10 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	{ 4, ST+E4 },		/* 1 11 00: evstwwe[x] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	INVALID,		/* 1 11 01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	{ 4, ST+E4 },		/* 1 11 10: evstwwo[x] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	INVALID,		/* 1 11 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define	EVLDD		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define	EVLDW		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define	EVLDH		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define	EVLHHESPLAT	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define	EVLHHOUSPLAT	0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define	EVLHHOSSPLAT	0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define	EVLWHE		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define	EVLWHOU		0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define	EVLWHOS		0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define	EVLWWSPLAT	0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define	EVLWHSPLAT	0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define	EVSTDD		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define	EVSTDW		0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define	EVSTDH		0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define	EVSTWHE		0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define	EVSTWHO		0x1A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define	EVSTWWE		0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define	EVSTWWO		0x1E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)  * Emulate SPE loads and stores.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)  * Only Book-E has these instructions, and it does true little-endian,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)  * so we don't need the address swizzling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static int emulate_spe(struct pt_regs *regs, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		       struct ppc_inst ppc_instr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		u64 ll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		u32 w[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		u16 h[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		u8 v[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	} data, temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	unsigned char __user *p, *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	unsigned long *evr = &current->thread.evr[reg];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	unsigned int nb, flags, instr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	instr = ppc_inst_val(ppc_instr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	instr = (instr >> 1) & 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	/* DAR has the operand effective address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	addr = (unsigned char __user *)regs->dar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	nb = spe_aligninfo[instr].len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	flags = spe_aligninfo[instr].flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	/* Verify the address of the operand */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	if (unlikely(user_mode(regs) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		     !access_ok(addr, nb)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	/* userland only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	if (unlikely(!user_mode(regs)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	flush_spe_to_thread(current);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	/* If we are loading, get the data from user space, else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	 * get it from register values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	if (flags & ST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		data.ll = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		switch (instr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		case EVSTDD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		case EVSTDW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		case EVSTDH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 			data.w[0] = *evr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 			data.w[1] = regs->gpr[reg];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		case EVSTWHE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 			data.h[2] = *evr >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 			data.h[3] = regs->gpr[reg] >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		case EVSTWHO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 			data.h[2] = *evr & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 			data.h[3] = regs->gpr[reg] & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		case EVSTWWE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 			data.w[1] = *evr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		case EVSTWWO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 			data.w[1] = regs->gpr[reg];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		temp.ll = data.ll = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		p = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		switch (nb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 			ret |= __get_user_inatomic(temp.v[0], p++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 			ret |= __get_user_inatomic(temp.v[1], p++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 			ret |= __get_user_inatomic(temp.v[2], p++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 			ret |= __get_user_inatomic(temp.v[3], p++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 			fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 			ret |= __get_user_inatomic(temp.v[4], p++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 			ret |= __get_user_inatomic(temp.v[5], p++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 			fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 			ret |= __get_user_inatomic(temp.v[6], p++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 			ret |= __get_user_inatomic(temp.v[7], p++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 			if (unlikely(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 				return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		switch (instr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		case EVLDD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		case EVLDW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		case EVLDH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 			data.ll = temp.ll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		case EVLHHESPLAT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 			data.h[0] = temp.h[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 			data.h[2] = temp.h[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		case EVLHHOUSPLAT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		case EVLHHOSSPLAT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 			data.h[1] = temp.h[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 			data.h[3] = temp.h[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		case EVLWHE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 			data.h[0] = temp.h[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 			data.h[2] = temp.h[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		case EVLWHOU:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		case EVLWHOS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 			data.h[1] = temp.h[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 			data.h[3] = temp.h[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		case EVLWWSPLAT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 			data.w[0] = temp.w[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 			data.w[1] = temp.w[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		case EVLWHSPLAT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 			data.h[0] = temp.h[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 			data.h[1] = temp.h[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 			data.h[2] = temp.h[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 			data.h[3] = temp.h[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	if (flags & SW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		switch (flags & 0xf0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		case E8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 			data.ll = swab64(data.ll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		case E4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 			data.w[0] = swab32(data.w[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 			data.w[1] = swab32(data.w[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		/* Its half word endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 			data.h[0] = swab16(data.h[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 			data.h[1] = swab16(data.h[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 			data.h[2] = swab16(data.h[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 			data.h[3] = swab16(data.h[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	if (flags & SE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		data.w[0] = (s16)data.h[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		data.w[1] = (s16)data.h[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	/* Store result to memory or update registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	if (flags & ST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		p = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		switch (nb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 			ret |= __put_user_inatomic(data.v[0], p++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 			ret |= __put_user_inatomic(data.v[1], p++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 			ret |= __put_user_inatomic(data.v[2], p++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 			ret |= __put_user_inatomic(data.v[3], p++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 			fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 			ret |= __put_user_inatomic(data.v[4], p++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 			ret |= __put_user_inatomic(data.v[5], p++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 			fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 			ret |= __put_user_inatomic(data.v[6], p++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 			ret |= __put_user_inatomic(data.v[7], p++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		if (unlikely(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 			return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		*evr = data.w[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		regs->gpr[reg] = data.w[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #endif /* CONFIG_SPE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)  * Called on alignment exception. Attempts to fixup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)  * Return 1 on success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)  * Return 0 if unable to handle the interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)  * Return -EFAULT if data address is bad
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)  * Other negative return values indicate that the instruction can't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)  * be emulated, and the process should be given a SIGBUS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) int fix_alignment(struct pt_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	struct ppc_inst instr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	struct instruction_op op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	int r, type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	 * We require a complete register set, if not, then our assembly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	 * is broken
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	CHECK_FULL_REGS(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	if (unlikely(__get_user_instr(instr, (void __user *)regs->nip)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	if ((regs->msr & MSR_LE) != (MSR_KERNEL & MSR_LE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		/* We don't handle PPC little-endian any more... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		if (cpu_has_feature(CPU_FTR_PPC_LE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 			return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		instr = ppc_inst_swab(instr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #ifdef CONFIG_SPE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	if (ppc_inst_primary_opcode(instr) == 0x4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		int reg = (ppc_inst_val(instr) >> 21) & 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 		PPC_WARN_ALIGNMENT(spe, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		return emulate_spe(regs, reg, instr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	 * ISA 3.0 (such as P9) copy, copy_first, paste and paste_last alignment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	 * check.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	 * Send a SIGBUS to the process that caused the fault.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	 * We do not emulate these because paste may contain additional metadata
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	 * when pasting to a co-processor. Furthermore, paste_last is the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	 * synchronisation point for preceding copy/paste sequences.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	if ((ppc_inst_val(instr) & 0xfc0006fe) == (PPC_INST_COPY & 0xfc0006fe))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	r = analyse_instr(&op, regs, instr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	if (r < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	type = GETTYPE(op.type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	if (!OP_IS_LOAD_STORE(type)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		if (op.type != CACHEOP + DCBZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		PPC_WARN_ALIGNMENT(dcbz, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 		r = emulate_dcbz(op.ea, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		if (type == LARX || type == STCX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 			return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 		PPC_WARN_ALIGNMENT(unaligned, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		r = emulate_loadstore(regs, &op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	if (!r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 		return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }