Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) #ifndef _ASM_POWERPC_VGA_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) #define _ASM_POWERPC_VGA_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) #ifdef __KERNEL__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  *	Access to VGA videoram
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  *	(c) 1998 Martin Mares <mj@ucw.cz>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_MDA_CONSOLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define VT_BUF_HAVE_RW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)  *  These are only needed for supporting VGA or MDA text mode, which use little
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)  *  endian byte ordering.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)  *  In other cases, we can optimize by using native byte ordering and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)  *  <linux/vt_buffer.h> has already done the right job for us.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static inline void scr_writew(u16 val, volatile u16 *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	*addr = cpu_to_le16(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static inline u16 scr_readw(volatile const u16 *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	return le16_to_cpu(*addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define VT_BUF_HAVE_MEMSETW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static inline void scr_memsetw(u16 *s, u16 v, unsigned int n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	memset16(s, cpu_to_le16(v), n / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define VT_BUF_HAVE_MEMCPYW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define VT_BUF_HAVE_MEMMOVEW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define scr_memcpyw	memcpy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define scr_memmovew	memmove
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #endif /* !CONFIG_VGA_CONSOLE && !CONFIG_MDA_CONSOLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #ifdef __powerpc64__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define VGA_MAP_MEM(x,s) ((unsigned long) ioremap((x), s))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define VGA_MAP_MEM(x,s) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define vga_readb(x) (*(x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define vga_writeb(x,y) (*(y) = (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #endif	/* __KERNEL__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #endif	/* _ASM_POWERPC_VGA_H_ */