^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * common routine and memory layout for Tundra TSI108(Grendel) host bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * memory controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Jacob Pan (jacob.pan@freescale.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Alex Bounine (alexandreb@tundra.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright 2004-2006 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #ifndef __PPC_KERNEL_TSI108_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define __PPC_KERNEL_TSI108_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/pci-bridge.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* Size of entire register space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define TSI108_REG_SIZE (0x10000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* Sizes of register spaces for individual blocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define TSI108_HLP_SIZE 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define TSI108_PCI_SIZE 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define TSI108_CLK_SIZE 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define TSI108_PB_SIZE 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define TSI108_SD_SIZE 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define TSI108_DMA_SIZE 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define TSI108_ETH_SIZE 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define TSI108_I2C_SIZE 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TSI108_MPIC_SIZE 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define TSI108_UART0_SIZE 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define TSI108_GPIO_SIZE 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define TSI108_UART1_SIZE 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* Offsets within Tsi108(A) CSR space for individual blocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define TSI108_HLP_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define TSI108_PCI_OFFSET 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define TSI108_CLK_OFFSET 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define TSI108_PB_OFFSET 0x3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define TSI108_SD_OFFSET 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define TSI108_DMA_OFFSET 0x5000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define TSI108_ETH_OFFSET 0x6000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define TSI108_I2C_OFFSET 0x7000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define TSI108_MPIC_OFFSET 0x7400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define TSI108_UART0_OFFSET 0x7800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define TSI108_GPIO_OFFSET 0x7A00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define TSI108_UART1_OFFSET 0x7C00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* Tsi108 registers used by common code components */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define TSI108_PCI_CSR (0x004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define TSI108_PCI_IRP_CFG_CTL (0x180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define TSI108_PCI_IRP_STAT (0x184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define TSI108_PCI_IRP_ENABLE (0x188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define TSI108_PCI_IRP_INTAD (0x18C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define TSI108_PCI_IRP_STAT_P_INT (0x00400000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define TSI108_PCI_IRP_ENABLE_P_INT (0x00400000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define TSI108_CG_PWRUP_STATUS (0x234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define TSI108_PB_ISR (0x00C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define TSI108_PB_ERRCS (0x404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define TSI108_PB_AERR (0x408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define TSI108_PB_ERRCS_ES (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define TSI108_PB_ISR_PBS_RD_ERR (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define TSI108_PCI_CFG_SIZE (0x01000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * PHY Configuration Options
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * Specify "bcm54xx" in the compatible property of your device tree phy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * nodes if your board uses the Broadcom PHYs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define TSI108_PHY_MV88E 0 /* Marvel 88Exxxx PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define TSI108_PHY_BCM54XX 1 /* Broadcom BCM54xx PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* Global variables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) extern u32 tsi108_pci_cfg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* Exported functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) extern int tsi108_direct_write_config(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) int offset, int len, u32 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) extern int tsi108_direct_read_config(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) int offset, int len, u32 * val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) extern void tsi108_clear_pci_error(u32 pci_cfg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) extern phys_addr_t get_csrbase(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u32 regs; /* hw registers base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u32 phyregs; /* phy registers base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u16 phy; /* phy address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u16 irq_num; /* irq number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u8 mac_addr[6]; /* phy mac address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u16 phy_type; /* type of phy on board */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) } hw_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) extern u32 get_vir_csrbase(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) extern u32 tsi108_csr_vir_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static inline u32 tsi108_read_reg(u32 reg_offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return in_be32((volatile u32 *)(tsi108_csr_vir_base + reg_offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static inline void tsi108_write_reg(u32 reg_offset, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) out_be32((volatile u32 *)(tsi108_csr_vir_base + reg_offset), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #endif /* __PPC_KERNEL_TSI108_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags