Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * Rewrite, cleanup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #ifndef _ASM_POWERPC_TCE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define _ASM_POWERPC_TCE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifdef __KERNEL__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/iommu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  * Tces come in two formats, one for the virtual bus and a different
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)  * format for PCI.  PCI TCEs can have hardware or software maintianed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)  * coherency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define TCE_VB			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define TCE_PCI			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* TCE page size is 4096 bytes (1 << 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define TCE_SHIFT	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define TCE_PAGE_SIZE	(1 << TCE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define TCE_ENTRY_SIZE		8		/* each TCE is 64 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TCE_RPN_MASK		0xfffffffffful  /* 40-bit RPN (4K pages) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define TCE_RPN_SHIFT		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define TCE_VALID		0x800		/* TCE valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define TCE_ALLIO		0x400		/* TCE valid for all lpars */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define TCE_PCI_WRITE		0x2		/* write from PCI allowed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define TCE_PCI_READ		0x1		/* read from PCI allowed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define TCE_VB_WRITE		0x1		/* write from VB allowed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #endif /* __KERNEL__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #endif /* _ASM_POWERPC_TCE_H */