Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) #ifndef _ASM_POWERPC_SYNCH_H 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) #define _ASM_POWERPC_SYNCH_H 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) #ifdef __KERNEL__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #include <asm/cputable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #include <asm/feature-fixups.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <asm/ppc-opcode.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) extern unsigned int __start___lwsync_fixup, __stop___lwsync_fixup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) extern void do_lwsync_fixups(unsigned long value, void *fixup_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 			     void *fixup_end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) static inline void eieio(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	__asm__ __volatile__ ("eieio" : : : "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static inline void isync(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	__asm__ __volatile__ ("isync" : : : "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static inline void ppc_after_tlbiel_barrier(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	asm volatile("ptesync": : :"memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	 * POWER9, POWER10 need a cp_abort after tlbiel to ensure the copy is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	 * invalidated correctly. If this is not done, the paste can take data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	 * from the physical address that was translated at copy time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	 * POWER9 in practice does not need this, because address spaces with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	 * accelerators mapped will use tlbie (which does invalidate the copy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	 * to invalidate translations. It's not possible to limit POWER10 this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	 * way due to local copy-paste.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	asm volatile(ASM_FTR_IFSET(PPC_CP_ABORT, "", %0) : : "i" (CPU_FTR_ARCH_31) : "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #endif /* __ASSEMBLY__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #if defined(__powerpc64__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #    define LWSYNC	lwsync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #elif defined(CONFIG_E500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #    define LWSYNC					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	START_LWSYNC_SECTION(96);			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	sync;						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	MAKE_LWSYNC_SECTION_ENTRY(96, __lwsync_fixup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #    define LWSYNC	sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define __PPC_ACQUIRE_BARRIER				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	START_LWSYNC_SECTION(97);			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	isync;						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	MAKE_LWSYNC_SECTION_ENTRY(97, __lwsync_fixup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PPC_ACQUIRE_BARRIER	 "\n" stringify_in_c(__PPC_ACQUIRE_BARRIER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PPC_RELEASE_BARRIER	 stringify_in_c(LWSYNC) "\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PPC_ATOMIC_ENTRY_BARRIER "\n" stringify_in_c(sync) "\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define PPC_ATOMIC_EXIT_BARRIER	 "\n" stringify_in_c(sync) "\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PPC_ACQUIRE_BARRIER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define PPC_RELEASE_BARRIER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define PPC_ATOMIC_ENTRY_BARRIER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define PPC_ATOMIC_EXIT_BARRIER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #endif /* __KERNEL__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #endif	/* _ASM_POWERPC_SYNCH_H */