^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * SPU core / file system interface and HW structures
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * (C) Copyright IBM Deutschland Entwicklung GmbH 2005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Arnd Bergmann <arndb@de.ibm.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef _SPU_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define _SPU_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #ifdef __KERNEL__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/workqueue.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/reg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/copro.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define LS_SIZE (256 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define LS_ADDR_MASK (LS_SIZE - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MFC_PUT_CMD 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MFC_PUTS_CMD 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MFC_PUTR_CMD 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MFC_PUTF_CMD 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MFC_PUTB_CMD 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MFC_PUTFS_CMD 0x2A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MFC_PUTBS_CMD 0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MFC_PUTRF_CMD 0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MFC_PUTRB_CMD 0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MFC_PUTL_CMD 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MFC_PUTRL_CMD 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MFC_PUTLF_CMD 0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MFC_PUTLB_CMD 0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MFC_PUTRLF_CMD 0x36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MFC_PUTRLB_CMD 0x35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MFC_GET_CMD 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MFC_GETS_CMD 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MFC_GETF_CMD 0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MFC_GETB_CMD 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MFC_GETFS_CMD 0x4A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MFC_GETBS_CMD 0x49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MFC_GETL_CMD 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MFC_GETLF_CMD 0x46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MFC_GETLB_CMD 0x45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MFC_SDCRT_CMD 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MFC_SDCRTST_CMD 0x81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MFC_SDCRZ_CMD 0x89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MFC_SDCRS_CMD 0x8D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MFC_SDCRF_CMD 0x8F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MFC_GETLLAR_CMD 0xD0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MFC_PUTLLC_CMD 0xB4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MFC_PUTLLUC_CMD 0xB0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MFC_PUTQLLUC_CMD 0xB8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MFC_SNDSIG_CMD 0xA0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MFC_SNDSIGB_CMD 0xA1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MFC_SNDSIGF_CMD 0xA2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MFC_BARRIER_CMD 0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MFC_EIEIO_CMD 0xC8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MFC_SYNC_CMD 0xCC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MFC_MIN_DMA_SIZE_SHIFT 4 /* 16 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MFC_MAX_DMA_SIZE_SHIFT 14 /* 16384 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MFC_MIN_DMA_SIZE (1 << MFC_MIN_DMA_SIZE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MFC_MAX_DMA_SIZE (1 << MFC_MAX_DMA_SIZE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MFC_MIN_DMA_SIZE_MASK (MFC_MIN_DMA_SIZE - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MFC_MAX_DMA_SIZE_MASK (MFC_MAX_DMA_SIZE - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MFC_MIN_DMA_LIST_SIZE 0x0008 /* 8 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MFC_MAX_DMA_LIST_SIZE 0x4000 /* 16K bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MFC_TAGID_TO_TAGMASK(tag_id) (1 << (tag_id & 0x1F))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* Events for Channels 0-2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MFC_DMA_TAG_STATUS_UPDATE_EVENT 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define MFC_DMA_TAG_CMD_STALL_NOTIFY_EVENT 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define MFC_DMA_QUEUE_AVAILABLE_EVENT 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MFC_SPU_MAILBOX_WRITTEN_EVENT 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define MFC_DECREMENTER_EVENT 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define MFC_PU_INT_MAILBOX_AVAILABLE_EVENT 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define MFC_PU_MAILBOX_AVAILABLE_EVENT 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define MFC_SIGNAL_2_EVENT 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define MFC_SIGNAL_1_EVENT 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define MFC_LLR_LOST_EVENT 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define MFC_PRIV_ATTN_EVENT 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define MFC_MULTI_SRC_EVENT 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* Flag indicating progress during context switch. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SPU_CONTEXT_SWITCH_PENDING 0UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SPU_CONTEXT_FAULT_PENDING 1UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct spu_context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct spu_runqueue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct spu_lscsa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct device_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) enum spu_utilization_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) SPU_UTIL_USER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) SPU_UTIL_SYSTEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) SPU_UTIL_IOWAIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) SPU_UTIL_IDLE_LOADED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) SPU_UTIL_MAX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct spu {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) unsigned long local_store_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u8 *local_store;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) unsigned long problem_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct spu_problem __iomem *problem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct spu_priv2 __iomem *priv2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct list_head cbe_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct list_head full_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) enum { SPU_FREE, SPU_USED } alloc_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) int number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) unsigned int irqs[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u32 node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u64 class_0_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u64 class_0_dar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u64 class_1_dar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u64 class_1_dsisr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) size_t ls_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) unsigned int slb_replace;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct mm_struct *mm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct spu_context *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct spu_runqueue *rq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) unsigned long long timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) pid_t pid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) pid_t tgid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) spinlock_t register_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) void (* wbox_callback)(struct spu *spu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) void (* ibox_callback)(struct spu *spu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) void (* stop_callback)(struct spu *spu, int irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) void (* mfc_callback)(struct spu *spu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) char irq_c0[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) char irq_c1[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) char irq_c2[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) u64 spe_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) void* pdata; /* platform private data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* of based platforms only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct device_node *devnode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* native only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct spu_priv1 __iomem *priv1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* beat only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) u64 shadow_int_mask_RW[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct device dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) int has_mem_affinity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct list_head aff_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* protected by interrupt reentrancy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) enum spu_utilization_state util_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) unsigned long long tstamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) unsigned long long times[SPU_UTIL_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) unsigned long long vol_ctx_switch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) unsigned long long invol_ctx_switch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) unsigned long long min_flt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) unsigned long long maj_flt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) unsigned long long hash_flt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) unsigned long long slb_flt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) unsigned long long class2_intr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) unsigned long long libassist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) } stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct cbe_spu_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct mutex list_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct list_head spus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) int n_spus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) int nr_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) atomic_t busy_spus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) atomic_t reserved_spus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) extern struct cbe_spu_info cbe_spu_info[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) void spu_init_channels(struct spu *spu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) void spu_irq_setaffinity(struct spu *spu, int cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) void spu_setup_kernel_slbs(struct spu *spu, struct spu_lscsa *lscsa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) void *code, int code_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) extern void spu_invalidate_slbs(struct spu *spu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) extern void spu_associate_mm(struct spu *spu, struct mm_struct *mm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) int spu_64k_pages_available(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* Calls from the memory management to the SPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct mm_struct;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) extern void spu_flush_all_slbs(struct mm_struct *mm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* This interface allows a profiler (e.g., OProfile) to store a ref
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * to spu context information that it creates. This caching technique
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * avoids the need to recreate this information after a save/restore operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * Assumes the caller has already incremented the ref count to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * profile_info; then spu_context_destroy must call kref_put
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * on prof_info_kref.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) void spu_set_profile_private_kref(struct spu_context *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct kref *prof_info_kref,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) void ( * prof_info_release) (struct kref *kref));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) void *spu_get_profile_private_kref(struct spu_context *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* system callbacks from the SPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct spu_syscall_block {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) u64 nr_ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) u64 parm[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) extern long spu_sys_callback(struct spu_syscall_block *s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* syscalls implemented in spufs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct file;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct coredump_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) struct spufs_calls {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) long (*create_thread)(const char __user *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) unsigned int flags, umode_t mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct file *neighbor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) long (*spu_run)(struct file *filp, __u32 __user *unpc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) __u32 __user *ustatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) int (*coredump_extra_notes_size)(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) int (*coredump_extra_notes_write)(struct coredump_params *cprm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) void (*notify_spus_active)(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct module *owner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* return status from spu_run, same as in libspe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define SPE_EVENT_DMA_ALIGNMENT 0x0008 /*A DMA alignment error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define SPE_EVENT_SPE_ERROR 0x0010 /*An illegal instruction error*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define SPE_EVENT_SPE_DATA_SEGMENT 0x0020 /*A DMA segmentation error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define SPE_EVENT_SPE_DATA_STORAGE 0x0040 /*A DMA storage error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define SPE_EVENT_INVALID_DMA 0x0800 /* Invalid MFC DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * Flags for sys_spu_create.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define SPU_CREATE_EVENTS_ENABLED 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define SPU_CREATE_GANG 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define SPU_CREATE_NOSCHED 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define SPU_CREATE_ISOLATE 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define SPU_CREATE_AFFINITY_SPU 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define SPU_CREATE_AFFINITY_MEM 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define SPU_CREATE_FLAG_ALL 0x003f /* mask of all valid flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) int register_spu_syscalls(struct spufs_calls *calls);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) void unregister_spu_syscalls(struct spufs_calls *calls);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) int spu_add_dev_attr(struct device_attribute *attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) void spu_remove_dev_attr(struct device_attribute *attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) int spu_add_dev_attr_group(struct attribute_group *attrs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) void spu_remove_dev_attr_group(struct attribute_group *attrs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * Notifier blocks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * oprofile can get notified when a context switch is performed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * on an spe. The notifer function that gets called is passed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * a pointer to the SPU structure as well as the object-id that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * identifies the binary running on that SPU now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * For a context save, the object-id that is passed is zero,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * identifying that the kernel will run from that moment on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * For a context restore, the object-id is the value written
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * to object-id spufs file from user space and the notifer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * function can assume that spu->ctx is valid.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) struct notifier_block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) int spu_switch_event_register(struct notifier_block * n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) int spu_switch_event_unregister(struct notifier_block * n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) extern void notify_spus_active(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) extern void do_notify_spus_active(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * This defines the Local Store, Problem Area and Privilege Area of an SPU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) union mfc_tag_size_class_cmd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) u16 mfc_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) u16 mfc_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) u8 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) u8 mfc_rclassid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) u16 mfc_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) } u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) u32 mfc_size_tag32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) u32 mfc_class_cmd32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) } by32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) u64 all64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) struct mfc_cq_sr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) u64 mfc_cq_data0_RW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) u64 mfc_cq_data1_RW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) u64 mfc_cq_data2_RW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) u64 mfc_cq_data3_RW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) struct spu_problem {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define MS_SYNC_PENDING 1L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) u64 spc_mssync_RW; /* 0x0000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) u8 pad_0x0008_0x3000[0x3000 - 0x0008];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /* DMA Area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) u8 pad_0x3000_0x3004[0x4]; /* 0x3000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) u32 mfc_lsa_W; /* 0x3004 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) u64 mfc_ea_W; /* 0x3008 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) union mfc_tag_size_class_cmd mfc_union_W; /* 0x3010 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) u8 pad_0x3018_0x3104[0xec]; /* 0x3018 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) u32 dma_qstatus_R; /* 0x3104 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) u8 pad_0x3108_0x3204[0xfc]; /* 0x3108 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) u32 dma_querytype_RW; /* 0x3204 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) u8 pad_0x3208_0x321c[0x14]; /* 0x3208 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) u32 dma_querymask_RW; /* 0x321c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) u8 pad_0x3220_0x322c[0xc]; /* 0x3220 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) u32 dma_tagstatus_R; /* 0x322c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define DMA_TAGSTATUS_INTR_ANY 1u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define DMA_TAGSTATUS_INTR_ALL 2u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) u8 pad_0x3230_0x4000[0x4000 - 0x3230]; /* 0x3230 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /* SPU Control Area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) u8 pad_0x4000_0x4004[0x4]; /* 0x4000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) u32 pu_mb_R; /* 0x4004 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) u8 pad_0x4008_0x400c[0x4]; /* 0x4008 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) u32 spu_mb_W; /* 0x400c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) u8 pad_0x4010_0x4014[0x4]; /* 0x4010 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) u32 mb_stat_R; /* 0x4014 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) u8 pad_0x4018_0x401c[0x4]; /* 0x4018 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) u32 spu_runcntl_RW; /* 0x401c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define SPU_RUNCNTL_STOP 0L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define SPU_RUNCNTL_RUNNABLE 1L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define SPU_RUNCNTL_ISOLATE 2L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) u8 pad_0x4020_0x4024[0x4]; /* 0x4020 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) u32 spu_status_R; /* 0x4024 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define SPU_STOP_STATUS_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define SPU_STATUS_STOPPED 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define SPU_STATUS_RUNNING 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define SPU_STATUS_STOPPED_BY_STOP 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define SPU_STATUS_STOPPED_BY_HALT 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define SPU_STATUS_WAITING_FOR_CHANNEL 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define SPU_STATUS_SINGLE_STEP 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define SPU_STATUS_INVALID_INSTR 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define SPU_STATUS_INVALID_CH 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define SPU_STATUS_ISOLATED_STATE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define SPU_STATUS_ISOLATED_LOAD_STATUS 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define SPU_STATUS_ISOLATED_EXIT_STATUS 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) u8 pad_0x4028_0x402c[0x4]; /* 0x4028 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) u32 spu_spe_R; /* 0x402c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) u8 pad_0x4030_0x4034[0x4]; /* 0x4030 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) u32 spu_npc_RW; /* 0x4034 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) u8 pad_0x4038_0x14000[0x14000 - 0x4038]; /* 0x4038 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /* Signal Notification Area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) u8 pad_0x14000_0x1400c[0xc]; /* 0x14000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) u32 signal_notify1; /* 0x1400c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) u8 pad_0x14010_0x1c00c[0x7ffc]; /* 0x14010 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) u32 signal_notify2; /* 0x1c00c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) } __attribute__ ((aligned(0x20000)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /* SPU Privilege 2 State Area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) struct spu_priv2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) /* MFC Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) u8 pad_0x0000_0x1100[0x1100 - 0x0000]; /* 0x0000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /* SLB Management Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) u8 pad_0x1100_0x1108[0x8]; /* 0x1100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) u64 slb_index_W; /* 0x1108 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define SLB_INDEX_MASK 0x7L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) u64 slb_esid_RW; /* 0x1110 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) u64 slb_vsid_RW; /* 0x1118 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define SLB_VSID_SUPERVISOR_STATE (0x1ull << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define SLB_VSID_SUPERVISOR_STATE_MASK (0x1ull << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define SLB_VSID_PROBLEM_STATE (0x1ull << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define SLB_VSID_PROBLEM_STATE_MASK (0x1ull << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define SLB_VSID_EXECUTE_SEGMENT (0x1ull << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define SLB_VSID_NO_EXECUTE_SEGMENT (0x1ull << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define SLB_VSID_EXECUTE_SEGMENT_MASK (0x1ull << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define SLB_VSID_4K_PAGE (0x0 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define SLB_VSID_LARGE_PAGE (0x1ull << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define SLB_VSID_PAGE_SIZE_MASK (0x1ull << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define SLB_VSID_CLASS_MASK (0x1ull << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define SLB_VSID_VIRTUAL_PAGE_SIZE_MASK (0x1ull << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) u64 slb_invalidate_entry_W; /* 0x1120 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) u64 slb_invalidate_all_W; /* 0x1128 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) u8 pad_0x1130_0x2000[0x2000 - 0x1130]; /* 0x1130 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /* Context Save / Restore Area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) struct mfc_cq_sr spuq[16]; /* 0x2000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) struct mfc_cq_sr puq[8]; /* 0x2200 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) u8 pad_0x2300_0x3000[0x3000 - 0x2300]; /* 0x2300 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /* MFC Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) u64 mfc_control_RW; /* 0x3000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define MFC_CNTL_RESUME_DMA_QUEUE (0ull << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define MFC_CNTL_SUSPEND_DMA_QUEUE (1ull << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define MFC_CNTL_SUSPEND_DMA_QUEUE_MASK (1ull << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define MFC_CNTL_SUSPEND_MASK (1ull << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define MFC_CNTL_NORMAL_DMA_QUEUE_OPERATION (0ull << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define MFC_CNTL_SUSPEND_IN_PROGRESS (1ull << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define MFC_CNTL_SUSPEND_COMPLETE (3ull << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define MFC_CNTL_SUSPEND_DMA_STATUS_MASK (3ull << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define MFC_CNTL_DMA_QUEUES_EMPTY (1ull << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define MFC_CNTL_DMA_QUEUES_EMPTY_MASK (1ull << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define MFC_CNTL_PURGE_DMA_REQUEST (1ull << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define MFC_CNTL_PURGE_DMA_IN_PROGRESS (1ull << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define MFC_CNTL_PURGE_DMA_COMPLETE (3ull << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define MFC_CNTL_PURGE_DMA_STATUS_MASK (3ull << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define MFC_CNTL_RESTART_DMA_COMMAND (1ull << 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define MFC_CNTL_DMA_COMMAND_REISSUE_PENDING (1ull << 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define MFC_CNTL_DMA_COMMAND_REISSUE_STATUS_MASK (1ull << 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define MFC_CNTL_MFC_PRIVILEGE_STATE (2ull << 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define MFC_CNTL_MFC_PROBLEM_STATE (3ull << 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define MFC_CNTL_MFC_KEY_PROTECTION_STATE_MASK (3ull << 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define MFC_CNTL_DECREMENTER_HALTED (1ull << 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define MFC_CNTL_DECREMENTER_RUNNING (1ull << 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define MFC_CNTL_DECREMENTER_STATUS_MASK (1ull << 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) u8 pad_0x3008_0x4000[0x4000 - 0x3008]; /* 0x3008 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /* Interrupt Mailbox */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) u64 puint_mb_R; /* 0x4000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) u8 pad_0x4008_0x4040[0x4040 - 0x4008]; /* 0x4008 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) /* SPU Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) u64 spu_privcntl_RW; /* 0x4040 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define SPU_PRIVCNTL_MODE_NORMAL (0x0ull << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define SPU_PRIVCNTL_MODE_SINGLE_STEP (0x1ull << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define SPU_PRIVCNTL_MODE_MASK (0x1ull << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define SPU_PRIVCNTL_NO_ATTENTION_EVENT (0x0ull << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define SPU_PRIVCNTL_ATTENTION_EVENT (0x1ull << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define SPU_PRIVCNTL_ATTENTION_EVENT_MASK (0x1ull << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define SPU_PRIVCNT_LOAD_REQUEST_NORMAL (0x0ull << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define SPU_PRIVCNT_LOAD_REQUEST_ENABLE_MASK (0x1ull << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) u8 pad_0x4048_0x4058[0x10]; /* 0x4048 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) u64 spu_lslr_RW; /* 0x4058 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) u64 spu_chnlcntptr_RW; /* 0x4060 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) u64 spu_chnlcnt_RW; /* 0x4068 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) u64 spu_chnldata_RW; /* 0x4070 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) u64 spu_cfg_RW; /* 0x4078 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) u8 pad_0x4080_0x5000[0x5000 - 0x4080]; /* 0x4080 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) /* PV2_ImplRegs: Implementation-specific privileged-state 2 regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) u64 spu_pm_trace_tag_status_RW; /* 0x5000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) u64 spu_tag_status_query_RW; /* 0x5008 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define TAG_STATUS_QUERY_CONDITION_BITS (0x3ull << 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define TAG_STATUS_QUERY_MASK_BITS (0xffffffffull)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) u64 spu_cmd_buf1_RW; /* 0x5010 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define SPU_COMMAND_BUFFER_1_LSA_BITS (0x7ffffull << 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define SPU_COMMAND_BUFFER_1_EAH_BITS (0xffffffffull)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) u64 spu_cmd_buf2_RW; /* 0x5018 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define SPU_COMMAND_BUFFER_2_EAL_BITS ((0xffffffffull) << 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define SPU_COMMAND_BUFFER_2_TS_BITS (0xffffull << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define SPU_COMMAND_BUFFER_2_TAG_BITS (0x3full)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) u64 spu_atomic_status_RW; /* 0x5020 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) } __attribute__ ((aligned(0x20000)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /* SPU Privilege 1 State Area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) struct spu_priv1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) /* Control and Configuration Area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) u64 mfc_sr1_RW; /* 0x000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define MFC_STATE1_LOCAL_STORAGE_DECODE_MASK 0x01ull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define MFC_STATE1_BUS_TLBIE_MASK 0x02ull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define MFC_STATE1_REAL_MODE_OFFSET_ENABLE_MASK 0x04ull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define MFC_STATE1_PROBLEM_STATE_MASK 0x08ull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define MFC_STATE1_RELOCATE_MASK 0x10ull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define MFC_STATE1_MASTER_RUN_CONTROL_MASK 0x20ull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define MFC_STATE1_TABLE_SEARCH_MASK 0x40ull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) u64 mfc_lpid_RW; /* 0x008 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) u64 spu_idr_RW; /* 0x010 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) u64 mfc_vr_RO; /* 0x018 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define MFC_VERSION_BITS (0xffff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define MFC_REVISION_BITS (0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define MFC_GET_VERSION_BITS(vr) (((vr) & MFC_VERSION_BITS) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define MFC_GET_REVISION_BITS(vr) ((vr) & MFC_REVISION_BITS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) u64 spu_vr_RO; /* 0x020 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define SPU_VERSION_BITS (0xffff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define SPU_REVISION_BITS (0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define SPU_GET_VERSION_BITS(vr) (vr & SPU_VERSION_BITS) >> 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define SPU_GET_REVISION_BITS(vr) (vr & SPU_REVISION_BITS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) u8 pad_0x28_0x100[0x100 - 0x28]; /* 0x28 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) /* Interrupt Area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) u64 int_mask_RW[3]; /* 0x100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define CLASS0_ENABLE_DMA_ALIGNMENT_INTR 0x1L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define CLASS0_ENABLE_INVALID_DMA_COMMAND_INTR 0x2L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define CLASS0_ENABLE_SPU_ERROR_INTR 0x4L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define CLASS0_ENABLE_MFC_FIR_INTR 0x8L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define CLASS1_ENABLE_SEGMENT_FAULT_INTR 0x1L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define CLASS1_ENABLE_STORAGE_FAULT_INTR 0x2L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define CLASS1_ENABLE_LS_COMPARE_SUSPEND_ON_GET_INTR 0x4L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define CLASS1_ENABLE_LS_COMPARE_SUSPEND_ON_PUT_INTR 0x8L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define CLASS2_ENABLE_MAILBOX_INTR 0x1L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define CLASS2_ENABLE_SPU_STOP_INTR 0x2L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define CLASS2_ENABLE_SPU_HALT_INTR 0x4L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define CLASS2_ENABLE_SPU_DMA_TAG_GROUP_COMPLETE_INTR 0x8L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define CLASS2_ENABLE_MAILBOX_THRESHOLD_INTR 0x10L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) u8 pad_0x118_0x140[0x28]; /* 0x118 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) u64 int_stat_RW[3]; /* 0x140 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define CLASS0_DMA_ALIGNMENT_INTR 0x1L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define CLASS0_INVALID_DMA_COMMAND_INTR 0x2L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define CLASS0_SPU_ERROR_INTR 0x4L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define CLASS0_INTR_MASK 0x7L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define CLASS1_SEGMENT_FAULT_INTR 0x1L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define CLASS1_STORAGE_FAULT_INTR 0x2L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define CLASS1_LS_COMPARE_SUSPEND_ON_GET_INTR 0x4L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define CLASS1_LS_COMPARE_SUSPEND_ON_PUT_INTR 0x8L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define CLASS1_INTR_MASK 0xfL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define CLASS2_MAILBOX_INTR 0x1L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define CLASS2_SPU_STOP_INTR 0x2L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define CLASS2_SPU_HALT_INTR 0x4L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define CLASS2_SPU_DMA_TAG_GROUP_COMPLETE_INTR 0x8L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define CLASS2_MAILBOX_THRESHOLD_INTR 0x10L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define CLASS2_INTR_MASK 0x1fL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) u8 pad_0x158_0x180[0x28]; /* 0x158 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) u64 int_route_RW; /* 0x180 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) /* Interrupt Routing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) u8 pad_0x188_0x200[0x200 - 0x188]; /* 0x188 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) /* Atomic Unit Control Area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) u64 mfc_atomic_flush_RW; /* 0x200 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define mfc_atomic_flush_enable 0x1L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) u8 pad_0x208_0x280[0x78]; /* 0x208 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) u64 resource_allocation_groupID_RW; /* 0x280 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) u64 resource_allocation_enable_RW; /* 0x288 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) u8 pad_0x290_0x3c8[0x3c8 - 0x290]; /* 0x290 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) /* SPU_Cache_ImplRegs: Implementation-dependent cache registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) u64 smf_sbi_signal_sel; /* 0x3c8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define smf_sbi_mask_lsb 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define smf_sbi_shift (63 - smf_sbi_mask_lsb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define smf_sbi_mask (0x301LL << smf_sbi_shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define smf_sbi_bus0_bits (0x001LL << smf_sbi_shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define smf_sbi_bus2_bits (0x100LL << smf_sbi_shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define smf_sbi2_bus0_bits (0x201LL << smf_sbi_shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define smf_sbi2_bus2_bits (0x300LL << smf_sbi_shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) u64 smf_ato_signal_sel; /* 0x3d0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define smf_ato_mask_lsb 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define smf_ato_shift (63 - smf_ato_mask_lsb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define smf_ato_mask (0x3LL << smf_ato_shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define smf_ato_bus0_bits (0x2LL << smf_ato_shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define smf_ato_bus2_bits (0x1LL << smf_ato_shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) u8 pad_0x3d8_0x400[0x400 - 0x3d8]; /* 0x3d8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) /* TLB Management Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) u64 mfc_sdr_RW; /* 0x400 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) u8 pad_0x408_0x500[0xf8]; /* 0x408 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) u64 tlb_index_hint_RO; /* 0x500 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) u64 tlb_index_W; /* 0x508 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) u64 tlb_vpn_RW; /* 0x510 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) u64 tlb_rpn_RW; /* 0x518 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) u8 pad_0x520_0x540[0x20]; /* 0x520 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) u64 tlb_invalidate_entry_W; /* 0x540 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) u64 tlb_invalidate_all_W; /* 0x548 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) u8 pad_0x550_0x580[0x580 - 0x550]; /* 0x550 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) /* SPU_MMU_ImplRegs: Implementation-dependent MMU registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) u64 smm_hid; /* 0x580 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define PAGE_SIZE_MASK 0xf000000000000000ull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define PAGE_SIZE_16MB_64KB 0x2000000000000000ull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) u8 pad_0x588_0x600[0x600 - 0x588]; /* 0x588 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) /* MFC Status/Control Area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) u64 mfc_accr_RW; /* 0x600 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define MFC_ACCR_EA_ACCESS_GET (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define MFC_ACCR_EA_ACCESS_PUT (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #define MFC_ACCR_LS_ACCESS_GET (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define MFC_ACCR_LS_ACCESS_PUT (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) u8 pad_0x608_0x610[0x8]; /* 0x608 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) u64 mfc_dsisr_RW; /* 0x610 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #define MFC_DSISR_PTE_NOT_FOUND (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #define MFC_DSISR_ACCESS_DENIED (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #define MFC_DSISR_ATOMIC (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #define MFC_DSISR_ACCESS_PUT (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #define MFC_DSISR_ADDR_MATCH (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define MFC_DSISR_LS (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #define MFC_DSISR_L (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define MFC_DSISR_ADDRESS_OVERFLOW (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) u8 pad_0x618_0x620[0x8]; /* 0x618 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) u64 mfc_dar_RW; /* 0x620 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) u8 pad_0x628_0x700[0x700 - 0x628]; /* 0x628 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) /* Replacement Management Table (RMT) Area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) u64 rmt_index_RW; /* 0x700 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) u8 pad_0x708_0x710[0x8]; /* 0x708 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) u64 rmt_data1_RW; /* 0x710 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) u8 pad_0x718_0x800[0x800 - 0x718]; /* 0x718 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) /* Control/Configuration Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) u64 mfc_dsir_R; /* 0x800 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #define MFC_DSIR_Q (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #define MFC_DSIR_SPU_QUEUE MFC_DSIR_Q
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) u64 mfc_lsacr_RW; /* 0x808 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #define MFC_LSACR_COMPARE_MASK ((~0ull) << 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define MFC_LSACR_COMPARE_ADDR ((~0ull) >> 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) u64 mfc_lscrr_R; /* 0x810 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #define MFC_LSCRR_Q (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define MFC_LSCRR_SPU_QUEUE MFC_LSCRR_Q
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define MFC_LSCRR_QI_SHIFT 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define MFC_LSCRR_QI_MASK ((~0ull) << MFC_LSCRR_QI_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) u8 pad_0x818_0x820[0x8]; /* 0x818 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) u64 mfc_tclass_id_RW; /* 0x820 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) #define MFC_TCLASS_ID_ENABLE (1L << 0L)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #define MFC_TCLASS_SLOT2_ENABLE (1L << 5L)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) #define MFC_TCLASS_SLOT1_ENABLE (1L << 6L)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) #define MFC_TCLASS_SLOT0_ENABLE (1L << 7L)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #define MFC_TCLASS_QUOTA_2_SHIFT 8L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #define MFC_TCLASS_QUOTA_1_SHIFT 16L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) #define MFC_TCLASS_QUOTA_0_SHIFT 24L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) #define MFC_TCLASS_QUOTA_2_MASK (0x1FL << MFC_TCLASS_QUOTA_2_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) #define MFC_TCLASS_QUOTA_1_MASK (0x1FL << MFC_TCLASS_QUOTA_1_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) #define MFC_TCLASS_QUOTA_0_MASK (0x1FL << MFC_TCLASS_QUOTA_0_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) u8 pad_0x828_0x900[0x900 - 0x828]; /* 0x828 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) /* Real Mode Support Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) u64 mfc_rm_boundary; /* 0x900 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) u8 pad_0x908_0x938[0x30]; /* 0x908 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) u64 smf_dma_signal_sel; /* 0x938 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) #define mfc_dma1_mask_lsb 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) #define mfc_dma1_shift (63 - mfc_dma1_mask_lsb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) #define mfc_dma1_mask (0x3LL << mfc_dma1_shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) #define mfc_dma1_bits (0x1LL << mfc_dma1_shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) #define mfc_dma2_mask_lsb 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) #define mfc_dma2_shift (63 - mfc_dma2_mask_lsb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) #define mfc_dma2_mask (0x3LL << mfc_dma2_shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) #define mfc_dma2_bits (0x1LL << mfc_dma2_shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) u8 pad_0x940_0xa38[0xf8]; /* 0x940 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) u64 smm_signal_sel; /* 0xa38 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) #define smm_sig_mask_lsb 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) #define smm_sig_shift (63 - smm_sig_mask_lsb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) #define smm_sig_mask (0x3LL << smm_sig_shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) #define smm_sig_bus0_bits (0x2LL << smm_sig_shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) #define smm_sig_bus2_bits (0x1LL << smm_sig_shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) u8 pad_0xa40_0xc00[0xc00 - 0xa40]; /* 0xa40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) /* DMA Command Error Area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) u64 mfc_cer_R; /* 0xc00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) #define MFC_CER_Q (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) #define MFC_CER_SPU_QUEUE MFC_CER_Q
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) u8 pad_0xc08_0x1000[0x1000 - 0xc08]; /* 0xc08 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) /* PV1_ImplRegs: Implementation-dependent privileged-state 1 regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) /* DMA Command Error Area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) u64 spu_ecc_cntl_RW; /* 0x1000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) #define SPU_ECC_CNTL_E (1ull << 0ull)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) #define SPU_ECC_CNTL_ENABLE SPU_ECC_CNTL_E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) #define SPU_ECC_CNTL_DISABLE (~SPU_ECC_CNTL_E & 1L)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) #define SPU_ECC_CNTL_S (1ull << 1ull)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) #define SPU_ECC_STOP_AFTER_ERROR SPU_ECC_CNTL_S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) #define SPU_ECC_CONTINUE_AFTER_ERROR (~SPU_ECC_CNTL_S & 2L)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) #define SPU_ECC_CNTL_B (1ull << 2ull)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) #define SPU_ECC_BACKGROUND_ENABLE SPU_ECC_CNTL_B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) #define SPU_ECC_BACKGROUND_DISABLE (~SPU_ECC_CNTL_B & 4L)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) #define SPU_ECC_CNTL_I_SHIFT 3ull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) #define SPU_ECC_CNTL_I_MASK (3ull << SPU_ECC_CNTL_I_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) #define SPU_ECC_WRITE_ALWAYS (~SPU_ECC_CNTL_I & 12L)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) #define SPU_ECC_WRITE_CORRECTABLE (1ull << SPU_ECC_CNTL_I_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) #define SPU_ECC_WRITE_UNCORRECTABLE (3ull << SPU_ECC_CNTL_I_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) #define SPU_ECC_CNTL_D (1ull << 5ull)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) #define SPU_ECC_DETECTION_ENABLE SPU_ECC_CNTL_D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) #define SPU_ECC_DETECTION_DISABLE (~SPU_ECC_CNTL_D & 32L)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) u64 spu_ecc_stat_RW; /* 0x1008 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) #define SPU_ECC_CORRECTED_ERROR (1ull << 0ul)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) #define SPU_ECC_UNCORRECTED_ERROR (1ull << 1ul)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) #define SPU_ECC_SCRUB_COMPLETE (1ull << 2ul)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) #define SPU_ECC_SCRUB_IN_PROGRESS (1ull << 3ul)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) #define SPU_ECC_INSTRUCTION_ERROR (1ull << 4ul)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) #define SPU_ECC_DATA_ERROR (1ull << 5ul)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) #define SPU_ECC_DMA_ERROR (1ull << 6ul)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) #define SPU_ECC_STATUS_CNT_MASK (256ull << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) u64 spu_ecc_addr_RW; /* 0x1010 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) u64 spu_err_mask_RW; /* 0x1018 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) #define SPU_ERR_ILLEGAL_INSTR (1ull << 0ul)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) #define SPU_ERR_ILLEGAL_CHANNEL (1ull << 1ul)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) u8 pad_0x1020_0x1028[0x1028 - 0x1020]; /* 0x1020 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) /* SPU Debug-Trace Bus (DTB) Selection Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) u64 spu_trig0_sel; /* 0x1028 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) u64 spu_trig1_sel; /* 0x1030 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) u64 spu_trig2_sel; /* 0x1038 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) u64 spu_trig3_sel; /* 0x1040 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) u64 spu_trace_sel; /* 0x1048 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) #define spu_trace_sel_mask 0x1f1fLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) #define spu_trace_sel_bus0_bits 0x1000LL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) #define spu_trace_sel_bus2_bits 0x0010LL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) u64 spu_event0_sel; /* 0x1050 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) u64 spu_event1_sel; /* 0x1058 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) u64 spu_event2_sel; /* 0x1060 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) u64 spu_event3_sel; /* 0x1068 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) u64 spu_trace_cntl; /* 0x1070 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) } __attribute__ ((aligned(0x2000)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) #endif /* __KERNEL__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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