^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef _SMU_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define _SMU_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Definitions for talking to the SMU chip in newer G5 PowerMacs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifdef __KERNEL__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Known SMU commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Most of what is below comes from looking at the Open Firmware driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * though this is still incomplete and could use better documentation here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * or there...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * Partition info commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * These commands are used to retrieve the sdb-partition-XX datas from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * the SMU. The length is always 2. First byte is the subcommand code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * and second byte is the partition ID.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * The reply is 6 bytes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * - 0..1 : partition address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * - 2 : a byte containing the partition ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * - 3 : length (maybe other bits are rest of header ?)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * The data must then be obtained with calls to another command:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * SMU_CMD_MISC_ee_GET_DATABLOCK_REC (described below).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SMU_CMD_PARTITION_COMMAND 0x3e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SMU_CMD_PARTITION_LATEST 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SMU_CMD_PARTITION_BASE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SMU_CMD_PARTITION_UPDATE 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * Fan control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * This is a "mux" for fan control commands. The command seem to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * act differently based on the number of arguments. With 1 byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * of argument, this seem to be queries for fans status, setpoint,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * etc..., while with 0xe arguments, we will set the fans speeds.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * Queries (1 byte arg):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * ---------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * arg=0x01: read RPM fans status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * arg=0x02: read RPM fans setpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * arg=0x11: read PWM fans status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * arg=0x12: read PWM fans setpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * the "status" queries return the current speed while the "setpoint" ones
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * return the programmed/target speed. It _seems_ that the result is a bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * mask in the first byte of active/available fans, followed by 6 words (16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * bits) containing the requested speed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * Setpoint (14 bytes arg):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * ------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * first arg byte is 0 for RPM fans and 0x10 for PWM. Second arg byte is the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * mask of fans affected by the command. Followed by 6 words containing the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * setpoint value for selected fans in the mask (or 0 if mask value is 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SMU_CMD_FAN_COMMAND 0x4a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * Battery access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * Same command number as the PMU, could it be same syntax ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SMU_CMD_BATTERY_COMMAND 0x6f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SMU_CMD_GET_BATTERY_INFO 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * Real time clock control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * This is a "mux", first data byte contains the "sub" command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * The "RTC" part of the SMU controls the date, time, powerup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * timer, but also a PRAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * Dates are in BCD format on 7 bytes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * [sec] [min] [hour] [weekday] [month day] [month] [year]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * with month being 1 based and year minus 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SMU_CMD_RTC_COMMAND 0x8e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SMU_CMD_RTC_SET_PWRUP_TIMER 0x00 /* i: 7 bytes date */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SMU_CMD_RTC_GET_PWRUP_TIMER 0x01 /* o: 7 bytes date */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SMU_CMD_RTC_STOP_PWRUP_TIMER 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SMU_CMD_RTC_SET_PRAM_BYTE_ACC 0x20 /* i: 1 byte (address?) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SMU_CMD_RTC_SET_PRAM_AUTOINC 0x21 /* i: 1 byte (data?) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SMU_CMD_RTC_SET_PRAM_LO_BYTES 0x22 /* i: 10 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SMU_CMD_RTC_SET_PRAM_HI_BYTES 0x23 /* i: 10 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SMU_CMD_RTC_GET_PRAM_BYTE 0x28 /* i: 1 bytes (address?) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SMU_CMD_RTC_GET_PRAM_LO_BYTES 0x29 /* o: 10 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SMU_CMD_RTC_GET_PRAM_HI_BYTES 0x2a /* o: 10 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SMU_CMD_RTC_SET_DATETIME 0x80 /* i: 7 bytes date */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SMU_CMD_RTC_GET_DATETIME 0x81 /* o: 7 bytes date */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * i2c commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * To issue an i2c command, first is to send a parameter block to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * the SMU. This is a command of type 0x9a with 9 bytes of header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * eventually followed by data for a write:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * 0: bus number (from device-tree usually, SMU has lots of busses !)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * 1: transfer type/format (see below)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * 2: device address. For combined and combined4 type transfers, this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * is the "write" version of the address (bit 0x01 cleared)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * 3: subaddress length (0..3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * 4: subaddress byte 0 (or only byte for subaddress length 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * 5: subaddress byte 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * 6: subaddress byte 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * 7: combined address (device address for combined mode data phase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * 8: data length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * The transfer types are the same good old Apple ones it seems,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * that is:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * - 0x00: Simple transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * - 0x01: Subaddress transfer (addr write + data tx, no restart)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * - 0x02: Combined transfer (addr write + restart + data tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * This is then followed by actual data for a write.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * At this point, the OF driver seems to have a limitation on transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * sizes of 0xd bytes on reads and 0x5 bytes on writes. I do not know
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * whether this is just an OF limit due to some temporary buffer size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * or if this is an SMU imposed limit. This driver has the same limitation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * for now as I use a 0x10 bytes temporary buffer as well
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * Once that is completed, a response is expected from the SMU. This is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * obtained via a command of type 0x9a with a length of 1 byte containing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * 0 as the data byte. OF also fills the rest of the data buffer with 0xff's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * though I can't tell yet if this is actually necessary. Once this command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * is complete, at this point, all I can tell is what OF does. OF tests
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * byte 0 of the reply:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * - on read, 0xfe or 0xfc : bus is busy, wait (see below) or nak ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * - on read, 0x00 or 0x01 : reply is in buffer (after the byte 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * - on write, < 0 -> failure (immediate exit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * - else, OF just exists (without error, weird)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * So on read, there is this wait-for-busy thing when getting a 0xfc or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * 0xfe result. OF does a loop of up to 64 retries, waiting 20ms and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * doing the above again until either the retries expire or the result
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * is no longer 0xfe or 0xfc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * The Darwin I2C driver is less subtle though. On any non-success status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * from the response command, it waits 5ms and tries again up to 20 times,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * it doesn't differentiate between fatal errors or "busy" status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * This driver provides an asynchronous paramblock based i2c command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * interface to be used either directly by low level code or by a higher
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * level driver interfacing to the linux i2c layer. The current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * implementation of this relies on working timers & timer interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * though, so be careful of calling context for now. This may be "fixed"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * in the future by adding a polling facility.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define SMU_CMD_I2C_COMMAND 0x9a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* transfer types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define SMU_I2C_TRANSFER_SIMPLE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define SMU_I2C_TRANSFER_STDSUB 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define SMU_I2C_TRANSFER_COMBINED 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * Power supply control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * The "sub" command is an ASCII string in the data, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * data length is that of the string.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * The VSLEW command can be used to get or set the voltage slewing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * - length 5 (only "VSLEW") : it returns "DONE" and 3 bytes of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * reply at data offset 6, 7 and 8.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * - length 8 ("VSLEWxyz") has 3 additional bytes appended, and is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * used to set the voltage slewing point. The SMU replies with "DONE"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * I yet have to figure out their exact meaning of those 3 bytes in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * both cases. They seem to be:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * x = processor mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * y = op. point index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * z = processor freq. step index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * I haven't yet deciphered result codes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define SMU_CMD_POWER_COMMAND 0xaa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define SMU_CMD_POWER_RESTART "RESTART"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define SMU_CMD_POWER_SHUTDOWN "SHUTDOWN"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define SMU_CMD_POWER_VOLTAGE_SLEW "VSLEW"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * Read ADC sensors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * This command takes one byte of parameter: the sensor ID (or "reg"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * value in the device-tree) and returns a 16 bits value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define SMU_CMD_READ_ADC 0xd8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* Misc commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * This command seem to be a grab bag of various things
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * Parameters:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * 1: subcommand
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define SMU_CMD_MISC_df_COMMAND 0xdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * Sets "system ready" status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * I did not yet understand how it exactly works or what it does.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * Guessing from OF code, 0x02 activates the display backlight. Apple uses/used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * the same codebase for all OF versions. On PowerBooks, this command would
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * enable the backlight. For the G5s, it only activates the front LED. However,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * don't take this for granted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * Parameters:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * 2: status [0x00, 0x01 or 0x02]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define SMU_CMD_MISC_df_SET_DISPLAY_LIT 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * Sets mode of power switch.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * What this actually does is not yet known. Maybe it enables some interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * Parameters:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * 2: enable power switch? [0x00 or 0x01]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * 3 (optional): enable nmi? [0x00 or 0x01]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * If parameter 2 is 0x00 and parameter 3 is not specified, returns whether
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * NMI is enabled. Otherwise unknown.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define SMU_CMD_MISC_df_NMI_OPTION 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* Sets LED dimm offset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * The front LED dimms itself during sleep. Its brightness (or, well, the PWM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * frequency) depends on current time. Therefore, the SMU needs to know the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * timezone.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * Parameters:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * 2-8: unknown (BCD coding)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define SMU_CMD_MISC_df_DIMM_OFFSET 0x99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * Version info commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * Parameters:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * 1 (optional): Specifies version part to retrieve
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * Version value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define SMU_CMD_VERSION_COMMAND 0xea
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define SMU_VERSION_RUNNING 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define SMU_VERSION_BASE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define SMU_VERSION_UPDATE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * Switches
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * These are switches whose status seems to be known to the SMU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * Parameters:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * none
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * Result:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * Switch bits (ORed, see below)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define SMU_CMD_SWITCHES 0xdc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* Switches bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define SMU_SWITCH_CASE_CLOSED 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define SMU_SWITCH_AC_POWER 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define SMU_SWITCH_POWER_SWITCH 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * Misc commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * This command seem to be a grab bag of various things
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * SMU_CMD_MISC_ee_GET_DATABLOCK_REC is used, among others, to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * transfer blocks of data from the SMU. So far, I've decrypted it's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * usage to retrieve partition data. In order to do that, you have to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * break your transfer in "chunks" since that command cannot transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * more than a chunk at a time. The chunk size used by OF is 0xe bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * but it seems that the darwin driver will let you do 0x1e bytes if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * your "PMU" version is >= 0x30. You can get the "PMU" version apparently
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * either in the last 16 bits of property "smu-version-pmu" or as the 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * bytes at offset 1 of "smu-version-info"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * For each chunk, the command takes 7 bytes of arguments:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * byte 0: subcommand code (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * byte 1: 0x04 (always, I don't know what it means, maybe the address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * space to use or some other nicety. It's hard coded in OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * byte 2..5: SMU address of the chunk (big endian 32 bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * byte 6: size to transfer (up to max chunk size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * The data is returned directly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define SMU_CMD_MISC_ee_COMMAND 0xee
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define SMU_CMD_MISC_ee_GET_DATABLOCK_REC 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /* Retrieves currently used watts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * Parameters:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * 1: 0x03 (Meaning unknown)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define SMU_CMD_MISC_ee_GET_WATTS 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define SMU_CMD_MISC_ee_LEDS_CTRL 0x04 /* i: 00 (00,01) [00] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define SMU_CMD_MISC_ee_GET_DATA 0x05 /* i: 00 , o: ?? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * Power related commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * Parameters:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * 1: subcommand
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define SMU_CMD_POWER_EVENTS_COMMAND 0x8f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* SMU_POWER_EVENTS subcommands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) SMU_PWR_GET_POWERUP_EVENTS = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) SMU_PWR_SET_POWERUP_EVENTS = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) SMU_PWR_CLR_POWERUP_EVENTS = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) SMU_PWR_GET_WAKEUP_EVENTS = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) SMU_PWR_SET_WAKEUP_EVENTS = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) SMU_PWR_CLR_WAKEUP_EVENTS = 0x05,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * Get last shutdown cause
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * 1 byte (signed char): Last shutdown cause. Exact meaning unknown.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) SMU_PWR_LAST_SHUTDOWN_CAUSE = 0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * Sets or gets server ID. Meaning or use is unknown.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * Parameters:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * 2 (optional): Set server ID (1 byte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * 1 byte (server ID?)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) SMU_PWR_SERVER_ID = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /* Power events wakeup bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) SMU_PWR_WAKEUP_KEY = 0x01, /* Wake on key press */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) SMU_PWR_WAKEUP_AC_INSERT = 0x02, /* Wake on AC adapter plug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) SMU_PWR_WAKEUP_AC_CHANGE = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) SMU_PWR_WAKEUP_LID_OPEN = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) SMU_PWR_WAKEUP_RING = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * - Kernel side interface -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #ifdef __KERNEL__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) * Asynchronous SMU commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) * Fill up this structure and submit it via smu_queue_command(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * and get notified by the optional done() callback, or because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) * status becomes != 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) struct smu_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) struct smu_cmd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /* public */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) u8 cmd; /* command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) int data_len; /* data len */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) int reply_len; /* reply len */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) void *data_buf; /* data buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) void *reply_buf; /* reply buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) int status; /* command status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) void (*done)(struct smu_cmd *cmd, void *misc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) void *misc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) /* private */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) struct list_head link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * Queues an SMU command, all fields have to be initialized
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) extern int smu_queue_cmd(struct smu_cmd *cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) * Simple command wrapper. This structure embeds a small buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * to ease sending simple SMU commands from the stack
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) struct smu_simple_cmd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) struct smu_cmd cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) u8 buffer[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) * Queues a simple command. All fields will be initialized by that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) * function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) extern int smu_queue_simple(struct smu_simple_cmd *scmd, u8 command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) unsigned int data_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) void (*done)(struct smu_cmd *cmd, void *misc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) void *misc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) ...);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) * Completion helper. Pass it to smu_queue_simple or as 'done'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) * member to smu_queue_cmd, it will call complete() on the struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) * completion passed in the "misc" argument
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) extern void smu_done_complete(struct smu_cmd *cmd, void *misc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * Synchronous helpers. Will spin-wait for completion of a command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) extern void smu_spinwait_cmd(struct smu_cmd *cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static inline void smu_spinwait_simple(struct smu_simple_cmd *scmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) smu_spinwait_cmd(&scmd->cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) * Poll routine to call if blocked with irqs off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) extern void smu_poll(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) * Init routine, presence check....
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) extern int smu_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) extern int smu_present(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) struct platform_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) extern struct platform_device *smu_get_ofdev(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) * Common command wrappers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) extern void smu_shutdown(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) extern void smu_restart(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) struct rtc_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) extern int smu_get_rtc_time(struct rtc_time *time, int spinwait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) extern int smu_set_rtc_time(struct rtc_time *time, int spinwait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) * Kernel asynchronous i2c interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define SMU_I2C_READ_MAX 0x1d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define SMU_I2C_WRITE_MAX 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) /* SMU i2c header, exactly matches i2c header on wire */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) struct smu_i2c_param
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) u8 bus; /* SMU bus ID (from device tree) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) u8 type; /* i2c transfer type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) u8 devaddr; /* device address (includes direction) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) u8 sublen; /* subaddress length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) u8 subaddr[3]; /* subaddress */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) u8 caddr; /* combined address, filled by SMU driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) u8 datalen; /* length of transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) u8 data[SMU_I2C_READ_MAX]; /* data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) struct smu_i2c_cmd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /* public */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) struct smu_i2c_param info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) void (*done)(struct smu_i2c_cmd *cmd, void *misc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) void *misc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) int status; /* 1 = pending, 0 = ok, <0 = fail */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) /* private */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) struct smu_cmd scmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) int read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) int stage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) int retries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) u8 pdata[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) struct list_head link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) * Call this to queue an i2c command to the SMU. You must fill info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) * including info.data for a write, done and misc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) * For now, no polling interface is provided so you have to use completion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) * callback.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) extern int smu_queue_i2c(struct smu_i2c_cmd *cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #endif /* __KERNEL__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) * - SMU "sdb" partitions informations -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) * Partition header format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) struct smu_sdbp_header {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) __u8 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) __u8 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) __u8 version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) __u8 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) * demangle 16 and 32 bits integer in some SMU partitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) * (currently, afaik, this concerns only the FVT partition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) * (0x12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define SMU_U16_MIX(x) le16_to_cpu(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define SMU_U32_MIX(x) ((((x) & 0xff00ff00u) >> 8)|(((x) & 0x00ff00ffu) << 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) /* This is the definition of the SMU sdb-partition-0x12 table (called
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) * CPU F/V/T operating points in Darwin). The definition for all those
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) * SMU tables should be moved to some separate file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define SMU_SDB_FVT_ID 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) struct smu_sdbp_fvt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) __u32 sysclk; /* Base SysClk frequency in Hz for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) * this operating point. Value need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) * be unmixed with SMU_U32_MIX()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) __u8 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) __u8 maxtemp; /* Max temp. supported by this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) * operating point
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) __u16 volts[3]; /* CPU core voltage for the 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) * PowerTune modes, a mode with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) * 0V = not supported. Value need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) * to be unmixed with SMU_U16_MIX()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) /* This partition contains voltage & current sensor calibration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) * informations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define SMU_SDB_CPUVCP_ID 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) struct smu_sdbp_cpuvcp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) __u16 volt_scale; /* u4.12 fixed point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) __s16 volt_offset; /* s4.12 fixed point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) __u16 curr_scale; /* u4.12 fixed point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) __s16 curr_offset; /* s4.12 fixed point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) __s32 power_quads[3]; /* s4.28 fixed point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) /* This partition contains CPU thermal diode calibration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define SMU_SDB_CPUDIODE_ID 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) struct smu_sdbp_cpudiode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) __u16 m_value; /* u1.15 fixed point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) __s16 b_value; /* s10.6 fixed point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) /* This partition contains Slots power calibration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define SMU_SDB_SLOTSPOW_ID 0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) struct smu_sdbp_slotspow {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) __u16 pow_scale; /* u4.12 fixed point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) __s16 pow_offset; /* s4.12 fixed point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) /* This partition contains machine specific version information about
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) * the sensor/control layout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #define SMU_SDB_SENSORTREE_ID 0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) struct smu_sdbp_sensortree {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) __u8 model_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) __u8 unknown[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) /* This partition contains CPU thermal control PID informations. So far
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) * only single CPU machines have been seen with an SMU, so we assume this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) * carries only informations for those
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define SMU_SDB_CPUPIDDATA_ID 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) struct smu_sdbp_cpupiddata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) __u8 unknown1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) __u8 target_temp_delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) __u8 unknown2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) __u8 history_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) __s16 power_adj;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) __u16 max_power;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) __s32 gp,gr,gd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) /* Other partitions without known structures */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #define SMU_SDB_DEBUG_SWITCHES_ID 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) #ifdef __KERNEL__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) * This returns the pointer to an SMU "sdb" partition data or NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) * if not found. The data format is described below
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) extern const struct smu_sdbp_header *smu_get_sdb_partition(int id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) unsigned int *size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) /* Get "sdb" partition data from an SMU satellite */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) extern struct smu_sdbp_header *smu_sat_get_sdb_partition(unsigned int sat_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) int id, unsigned int *size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) #endif /* __KERNEL__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) * - Userland interface -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) * A given instance of the device can be configured for 2 different
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) * things at the moment:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) * - sending SMU commands (default at open() time)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) * - receiving SMU events (not yet implemented)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) * Commands are written with write() of a command block. They can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) * "driver" commands (for example to switch to event reception mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) * or real SMU commands. They are made of a header followed by command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) * data if any.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) * For SMU commands (not for driver commands), you can then read() back
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) * a reply. The reader will be blocked or not depending on how the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) * file is opened. poll() isn't implemented yet. The reply will consist
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) * of a header as well, followed by the reply data if any. You should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) * always provide a buffer large enough for the maximum reply data, I
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) * recommand one page.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) * It is illegal to send SMU commands through a file descriptor configured
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) * for events reception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) struct smu_user_cmd_hdr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) __u32 cmdtype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) #define SMU_CMDTYPE_SMU 0 /* SMU command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) #define SMU_CMDTYPE_WANTS_EVENTS 1 /* switch fd to events mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) #define SMU_CMDTYPE_GET_PARTITION 2 /* retrieve an sdb partition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) __u8 cmd; /* SMU command byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) __u8 pad[3]; /* padding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) __u32 data_len; /* Length of data following */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) struct smu_user_reply_hdr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) __u32 status; /* Command status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) __u32 reply_len; /* Length of data follwing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) #endif /* _SMU_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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