^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Contains the definition of registers common to all PowerPC variants.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * If a register definition has been changed in a different PowerPC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * variant, we will case it in #ifndef XXX ... #endif, and have the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * number used in the Programming Environments Manual For 32-Bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Implementations of the PowerPC Architecture (a.k.a. Green Book) here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef _ASM_POWERPC_REG_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define _ASM_POWERPC_REG_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #ifdef __KERNEL__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/stringify.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/const.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/cputable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/asm-const.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/feature-fixups.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* Pickup Book E specific registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/reg_booke.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #endif /* CONFIG_BOOKE || CONFIG_40x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #ifdef CONFIG_FSL_EMB_PERFMON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/reg_fsl_emb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <asm/reg_8xx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MSR_SF_LG 63 /* Enable 64 bit mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MSR_ISF_LG 61 /* Interrupt 64b mode valid on 630 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MSR_HV_LG 60 /* Hypervisor state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MSR_TS_T_LG 34 /* Trans Mem state: Transactional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MSR_TS_S_LG 33 /* Trans Mem state: Suspended */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MSR_TS_LG 33 /* Trans Mem state (2 bits) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MSR_TM_LG 32 /* Trans Mem Available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MSR_VEC_LG 25 /* Enable AltiVec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MSR_VSX_LG 23 /* Enable VSX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MSR_S_LG 22 /* Secure state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MSR_POW_LG 18 /* Enable Power Management */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MSR_WE_LG 18 /* Wait State Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MSR_TGPR_LG 17 /* TLB Update registers in use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MSR_CE_LG 17 /* Critical Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MSR_ILE_LG 16 /* Interrupt Little Endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MSR_EE_LG 15 /* External Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MSR_PR_LG 14 /* Problem State / Privilege Level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MSR_FP_LG 13 /* Floating Point enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MSR_ME_LG 12 /* Machine Check Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MSR_FE0_LG 11 /* Floating Exception mode 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MSR_SE_LG 10 /* Single Step */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MSR_BE_LG 9 /* Branch Trace */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MSR_DE_LG 9 /* Debug Exception Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MSR_FE1_LG 8 /* Floating Exception mode 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MSR_IP_LG 6 /* Exception prefix 0x000/0xFFF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MSR_IR_LG 5 /* Instruction Relocate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MSR_DR_LG 4 /* Data Relocate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MSR_PE_LG 3 /* Protection Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MSR_PX_LG 2 /* Protection Exclusive Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MSR_PMM_LG 2 /* Performance monitor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MSR_RI_LG 1 /* Recoverable Exception */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MSR_LE_LG 0 /* Little Endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #ifdef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define __MASK(X) (1<<(X))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define __MASK(X) (1UL<<(X))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #ifdef CONFIG_PPC64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MSR_SF __MASK(MSR_SF_LG) /* Enable 64 bit mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MSR_ISF __MASK(MSR_ISF_LG) /* Interrupt 64b mode valid on 630 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MSR_HV __MASK(MSR_HV_LG) /* Hypervisor state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MSR_S __MASK(MSR_S_LG) /* Secure state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* so tests for these bits fail on 32-bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define MSR_SF 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MSR_ISF 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define MSR_HV 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define MSR_S 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * To be used in shared book E/book S, this avoids needing to worry about
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * book S/book E in shared code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #ifndef MSR_SPE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define MSR_SPE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define MSR_VEC __MASK(MSR_VEC_LG) /* Enable AltiVec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define MSR_VSX __MASK(MSR_VSX_LG) /* Enable VSX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define MSR_POW __MASK(MSR_POW_LG) /* Enable Power Management */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define MSR_WE __MASK(MSR_WE_LG) /* Wait State Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define MSR_TGPR __MASK(MSR_TGPR_LG) /* TLB Update registers in use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define MSR_CE __MASK(MSR_CE_LG) /* Critical Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define MSR_ILE __MASK(MSR_ILE_LG) /* Interrupt Little Endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define MSR_EE __MASK(MSR_EE_LG) /* External Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define MSR_PR __MASK(MSR_PR_LG) /* Problem State / Privilege Level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define MSR_FP __MASK(MSR_FP_LG) /* Floating Point enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define MSR_ME __MASK(MSR_ME_LG) /* Machine Check Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define MSR_FE0 __MASK(MSR_FE0_LG) /* Floating Exception mode 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define MSR_SE __MASK(MSR_SE_LG) /* Single Step */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define MSR_BE __MASK(MSR_BE_LG) /* Branch Trace */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define MSR_DE __MASK(MSR_DE_LG) /* Debug Exception Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define MSR_FE1 __MASK(MSR_FE1_LG) /* Floating Exception mode 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define MSR_IP __MASK(MSR_IP_LG) /* Exception prefix 0x000/0xFFF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define MSR_IR __MASK(MSR_IR_LG) /* Instruction Relocate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define MSR_DR __MASK(MSR_DR_LG) /* Data Relocate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define MSR_PE __MASK(MSR_PE_LG) /* Protection Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define MSR_PX __MASK(MSR_PX_LG) /* Protection Exclusive Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #ifndef MSR_PMM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define MSR_PMM __MASK(MSR_PMM_LG) /* Performance monitor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define MSR_RI __MASK(MSR_RI_LG) /* Recoverable Exception */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define MSR_LE __MASK(MSR_LE_LG) /* Little Endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define MSR_TM __MASK(MSR_TM_LG) /* Transactional Mem Available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define MSR_TS_N 0 /* Non-transactional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define MSR_TS_S __MASK(MSR_TS_S_LG) /* Transaction Suspended */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define MSR_TS_T __MASK(MSR_TS_T_LG) /* Transaction Transactional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define MSR_TS_MASK (MSR_TS_T | MSR_TS_S) /* Transaction State bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define MSR_TM_RESV(x) (((x) & MSR_TS_MASK) == MSR_TS_MASK) /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define MSR_TM_TRANSACTIONAL(x) (((x) & MSR_TS_MASK) == MSR_TS_T)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define MSR_TM_SUSPENDED(x) (((x) & MSR_TS_MASK) == MSR_TS_S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define MSR_TM_ACTIVE(x) (((x) & MSR_TS_MASK) != 0) /* Transaction active? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define MSR_TM_ACTIVE(x) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #if defined(CONFIG_PPC_BOOK3S_64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define MSR_64BIT MSR_SF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* Server variant */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define __MSR (MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_ISF |MSR_HV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #ifdef __BIG_ENDIAN__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define MSR_ __MSR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define MSR_IDLE (MSR_ME | MSR_SF | MSR_HV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define MSR_ (__MSR | MSR_LE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define MSR_IDLE (MSR_ME | MSR_SF | MSR_HV | MSR_LE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define MSR_KERNEL (MSR_ | MSR_64BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define MSR_USER32 (MSR_ | MSR_PR | MSR_EE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define MSR_USER64 (MSR_USER32 | MSR_64BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #elif defined(CONFIG_PPC_BOOK3S_32) || defined(CONFIG_PPC_8xx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* Default MSR for kernel mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define MSR_USER (MSR_KERNEL|MSR_PR|MSR_EE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #ifndef MSR_64BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define MSR_64BIT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* Condition Register related */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define CR0_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define CR0_MASK 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define CR0_TBEGIN_FAILURE (0x2 << 28) /* 0b0010 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* Power Management - Processor Stop Status and Control Register Fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define PSSCR_RL_MASK 0x0000000F /* Requested Level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define PSSCR_MTL_MASK 0x000000F0 /* Maximum Transition Level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define PSSCR_TR_MASK 0x00000300 /* Transition State */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define PSSCR_PSLL_MASK 0x000F0000 /* Power-Saving Level Limit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define PSSCR_EC 0x00100000 /* Exit Criterion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define PSSCR_ESL 0x00200000 /* Enable State Loss */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define PSSCR_SD 0x00400000 /* Status Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define PSSCR_PLS 0xf000000000000000 /* Power-saving Level Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define PSSCR_PLS_SHIFT 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define PSSCR_GUEST_VIS 0xf0000000000003ffUL /* Guest-visible PSSCR fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define PSSCR_FAKE_SUSPEND 0x00000400 /* Fake-suspend bit (P9 DD2.2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define PSSCR_FAKE_SUSPEND_LG 10 /* Fake-suspend bit position */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* Floating Point Status and Control Register (FPSCR) Fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define FPSCR_FX 0x80000000 /* FPU exception summary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define FPSCR_FEX 0x40000000 /* FPU enabled exception summary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define FPSCR_VX 0x20000000 /* Invalid operation summary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define FPSCR_OX 0x10000000 /* Overflow exception summary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define FPSCR_UX 0x08000000 /* Underflow exception summary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define FPSCR_ZX 0x04000000 /* Zero-divide exception summary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define FPSCR_XX 0x02000000 /* Inexact exception summary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define FPSCR_VXSNAN 0x01000000 /* Invalid op for SNaN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define FPSCR_VXISI 0x00800000 /* Invalid op for Inv - Inv */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define FPSCR_VXIDI 0x00400000 /* Invalid op for Inv / Inv */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define FPSCR_VXZDZ 0x00200000 /* Invalid op for Zero / Zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define FPSCR_VXIMZ 0x00100000 /* Invalid op for Inv * Zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define FPSCR_VXVC 0x00080000 /* Invalid op for Compare */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define FPSCR_FR 0x00040000 /* Fraction rounded */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define FPSCR_FI 0x00020000 /* Fraction inexact */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define FPSCR_FPRF 0x0001f000 /* FPU Result Flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define FPSCR_FPCC 0x0000f000 /* FPU Condition Codes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define FPSCR_VXSOFT 0x00000400 /* Invalid op for software request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define FPSCR_VXSQRT 0x00000200 /* Invalid op for square root */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define FPSCR_VXCVI 0x00000100 /* Invalid op for integer convert */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define FPSCR_VE 0x00000080 /* Invalid op exception enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define FPSCR_OE 0x00000040 /* IEEE overflow exception enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define FPSCR_UE 0x00000020 /* IEEE underflow exception enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define FPSCR_ZE 0x00000010 /* IEEE zero divide exception enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define FPSCR_XE 0x00000008 /* FP inexact exception enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define FPSCR_NI 0x00000004 /* FPU non IEEE-Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define FPSCR_RN 0x00000003 /* FPU rounding control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* Bit definitions for SPEFSCR. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define SPEFSCR_SOVH 0x80000000 /* Summary integer overflow high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define SPEFSCR_OVH 0x40000000 /* Integer overflow high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define SPEFSCR_FGH 0x20000000 /* Embedded FP guard bit high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define SPEFSCR_FXH 0x10000000 /* Embedded FP sticky bit high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define SPEFSCR_FINVH 0x08000000 /* Embedded FP invalid operation high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define SPEFSCR_FDBZH 0x04000000 /* Embedded FP div by zero high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define SPEFSCR_FUNFH 0x02000000 /* Embedded FP underflow high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define SPEFSCR_FOVFH 0x01000000 /* Embedded FP overflow high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define SPEFSCR_FINXS 0x00200000 /* Embedded FP inexact sticky */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define SPEFSCR_FINVS 0x00100000 /* Embedded FP invalid op. sticky */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define SPEFSCR_FDBZS 0x00080000 /* Embedded FP div by zero sticky */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define SPEFSCR_FUNFS 0x00040000 /* Embedded FP underflow sticky */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define SPEFSCR_FOVFS 0x00020000 /* Embedded FP overflow sticky */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define SPEFSCR_MODE 0x00010000 /* Embedded FP mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define SPEFSCR_SOV 0x00008000 /* Integer summary overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define SPEFSCR_OV 0x00004000 /* Integer overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define SPEFSCR_FG 0x00002000 /* Embedded FP guard bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define SPEFSCR_FX 0x00001000 /* Embedded FP sticky bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define SPEFSCR_FINV 0x00000800 /* Embedded FP invalid operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define SPEFSCR_FDBZ 0x00000400 /* Embedded FP div by zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define SPEFSCR_FUNF 0x00000200 /* Embedded FP underflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define SPEFSCR_FOVF 0x00000100 /* Embedded FP overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define SPEFSCR_FINXE 0x00000040 /* Embedded FP inexact enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define SPEFSCR_FINVE 0x00000020 /* Embedded FP invalid op. enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define SPEFSCR_FDBZE 0x00000010 /* Embedded FP div by zero enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define SPEFSCR_FUNFE 0x00000008 /* Embedded FP underflow enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define SPEFSCR_FOVFE 0x00000004 /* Embedded FP overflow enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define SPEFSCR_FRMC 0x00000003 /* Embedded FP rounding mode control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* Special Purpose Registers (SPRNs)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #ifdef CONFIG_40x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define SPRN_PID 0x3B1 /* Process ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define SPRN_PID 0x030 /* Process ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #ifdef CONFIG_BOOKE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define SPRN_PID0 SPRN_PID/* Process ID Register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define SPRN_CTR 0x009 /* Count Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define SPRN_DSCR 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define SPRN_CFAR 0x1c /* Come From Address Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define SPRN_AMR 0x1d /* Authority Mask Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define SPRN_UAMOR 0x9d /* User Authority Mask Override Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define SPRN_AMOR 0x15d /* Authority Mask Override Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define SPRN_ACOP 0x1F /* Available Coprocessor Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define SPRN_TFIAR 0x81 /* Transaction Failure Inst Addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define SPRN_TEXASR 0x82 /* Transaction EXception & Summary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define SPRN_TEXASRU 0x83 /* '' '' '' Upper 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define TEXASR_FC_LG (63 - 7) /* Failure Code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define TEXASR_AB_LG (63 - 31) /* Abort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define TEXASR_SU_LG (63 - 32) /* Suspend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define TEXASR_HV_LG (63 - 34) /* Hypervisor state*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define TEXASR_PR_LG (63 - 35) /* Privilege level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define TEXASR_FS_LG (63 - 36) /* failure summary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define TEXASR_EX_LG (63 - 37) /* TFIAR exact bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define TEXASR_ROT_LG (63 - 38) /* ROT bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define TEXASR_ABORT __MASK(TEXASR_AB_LG) /* terminated by tabort or treclaim */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define TEXASR_SUSP __MASK(TEXASR_SU_LG) /* tx failed in suspended state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define TEXASR_HV __MASK(TEXASR_HV_LG) /* MSR[HV] when failure occurred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define TEXASR_PR __MASK(TEXASR_PR_LG) /* MSR[PR] when failure occurred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define TEXASR_FS __MASK(TEXASR_FS_LG) /* TEXASR Failure Summary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define TEXASR_EXACT __MASK(TEXASR_EX_LG) /* TFIAR value is exact */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define TEXASR_ROT __MASK(TEXASR_ROT_LG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define TEXASR_FC (ASM_CONST(0xFF) << TEXASR_FC_LG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define SPRN_TFHAR 0x80 /* Transaction Failure Handler Addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define SPRN_TIDR 144 /* Thread ID register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define SPRN_CTRLF 0x088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define SPRN_CTRLT 0x098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define CTRL_CT 0xc0000000 /* current thread */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define CTRL_CT0 0x80000000 /* thread 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define CTRL_CT1 0x40000000 /* thread 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define CTRL_TE 0x00c00000 /* thread enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define CTRL_RUNLATCH 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define SPRN_DAWR0 0xB4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define SPRN_DAWR1 0xB5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define SPRN_RPR 0xBA /* Relative Priority Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define SPRN_CIABR 0xBB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define CIABR_PRIV 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define CIABR_PRIV_USER 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define CIABR_PRIV_SUPER 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define CIABR_PRIV_HYPER 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define SPRN_DAWRX0 0xBC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define SPRN_DAWRX1 0xBD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define DAWRX_USER __MASK(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define DAWRX_KERNEL __MASK(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define DAWRX_HYP __MASK(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define DAWRX_WTI __MASK(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define DAWRX_WT __MASK(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define DAWRX_DR __MASK(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define DAWRX_DW __MASK(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define SPRN_DABR2 0x13D /* e300 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define SPRN_DABRX 0x3F7 /* Data Address Breakpoint Register Extension */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define DABRX_USER __MASK(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define DABRX_KERNEL __MASK(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define DABRX_HYP __MASK(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define DABRX_BTI __MASK(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define DABRX_ALL (DABRX_BTI | DABRX_HYP | DABRX_KERNEL | DABRX_USER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define SPRN_DAR 0x013 /* Data Address Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define SPRN_DBCR 0x136 /* e300 Data Breakpoint Control Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define DSISR_BAD_DIRECT_ST 0x80000000 /* Obsolete: Direct store error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define DSISR_NOHPTE 0x40000000 /* no translation found */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define DSISR_ATTR_CONFLICT 0x20000000 /* P9: Process vs. Partition attr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define DSISR_NOEXEC_OR_G 0x10000000 /* Alias of SRR1 bit, see below */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define DSISR_PROTFAULT 0x08000000 /* protection fault */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define DSISR_BADACCESS 0x04000000 /* bad access to CI or G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define DSISR_ISSTORE 0x02000000 /* access was a store */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define DSISR_DABRMATCH 0x00400000 /* hit data breakpoint */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define DSISR_NOSEGMENT 0x00200000 /* STAB miss (unsupported) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define DSISR_KEYFAULT 0x00200000 /* Storage Key fault */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define DSISR_BAD_EXT_CTRL 0x00100000 /* Obsolete: External ctrl error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define DSISR_UNSUPP_MMU 0x00080000 /* P9: Unsupported MMU config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define DSISR_SET_RC 0x00040000 /* P9: Failed setting of R/C bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define DSISR_PRTABLE_FAULT 0x00020000 /* P9: Fault on process table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define DSISR_ICSWX_NO_CT 0x00004000 /* P7: icswx unavailable cp type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define DSISR_BAD_COPYPASTE 0x00000008 /* P9: Copy/Paste on wrong memtype */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define DSISR_BAD_AMO 0x00000004 /* P9: Incorrect AMO opcode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define DSISR_BAD_CI_LDST 0x00000002 /* P8: Bad HV CI load/store */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) * DSISR_NOEXEC_OR_G doesn't actually exist. This bit is always
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * 0 on DSIs. However, on ISIs, the corresponding bit in SRR1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * indicates an attempt at executing from a no-execute PTE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * or segment or from a guarded page.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * We add a definition here for completeness as we alias
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) * DSISR and SRR1 in do_page_fault.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * DSISR bits that are treated as a fault. Any bit set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * here will skip hash_page, and cause do_page_fault to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * trigger a SIGBUS or SIGSEGV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define DSISR_BAD_FAULT_32S (DSISR_BAD_DIRECT_ST | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) DSISR_BADACCESS | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) DSISR_BAD_EXT_CTRL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define DSISR_BAD_FAULT_64S (DSISR_BAD_FAULT_32S | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) DSISR_ATTR_CONFLICT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) DSISR_UNSUPP_MMU | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) DSISR_PRTABLE_FAULT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) DSISR_ICSWX_NO_CT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) DSISR_BAD_COPYPASTE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) DSISR_BAD_AMO | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) DSISR_BAD_CI_LDST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * These bits are equivalent in SRR1 and DSISR for 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * instruction access interrupts on Book3S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define DSISR_SRR1_MATCH_32S (DSISR_NOHPTE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) DSISR_NOEXEC_OR_G | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) DSISR_PROTFAULT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define DSISR_SRR1_MATCH_64S (DSISR_SRR1_MATCH_32S | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) DSISR_KEYFAULT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) DSISR_UNSUPP_MMU | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) DSISR_SET_RC | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) DSISR_PRTABLE_FAULT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define SPRN_TBRL 0x10C /* Time Base Read Lower Register (user, R/O) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define SPRN_TBRU 0x10D /* Time Base Read Upper Register (user, R/O) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define SPRN_CIR 0x11B /* Chip Information Register (hyper, R/0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define SPRN_TBWL 0x11C /* Time Base Lower Register (super, R/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define SPRN_TBWU 0x11D /* Time Base Upper Register (super, R/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define SPRN_TBU40 0x11E /* Timebase upper 40 bits (hyper, R/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define SPRN_SPURR 0x134 /* Scaled PURR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define SPRN_HSPRG0 0x130 /* Hypervisor Scratch 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define SPRN_HSPRG1 0x131 /* Hypervisor Scratch 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define SPRN_HDSISR 0x132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define SPRN_HDAR 0x133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define SPRN_HDEC 0x136 /* Hypervisor Decrementer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define SPRN_HIOR 0x137 /* 970 Hypervisor interrupt offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define SPRN_RMOR 0x138 /* Real mode offset register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define SPRN_HRMOR 0x139 /* Real mode offset register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define SPRN_HSRR0 0x13A /* Hypervisor Save/Restore 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define SPRN_HSRR1 0x13B /* Hypervisor Save/Restore 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define SPRN_ASDR 0x330 /* Access segment descriptor register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define SPRN_IC 0x350 /* Virtual Instruction Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define SPRN_VTB 0x351 /* Virtual Time Base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define SPRN_LDBAR 0x352 /* LD Base Address Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define SPRN_PMICR 0x354 /* Power Management Idle Control Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define SPRN_PMSR 0x355 /* Power Management Status Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define SPRN_PMMAR 0x356 /* Power Management Memory Activity Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define SPRN_PSSCR 0x357 /* Processor Stop Status and Control Register (ISA 3.0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define SPRN_PSSCR_PR 0x337 /* PSSCR ISA 3.0, privileged mode access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define SPRN_PMCR 0x374 /* Power Management Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define SPRN_RWMR 0x375 /* Region-Weighting Mode Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /* HFSCR and FSCR bit numbers are the same */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define FSCR_PREFIX_LG 13 /* Enable Prefix Instructions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define FSCR_SCV_LG 12 /* Enable System Call Vectored */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define FSCR_MSGP_LG 10 /* Enable MSGP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define FSCR_TAR_LG 8 /* Enable Target Address Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define FSCR_EBB_LG 7 /* Enable Event Based Branching */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define FSCR_TM_LG 5 /* Enable Transactional Memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define FSCR_BHRB_LG 4 /* Enable Branch History Rolling Buffer*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define FSCR_PM_LG 3 /* Enable prob/priv access to PMU SPRs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define FSCR_DSCR_LG 2 /* Enable Data Stream Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define FSCR_VECVSX_LG 1 /* Enable VMX/VSX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define FSCR_FP_LG 0 /* Enable Floating Point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define SPRN_FSCR 0x099 /* Facility Status & Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define FSCR_PREFIX __MASK(FSCR_PREFIX_LG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define FSCR_SCV __MASK(FSCR_SCV_LG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define FSCR_TAR __MASK(FSCR_TAR_LG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define FSCR_EBB __MASK(FSCR_EBB_LG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define FSCR_DSCR __MASK(FSCR_DSCR_LG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define SPRN_HFSCR 0xbe /* HV=1 Facility Status & Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define HFSCR_PREFIX __MASK(FSCR_PREFIX_LG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define HFSCR_MSGP __MASK(FSCR_MSGP_LG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define HFSCR_TAR __MASK(FSCR_TAR_LG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define HFSCR_EBB __MASK(FSCR_EBB_LG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define HFSCR_TM __MASK(FSCR_TM_LG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define HFSCR_PM __MASK(FSCR_PM_LG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define HFSCR_BHRB __MASK(FSCR_BHRB_LG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define HFSCR_DSCR __MASK(FSCR_DSCR_LG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define HFSCR_VECVSX __MASK(FSCR_VECVSX_LG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define HFSCR_FP __MASK(FSCR_FP_LG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define HFSCR_INTR_CAUSE (ASM_CONST(0xFF) << 56) /* interrupt cause */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define SPRN_TAR 0x32f /* Target Address Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define SPRN_LPCR 0x13E /* LPAR Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define LPCR_VPM0 ASM_CONST(0x8000000000000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define LPCR_VPM1 ASM_CONST(0x4000000000000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define LPCR_ISL ASM_CONST(0x2000000000000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define LPCR_VC_SH 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define LPCR_DPFD_SH 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define LPCR_DPFD (ASM_CONST(7) << LPCR_DPFD_SH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define LPCR_VRMASD_SH 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define LPCR_VRMASD (ASM_CONST(0x1f) << LPCR_VRMASD_SH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define LPCR_VRMA_L ASM_CONST(0x0008000000000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define LPCR_VRMA_LP0 ASM_CONST(0x0001000000000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define LPCR_VRMA_LP1 ASM_CONST(0x0000800000000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define LPCR_RMLS 0x1C000000 /* Implementation dependent RMO limit sel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define LPCR_RMLS_SH 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define LPCR_HAIL ASM_CONST(0x0000000004000000) /* HV AIL (ISAv3.1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define LPCR_ILE ASM_CONST(0x0000000002000000) /* !HV irqs set MSR:LE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define LPCR_AIL ASM_CONST(0x0000000001800000) /* Alternate interrupt location */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define LPCR_AIL_0 ASM_CONST(0x0000000000000000) /* MMU off exception offset 0x0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define LPCR_AIL_3 ASM_CONST(0x0000000001800000) /* MMU on exception offset 0xc00...4xxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define LPCR_ONL ASM_CONST(0x0000000000040000) /* online - PURR/SPURR count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define LPCR_LD ASM_CONST(0x0000000000020000) /* large decremeter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define LPCR_PECE ASM_CONST(0x000000000001f000) /* powersave exit cause enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define LPCR_PECEDP ASM_CONST(0x0000000000010000) /* directed priv dbells cause exit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define LPCR_PECEDH ASM_CONST(0x0000000000008000) /* directed hyp dbells cause exit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define LPCR_PECE0 ASM_CONST(0x0000000000004000) /* ext. exceptions can cause exit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define LPCR_PECE1 ASM_CONST(0x0000000000002000) /* decrementer can cause exit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define LPCR_PECE2 ASM_CONST(0x0000000000001000) /* machine check etc can cause exit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define LPCR_PECE_HVEE ASM_CONST(0x0000400000000000) /* P9 Wakeup on HV interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define LPCR_MER ASM_CONST(0x0000000000000800) /* Mediated External Exception */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define LPCR_MER_SH 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define LPCR_GTSE ASM_CONST(0x0000000000000400) /* Guest Translation Shootdown Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define LPCR_TC ASM_CONST(0x0000000000000200) /* Translation control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define LPCR_HEIC ASM_CONST(0x0000000000000010) /* Hypervisor External Interrupt Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define LPCR_LPES 0x0000000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define LPCR_LPES0 ASM_CONST(0x0000000000000008) /* LPAR Env selector 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define LPCR_LPES1 ASM_CONST(0x0000000000000004) /* LPAR Env selector 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define LPCR_LPES_SH 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define LPCR_RMI ASM_CONST(0x0000000000000002) /* real mode is cache inhibit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define LPCR_HVICE ASM_CONST(0x0000000000000002) /* P9: HV interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define LPCR_HDICE ASM_CONST(0x0000000000000001) /* Hyp Decr enable (HV,PR,EE) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define LPCR_UPRT ASM_CONST(0x0000000000400000) /* Use Process Table (ISA 3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define LPCR_HR ASM_CONST(0x0000000000100000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #ifndef SPRN_LPID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define SPRN_LPID 0x13F /* Logical Partition Identifier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define LPID_RSVD_POWER7 0x3ff /* Reserved LPID for partn switching */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define LPID_RSVD 0xfff /* Reserved LPID for partn switching */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define SPRN_HMER 0x150 /* Hypervisor maintenance exception reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define HMER_DEBUG_TRIG (1ul << (63 - 17)) /* Debug trigger */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define SPRN_HMEER 0x151 /* Hyp maintenance exception enable reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define SPRN_PCR 0x152 /* Processor compatibility register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define PCR_VEC_DIS (__MASK(63-0)) /* Vec. disable (bit NA since POWER8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define PCR_VSX_DIS (__MASK(63-1)) /* VSX disable (bit NA since POWER8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define PCR_TM_DIS (__MASK(63-2)) /* Trans. memory disable (POWER8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define PCR_MMA_DIS (__MASK(63-3)) /* Matrix-Multiply Accelerator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define PCR_HIGH_BITS (PCR_MMA_DIS | PCR_VEC_DIS | PCR_VSX_DIS | PCR_TM_DIS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) * These bits are used in the function kvmppc_set_arch_compat() to specify and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) * determine both the compatibility level which we want to emulate and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) * compatibility level which the host is capable of emulating.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define PCR_ARCH_300 0x10 /* Architecture 3.00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define PCR_ARCH_207 0x8 /* Architecture 2.07 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define PCR_ARCH_206 0x4 /* Architecture 2.06 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define PCR_ARCH_205 0x2 /* Architecture 2.05 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define PCR_LOW_BITS (PCR_ARCH_207 | PCR_ARCH_206 | PCR_ARCH_205 | PCR_ARCH_300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define PCR_MASK ~(PCR_HIGH_BITS | PCR_LOW_BITS) /* PCR Reserved Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define SPRN_HEIR 0x153 /* Hypervisor Emulated Instruction Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define SPRN_TLBINDEXR 0x154 /* P7 TLB control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define SPRN_TLBVPNR 0x155 /* P7 TLB control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define SPRN_TLBRPNR 0x156 /* P7 TLB control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define SPRN_TLBLPIDR 0x157 /* P7 TLB control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define SPRN_DBAT0L 0x219 /* Data BAT 0 Lower Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define SPRN_DBAT0U 0x218 /* Data BAT 0 Upper Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define SPRN_DBAT1L 0x21B /* Data BAT 1 Lower Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define SPRN_DBAT1U 0x21A /* Data BAT 1 Upper Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define SPRN_DBAT2L 0x21D /* Data BAT 2 Lower Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define SPRN_DBAT2U 0x21C /* Data BAT 2 Upper Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define SPRN_DBAT3L 0x21F /* Data BAT 3 Lower Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define SPRN_DBAT3U 0x21E /* Data BAT 3 Upper Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define SPRN_DBAT4L 0x239 /* Data BAT 4 Lower Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define SPRN_DBAT4U 0x238 /* Data BAT 4 Upper Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define SPRN_DBAT5L 0x23B /* Data BAT 5 Lower Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define SPRN_DBAT5U 0x23A /* Data BAT 5 Upper Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define SPRN_DBAT6L 0x23D /* Data BAT 6 Lower Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define SPRN_DBAT6U 0x23C /* Data BAT 6 Upper Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define SPRN_DBAT7L 0x23F /* Data BAT 7 Lower Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define SPRN_DBAT7U 0x23E /* Data BAT 7 Upper Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define SPRN_PPR 0x380 /* SMT Thread status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define SPRN_TSCR 0x399 /* Thread Switch Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define SPRN_DEC 0x016 /* Decrement Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define SPRN_PIT 0x3DB /* Programmable Interval Timer (40x/BOOKE) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define SPRN_DER 0x095 /* Debug Enable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define DER_RSTE 0x40000000 /* Reset Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define DER_CHSTPE 0x20000000 /* Check Stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define DER_MCIE 0x10000000 /* Machine Check Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define DER_EXTIE 0x02000000 /* External Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define DER_ALIE 0x01000000 /* Alignment Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define DER_PRIE 0x00800000 /* Program Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define DER_FPUVIE 0x00400000 /* FP Unavailable Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define DER_DECIE 0x00200000 /* Decrementer Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define DER_SYSIE 0x00040000 /* System Call Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define DER_TRE 0x00020000 /* Trace Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define DER_SEIE 0x00004000 /* FP SW Emulation Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define DER_ITLBMSE 0x00002000 /* Imp. Spec. Instruction TLB Miss */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define DER_ITLBERE 0x00001000 /* Imp. Spec. Instruction TLB Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define DER_DTLBMSE 0x00000800 /* Imp. Spec. Data TLB Miss */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define DER_DTLBERE 0x00000400 /* Imp. Spec. Data TLB Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define DER_LBRKE 0x00000008 /* Load/Store Breakpoint Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define DER_IBRKE 0x00000004 /* Instruction Breakpoint Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define DER_EBRKE 0x00000002 /* External Breakpoint Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define DER_DPIE 0x00000001 /* Dev. Port Nonmaskable Request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define SPRN_DHDES 0x0B1 /* Directed Hyp. Doorbell Exc. State */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define SPRN_DPDES 0x0B0 /* Directed Priv. Doorbell Exc. State */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define SPRN_EAR 0x11A /* External Address Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define SPRN_HASH1 0x3D2 /* Primary Hash Address Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define SPRN_HASH2 0x3D3 /* Secondary Hash Address Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define SPRN_HID0 0x3F0 /* Hardware Implementation Register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define HID0_HDICE_SH (63 - 23) /* 970 HDEC interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define HID0_EMCP (1<<31) /* Enable Machine Check pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define HID0_EBA (1<<29) /* Enable Bus Address Parity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define HID0_EBD (1<<28) /* Enable Bus Data Parity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define HID0_SBCLK (1<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define HID0_EICE (1<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define HID0_TBEN (1<<26) /* Timebase enable - 745x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define HID0_ECLK (1<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define HID0_PAR (1<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define HID0_STEN (1<<24) /* Software table search enable - 745x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define HID0_HIGH_BAT (1<<23) /* Enable high BATs - 7455 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define HID0_DOZE (1<<23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define HID0_NAP (1<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define HID0_SLEEP (1<<21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define HID0_DPM (1<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define HID0_BHTCLR (1<<18) /* Clear branch history table - 7450 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define HID0_XAEN (1<<17) /* Extended addressing enable - 7450 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define HID0_NHR (1<<16) /* Not hard reset (software bit-7450)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #define HID0_ICE (1<<15) /* Instruction Cache Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define HID0_DCE (1<<14) /* Data Cache Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define HID0_ILOCK (1<<13) /* Instruction Cache Lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define HID0_DLOCK (1<<12) /* Data Cache Lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define HID0_ICFI (1<<11) /* Instr. Cache Flash Invalidate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define HID0_DCI (1<<10) /* Data Cache Invalidate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define HID0_SPD (1<<9) /* Speculative disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define HID0_DAPUEN (1<<8) /* Debug APU enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #define HID0_SGE (1<<7) /* Store Gathering Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define HID0_SIED (1<<7) /* Serial Instr. Execution [Disable] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define HID0_DCFA (1<<6) /* Data Cache Flush Assist */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define HID0_LRSTK (1<<4) /* Link register stack - 745x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define HID0_BTIC (1<<5) /* Branch Target Instr Cache Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #define HID0_ABE (1<<3) /* Address Broadcast Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define HID0_FOLD (1<<3) /* Branch Folding enable - 745x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #define HID0_BHTE (1<<2) /* Branch History Table Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define HID0_BTCD (1<<1) /* Branch target cache disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #define HID0_NOPDST (1<<1) /* No-op dst, dstt, etc. instr. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #define HID0_NOPTI (1<<0) /* No-op dcbt and dcbst instr. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) /* POWER8 HID0 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #define HID0_POWER8_4LPARMODE __MASK(61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #define HID0_POWER8_2LPARMODE __MASK(57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define HID0_POWER8_1TO2LPAR __MASK(52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #define HID0_POWER8_1TO4LPAR __MASK(51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define HID0_POWER8_DYNLPARDIS __MASK(48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) /* POWER9 HID0 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #define HID0_POWER9_RADIX __MASK(63 - 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #ifdef CONFIG_PPC_BOOK3S_32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #define HID1_EMCP (1<<31) /* 7450 Machine Check Pin Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #define HID1_DFS (1<<22) /* 7447A Dynamic Frequency Scaling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #define HID1_PC0 (1<<16) /* 7450 PLL_CFG[0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #define HID1_PC1 (1<<15) /* 7450 PLL_CFG[1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #define HID1_PC2 (1<<14) /* 7450 PLL_CFG[2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #define HID1_PC3 (1<<13) /* 7450 PLL_CFG[3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #define HID1_SYNCBE (1<<11) /* 7450 ABE for sync, eieio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #define HID1_ABE (1<<10) /* 7450 Address Broadcast Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #define HID1_PS (1<<16) /* 750FX PLL selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define SPRN_HID2 0x3F8 /* Hardware Implementation Register 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #define SPRN_HID2_GEKKO 0x398 /* Gekko HID2 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define SPRN_IABR2 0x3FA /* 83xx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define SPRN_IBCR 0x135 /* 83xx Insn Breakpoint Control Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define SPRN_IAMR 0x03D /* Instr. Authority Mask Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #define SPRN_HID4 0x3F4 /* 970 HID4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #define HID4_LPES0 (1ul << (63-0)) /* LPAR env. sel. bit 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) #define HID4_RMLS2_SH (63 - 2) /* Real mode limit bottom 2 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #define HID4_LPID5_SH (63 - 6) /* partition ID bottom 4 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) #define HID4_RMOR_SH (63 - 22) /* real mode offset (16 bits) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) #define HID4_RMOR (0xFFFFul << HID4_RMOR_SH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #define HID4_LPES1 (1 << (63-57)) /* LPAR env. sel. bit 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #define HID4_RMLS0_SH (63 - 58) /* Real mode limit top bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) #define HID4_LPID1_SH 0 /* partition ID top 2 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) #define SPRN_HID4_GEKKO 0x3F3 /* Gekko HID4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) #define SPRN_HID5 0x3F6 /* 970 HID5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) #define SPRN_HID6 0x3F9 /* BE HID 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #define HID6_LB (0x0F<<12) /* Concurrent Large Page Modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #define HID6_DLP (1<<20) /* Disable all large page modes (4K only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) #define SPRN_TSC_CELL 0x399 /* Thread switch control on Cell */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) #define TSC_CELL_DEC_ENABLE_0 0x400000 /* Decrementer Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #define TSC_CELL_DEC_ENABLE_1 0x200000 /* Decrementer Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) #define TSC_CELL_EE_ENABLE 0x100000 /* External Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) #define TSC_CELL_EE_BOOST 0x080000 /* External Interrupt Boost */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) #define SPRN_TSC 0x3FD /* Thread switch control on others */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) #define SPRN_TST 0x3FC /* Thread switch timeout on others */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) #if !defined(SPRN_IAC1) && !defined(SPRN_IAC2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) #define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) #define SPRN_IAC2 0x3F5 /* Instruction Address Compare 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) #define SPRN_IBAT0L 0x211 /* Instruction BAT 0 Lower Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) #define SPRN_IBAT0U 0x210 /* Instruction BAT 0 Upper Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) #define SPRN_IBAT1L 0x213 /* Instruction BAT 1 Lower Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) #define SPRN_IBAT1U 0x212 /* Instruction BAT 1 Upper Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) #define SPRN_IBAT2L 0x215 /* Instruction BAT 2 Lower Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) #define SPRN_IBAT2U 0x214 /* Instruction BAT 2 Upper Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) #define SPRN_IBAT3L 0x217 /* Instruction BAT 3 Lower Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) #define SPRN_IBAT3U 0x216 /* Instruction BAT 3 Upper Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) #define SPRN_IBAT4L 0x231 /* Instruction BAT 4 Lower Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) #define SPRN_IBAT4U 0x230 /* Instruction BAT 4 Upper Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) #define SPRN_IBAT5L 0x233 /* Instruction BAT 5 Lower Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) #define SPRN_IBAT5U 0x232 /* Instruction BAT 5 Upper Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) #define SPRN_IBAT6L 0x235 /* Instruction BAT 6 Lower Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) #define SPRN_IBAT6U 0x234 /* Instruction BAT 6 Upper Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) #define SPRN_IBAT7L 0x237 /* Instruction BAT 7 Lower Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) #define SPRN_IBAT7U 0x236 /* Instruction BAT 7 Upper Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) #define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) #define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) #ifndef SPRN_ICTRL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) #define SPRN_ICTRL 0x3F3 /* 1011 7450 icache and interrupt ctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) #define ICTRL_EICE 0x08000000 /* enable icache parity errs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) #define ICTRL_EDC 0x04000000 /* enable dcache parity errs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) #define ICTRL_EICP 0x00000100 /* enable icache par. check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) #define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) #define SPRN_IMMR 0x27E /* Internal Memory Map Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) #define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) #define SPRN_L2CR2 0x3f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) #define L2CR_L2E 0x80000000 /* L2 enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) #define L2CR_L2PE 0x40000000 /* L2 parity enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) #define L2CR_L2SIZ_MASK 0x30000000 /* L2 size mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) #define L2CR_L2SIZ_256KB 0x10000000 /* L2 size 256KB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) #define L2CR_L2SIZ_512KB 0x20000000 /* L2 size 512KB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) #define L2CR_L2SIZ_1MB 0x30000000 /* L2 size 1MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) #define L2CR_L2CLK_MASK 0x0e000000 /* L2 clock mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) #define L2CR_L2CLK_DISABLED 0x00000000 /* L2 clock disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) #define L2CR_L2CLK_DIV1 0x02000000 /* L2 clock / 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) #define L2CR_L2CLK_DIV1_5 0x04000000 /* L2 clock / 1.5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) #define L2CR_L2CLK_DIV2 0x08000000 /* L2 clock / 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) #define L2CR_L2CLK_DIV2_5 0x0a000000 /* L2 clock / 2.5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) #define L2CR_L2CLK_DIV3 0x0c000000 /* L2 clock / 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) #define L2CR_L2RAM_MASK 0x01800000 /* L2 RAM type mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) #define L2CR_L2RAM_FLOW 0x00000000 /* L2 RAM flow through */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) #define L2CR_L2RAM_PIPE 0x01000000 /* L2 RAM pipelined */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) #define L2CR_L2RAM_PIPE_LW 0x01800000 /* L2 RAM pipelined latewr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) #define L2CR_L2DO 0x00400000 /* L2 data only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) #define L2CR_L2I 0x00200000 /* L2 global invalidate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) #define L2CR_L2CTL 0x00100000 /* L2 RAM control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) #define L2CR_L2WT 0x00080000 /* L2 write-through */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) #define L2CR_L2TS 0x00040000 /* L2 test support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) #define L2CR_L2OH_MASK 0x00030000 /* L2 output hold mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) #define L2CR_L2OH_0_5 0x00000000 /* L2 output hold 0.5 ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) #define L2CR_L2OH_1_0 0x00010000 /* L2 output hold 1.0 ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) #define L2CR_L2SL 0x00008000 /* L2 DLL slow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) #define L2CR_L2DF 0x00004000 /* L2 differential clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) #define L2CR_L2BYP 0x00002000 /* L2 DLL bypass */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) #define L2CR_L2IP 0x00000001 /* L2 GI in progress */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) #define L2CR_L2IO_745x 0x00100000 /* L2 instr. only (745x) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) #define L2CR_L2DO_745x 0x00010000 /* L2 data only (745x) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) #define L2CR_L2REP_745x 0x00001000 /* L2 repl. algorithm (745x) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) #define L2CR_L2HWF_745x 0x00000800 /* L2 hardware flush (745x) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) #define SPRN_L3CR 0x3FA /* Level 3 Cache Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) #define L3CR_L3E 0x80000000 /* L3 enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) #define L3CR_L3PE 0x40000000 /* L3 data parity enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) #define L3CR_L3APE 0x20000000 /* L3 addr parity enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) #define L3CR_L3SIZ 0x10000000 /* L3 size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) #define L3CR_L3CLKEN 0x08000000 /* L3 clock enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) #define L3CR_L3RES 0x04000000 /* L3 special reserved bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) #define L3CR_L3CLKDIV 0x03800000 /* L3 clock divisor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) #define L3CR_L3IO 0x00400000 /* L3 instruction only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) #define L3CR_L3SPO 0x00040000 /* L3 sample point override */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) #define L3CR_L3CKSP 0x00030000 /* L3 clock sample point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) #define L3CR_L3PSP 0x0000e000 /* L3 P-clock sample point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) #define L3CR_L3REP 0x00001000 /* L3 replacement algorithm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) #define L3CR_L3HWF 0x00000800 /* L3 hardware flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) #define L3CR_L3I 0x00000400 /* L3 global invalidate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) #define L3CR_L3RT 0x00000300 /* L3 SRAM type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) #define L3CR_L3NIRCA 0x00000080 /* L3 non-integer ratio clock adj. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) #define L3CR_L3DO 0x00000040 /* L3 data only mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) #define L3CR_PMEN 0x00000004 /* L3 private memory enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) #define L3CR_PMSIZ 0x00000001 /* L3 private memory size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) #define SPRN_MSSCR0 0x3f6 /* Memory Subsystem Control Register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) #define SPRN_MSSSR0 0x3f7 /* Memory Subsystem Status Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) #define SPRN_LDSTCR 0x3f8 /* Load/Store control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) #define SPRN_LDSTDB 0x3f4 /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) #define SPRN_LR 0x008 /* Link Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) #ifndef SPRN_PIR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) #define SPRN_PIR 0x3FF /* Processor Identification Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) #define SPRN_TIR 0x1BE /* Thread Identification Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) #define SPRN_PTCR 0x1D0 /* Partition table control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) #define SPRN_PSPB 0x09F /* Problem State Priority Boost reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) #define SPRN_PTEHI 0x3D5 /* 981 7450 PTE HI word (S/W TLB load) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) #define SPRN_PTELO 0x3D6 /* 982 7450 PTE LO word (S/W TLB load) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) #define SPRN_PURR 0x135 /* Processor Utilization of Resources Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) #define SPRN_PVR 0x11F /* Processor Version Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) #define SPRN_RPA 0x3D6 /* Required Physical Address Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) #define SPRN_SDA 0x3BF /* Sampled Data Address Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) #define SPRN_SDR1 0x019 /* MMU Hash Base Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) #define SPRN_ASR 0x118 /* Address Space Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) #define SPRN_SIA 0x3BB /* Sampled Instruction Address Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) #define SPRN_SPRG0 0x110 /* Special Purpose Register General 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) #define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) #define SPRN_SPRG2 0x112 /* Special Purpose Register General 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) #define SPRN_SPRG3 0x113 /* Special Purpose Register General 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) #define SPRN_USPRG3 0x103 /* SPRG3 userspace read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) #define SPRN_SPRG4 0x114 /* Special Purpose Register General 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) #define SPRN_USPRG4 0x104 /* SPRG4 userspace read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) #define SPRN_SPRG5 0x115 /* Special Purpose Register General 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) #define SPRN_USPRG5 0x105 /* SPRG5 userspace read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) #define SPRN_SPRG6 0x116 /* Special Purpose Register General 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) #define SPRN_USPRG6 0x106 /* SPRG6 userspace read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) #define SPRN_SPRG7 0x117 /* Special Purpose Register General 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) #define SPRN_USPRG7 0x107 /* SPRG7 userspace read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) #define SPRN_SRR0 0x01A /* Save/Restore Register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) #define SPRN_SRR1 0x01B /* Save/Restore Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) #ifdef CONFIG_PPC_BOOK3S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) * Bits loaded from MSR upon interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) * PPC (64-bit) bits 33-36,42-47 are interrupt dependent, the others are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) * loaded from MSR. The exception is that SRESET and MCE do not always load
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) * bit 62 (RI) from MSR. Don't use PPC_BITMASK for this because 32-bit uses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) * it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) #define SRR1_MSR_BITS (~0x783f0000UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) #define SRR1_ISI_NOPT 0x40000000 /* ISI: Not found in hash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) #define SRR1_ISI_N_G_OR_CIP 0x10000000 /* ISI: Access is no-exec or G or CI for a prefixed instruction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) #define SRR1_ISI_PROT 0x08000000 /* ISI: Other protection fault */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) #define SRR1_WAKEMASK 0x00380000 /* reason for wakeup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) #define SRR1_WAKEMASK_P8 0x003c0000 /* reason for wakeup on POWER8 and 9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) #define SRR1_WAKEMCE_RESVD 0x003c0000 /* Unused/reserved value used by MCE wakeup to indicate cause to idle wakeup handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) #define SRR1_WAKESYSERR 0x00300000 /* System error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) #define SRR1_WAKEEE 0x00200000 /* External interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) #define SRR1_WAKEHVI 0x00240000 /* Hypervisor Virtualization Interrupt (P9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) #define SRR1_WAKEMT 0x00280000 /* mtctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) #define SRR1_WAKEHMI 0x00280000 /* Hypervisor maintenance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) #define SRR1_WAKEDEC 0x00180000 /* Decrementer interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) #define SRR1_WAKEDBELL 0x00140000 /* Privileged doorbell on P8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) #define SRR1_WAKETHERM 0x00100000 /* Thermal management interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) #define SRR1_WAKERESET 0x00100000 /* System reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) #define SRR1_WAKEHDBELL 0x000c0000 /* Hypervisor doorbell on P8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) #define SRR1_WAKESTATE 0x00030000 /* Powersave exit mask [46:47] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) #define SRR1_WS_HVLOSS 0x00030000 /* HV resources not maintained */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) #define SRR1_WS_GPRLOSS 0x00020000 /* GPRs not maintained */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) #define SRR1_WS_NOLOSS 0x00010000 /* All resources maintained */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) #define SRR1_PROGTM 0x00200000 /* TM Bad Thing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) #define SRR1_PROGFPE 0x00100000 /* Floating Point Enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) #define SRR1_PROGILL 0x00080000 /* Illegal instruction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) #define SRR1_PROGPRIV 0x00040000 /* Privileged instruction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) #define SRR1_PROGTRAP 0x00020000 /* Trap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) #define SRR1_PROGADDR 0x00010000 /* SRR0 contains subsequent addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) #define SRR1_MCE_MCP 0x00080000 /* Machine check signal caused interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) #define SRR1_BOUNDARY 0x10000000 /* Prefixed instruction crosses 64-byte boundary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) #define SRR1_PREFIXED 0x20000000 /* Exception caused by prefixed instruction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) #define SPRN_HSRR0 0x13A /* Save/Restore Register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) #define SPRN_HSRR1 0x13B /* Save/Restore Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) #define HSRR1_DENORM 0x00100000 /* Denorm exception */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) #define HSRR1_HISI_WRITE 0x00010000 /* HISI bcs couldn't update mem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) #define SPRN_TBCTL 0x35f /* PA6T Timebase control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) #define TBCTL_FREEZE 0x0000000000000000ull /* Freeze all tbs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) #define TBCTL_RESTART 0x0000000100000000ull /* Restart all tbs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) #define TBCTL_UPDATE_UPPER 0x0000000200000000ull /* Set upper 32 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) #define TBCTL_UPDATE_LOWER 0x0000000300000000ull /* Set lower 32 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) #ifndef SPRN_SVR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) #define SPRN_SVR 0x11E /* System Version Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) #define SPRN_THRM1 0x3FC /* Thermal Management Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) /* these bits were defined in inverted endian sense originally, ugh, confusing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) #define THRM1_TIN (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) #define THRM1_TIV (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) #define THRM1_THRES(x) ((x&0x7f)<<23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) #define THRM3_SITV(x) ((x & 0x1fff) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) #define THRM1_TID (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) #define THRM1_TIE (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) #define THRM1_V (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) #define SPRN_THRM2 0x3FD /* Thermal Management Register 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) #define SPRN_THRM3 0x3FE /* Thermal Management Register 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) #define THRM3_E (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) #define SPRN_TLBMISS 0x3D4 /* 980 7450 TLB Miss Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) #define SPRN_UMMCR0 0x3A8 /* User Monitor Mode Control Register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) #define SPRN_UMMCR1 0x3AC /* User Monitor Mode Control Register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) #define SPRN_UPMC1 0x3A9 /* User Performance Counter Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) #define SPRN_UPMC2 0x3AA /* User Performance Counter Register 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) #define SPRN_UPMC3 0x3AD /* User Performance Counter Register 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) #define SPRN_UPMC4 0x3AE /* User Performance Counter Register 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) #define SPRN_USIA 0x3AB /* User Sampled Instruction Address Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) #define SPRN_VRSAVE 0x100 /* Vector Register Save Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) #define SPRN_XER 0x001 /* Fixed Point Exception Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) #define SPRN_MMCR0_GEKKO 0x3B8 /* Gekko Monitor Mode Control Register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) #define SPRN_MMCR1_GEKKO 0x3BC /* Gekko Monitor Mode Control Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) #define SPRN_PMC1_GEKKO 0x3B9 /* Gekko Performance Monitor Control 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) #define SPRN_PMC2_GEKKO 0x3BA /* Gekko Performance Monitor Control 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) #define SPRN_PMC3_GEKKO 0x3BD /* Gekko Performance Monitor Control 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) #define SPRN_PMC4_GEKKO 0x3BE /* Gekko Performance Monitor Control 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) #define SPRN_WPAR_GEKKO 0x399 /* Gekko Write Pipe Address Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) #define SPRN_SCOMC 0x114 /* SCOM Access Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) #define SPRN_SCOMD 0x115 /* SCOM Access DATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) /* Performance monitor SPRs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) #ifdef CONFIG_PPC64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) #define SPRN_MMCR0 795
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) #define MMCR0_FC 0x80000000UL /* freeze counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) #define MMCR0_FCS 0x40000000UL /* freeze in supervisor state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) #define MMCR0_KERNEL_DISABLE MMCR0_FCS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) #define MMCR0_FCP 0x20000000UL /* freeze in problem state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) #define MMCR0_PROBLEM_DISABLE MMCR0_FCP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) #define MMCR0_FCM1 0x10000000UL /* freeze counters while MSR mark = 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) #define MMCR0_FCM0 0x08000000UL /* freeze counters while MSR mark = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) #define MMCR0_PMXE ASM_CONST(0x04000000) /* perf mon exception enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) #define MMCR0_FCECE ASM_CONST(0x02000000) /* freeze ctrs on enabled cond or event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) #define MMCR0_TBEE 0x00400000UL /* time base exception enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) #define MMCR0_BHRBA 0x00200000UL /* BHRB Access allowed in userspace */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) #define MMCR0_EBE 0x00100000UL /* Event based branch enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) #define MMCR0_PMCC 0x000c0000UL /* PMC control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) #define MMCR0_PMCCEXT ASM_CONST(0x00000200) /* PMCCEXT control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) #define MMCR0_PMCC_U6 0x00080000UL /* PMC1-6 are R/W by user (PR) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) #define MMCR0_PMC1CE 0x00008000UL /* PMC1 count enable*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) #define MMCR0_PMCjCE ASM_CONST(0x00004000) /* PMCj count enable*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) #define MMCR0_TRIGGER 0x00002000UL /* TRIGGER enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) #define MMCR0_PMAO_SYNC ASM_CONST(0x00000800) /* PMU intr is synchronous */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) #define MMCR0_C56RUN ASM_CONST(0x00000100) /* PMC5/6 count when RUN=0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) /* performance monitor alert has occurred, set to 0 after handling exception */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) #define MMCR0_PMAO ASM_CONST(0x00000080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) #define MMCR0_SHRFC 0x00000040UL /* SHRre freeze conditions between threads */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) #define MMCR0_FC56 0x00000010UL /* freeze counters 5 and 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) #define MMCR0_FCTI 0x00000008UL /* freeze counters in tags inactive mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) #define MMCR0_FCTA 0x00000004UL /* freeze counters in tags active mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) #define MMCR0_FCWAIT 0x00000002UL /* freeze counter in WAIT state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) #define MMCR0_FCHV 0x00000001UL /* freeze conditions in hypervisor mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) #define SPRN_MMCR1 798
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) #define SPRN_MMCR2 785
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) #define SPRN_MMCR3 754
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) #define SPRN_UMMCR2 769
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) #define SPRN_UMMCR3 738
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) #define SPRN_MMCRA 0x312
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) #define MMCRA_SDSYNC 0x80000000UL /* SDAR synced with SIAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) #define MMCRA_SDAR_DCACHE_MISS 0x40000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) #define MMCRA_SDAR_ERAT_MISS 0x20000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) #define MMCRA_SIHV 0x10000000UL /* state of MSR HV when SIAR set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) #define MMCRA_SIPR 0x08000000UL /* state of MSR PR when SIAR set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) #define MMCRA_SLOT 0x07000000UL /* SLOT bits (37-39) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) #define MMCRA_SLOT_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) #define MMCRA_SAMPLE_ENABLE 0x00000001UL /* enable sampling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) #define MMCRA_BHRB_DISABLE _UL(0x2000000000) // BHRB disable bit for ISA v3.1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) #define POWER6_MMCRA_SDSYNC 0x0000080000000000ULL /* SDAR/SIAR synced */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) #define POWER6_MMCRA_SIHV 0x0000040000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) #define POWER6_MMCRA_SIPR 0x0000020000000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) #define POWER6_MMCRA_THRM 0x00000020UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) #define POWER6_MMCRA_OTHER 0x0000000EUL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) #define POWER7P_MMCRA_SIAR_VALID 0x10000000 /* P7+ SIAR contents valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) #define POWER7P_MMCRA_SDAR_VALID 0x08000000 /* P7+ SDAR contents valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) #define SPRN_MMCRH 316 /* Hypervisor monitor mode control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) #define SPRN_MMCRS 894 /* Supervisor monitor mode control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) #define SPRN_MMCRC 851 /* Core monitor mode control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) #define SPRN_EBBHR 804 /* Event based branch handler register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) #define SPRN_EBBRR 805 /* Event based branch return register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) #define SPRN_BESCR 806 /* Branch event status and control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) #define BESCR_GE 0x8000000000000000ULL /* Global Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) #define SPRN_WORT 895 /* Workload optimization register - thread */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) #define SPRN_WORC 863 /* Workload optimization register - core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) #define SPRN_PMC1 787
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) #define SPRN_PMC2 788
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) #define SPRN_PMC3 789
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) #define SPRN_PMC4 790
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) #define SPRN_PMC5 791
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) #define SPRN_PMC6 792
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) #define SPRN_PMC7 793
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) #define SPRN_PMC8 794
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) #define SPRN_SIER 784
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) #define SIER_SIPR 0x2000000 /* Sampled MSR_PR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) #define SIER_SIHV 0x1000000 /* Sampled MSR_HV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) #define SIER_SIAR_VALID 0x0400000 /* SIAR contents valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) #define SIER_SDAR_VALID 0x0200000 /* SDAR contents valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) #define SPRN_SIER2 752
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) #define SPRN_SIER3 753
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) #define SPRN_USIER2 736
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) #define SPRN_USIER3 737
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) #define SPRN_SIAR 796
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) #define SPRN_SDAR 797
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) #define SPRN_TACR 888
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) #define SPRN_TCSCR 889
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) #define SPRN_CSIGR 890
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) #define SPRN_SPMC1 892
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) #define SPRN_SPMC2 893
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) /* When EBB is enabled, some of MMCR0/MMCR2/SIER are user accessible */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) #define MMCR0_USER_MASK (MMCR0_FC | MMCR0_PMXE | MMCR0_PMAO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) #define MMCR2_USER_MASK 0x4020100804020000UL /* (FC1P|FC2P|FC3P|FC4P|FC5P|FC6P) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) #define SIER_USER_MASK 0x7fffffUL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) #define SPRN_PA6T_MMCR0 795
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) #define PA6T_MMCR0_EN0 0x0000000000000001UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) #define PA6T_MMCR0_EN1 0x0000000000000002UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) #define PA6T_MMCR0_EN2 0x0000000000000004UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) #define PA6T_MMCR0_EN3 0x0000000000000008UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) #define PA6T_MMCR0_EN4 0x0000000000000010UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) #define PA6T_MMCR0_EN5 0x0000000000000020UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) #define PA6T_MMCR0_SUPEN 0x0000000000000040UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) #define PA6T_MMCR0_PREN 0x0000000000000080UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) #define PA6T_MMCR0_HYPEN 0x0000000000000100UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) #define PA6T_MMCR0_FCM0 0x0000000000000200UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) #define PA6T_MMCR0_FCM1 0x0000000000000400UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) #define PA6T_MMCR0_INTGEN 0x0000000000000800UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) #define PA6T_MMCR0_INTEN0 0x0000000000001000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) #define PA6T_MMCR0_INTEN1 0x0000000000002000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) #define PA6T_MMCR0_INTEN2 0x0000000000004000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) #define PA6T_MMCR0_INTEN3 0x0000000000008000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) #define PA6T_MMCR0_INTEN4 0x0000000000010000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) #define PA6T_MMCR0_INTEN5 0x0000000000020000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) #define PA6T_MMCR0_DISCNT 0x0000000000040000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) #define PA6T_MMCR0_UOP 0x0000000000080000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) #define PA6T_MMCR0_TRG 0x0000000000100000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) #define PA6T_MMCR0_TRGEN 0x0000000000200000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) #define PA6T_MMCR0_TRGREG 0x0000000001600000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) #define PA6T_MMCR0_SIARLOG 0x0000000002000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) #define PA6T_MMCR0_SDARLOG 0x0000000004000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) #define PA6T_MMCR0_PROEN 0x0000000008000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) #define PA6T_MMCR0_PROLOG 0x0000000010000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) #define PA6T_MMCR0_DAMEN2 0x0000000020000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) #define PA6T_MMCR0_DAMEN3 0x0000000040000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) #define PA6T_MMCR0_DAMEN4 0x0000000080000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) #define PA6T_MMCR0_DAMEN5 0x0000000100000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) #define PA6T_MMCR0_DAMSEL2 0x0000000200000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) #define PA6T_MMCR0_DAMSEL3 0x0000000400000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) #define PA6T_MMCR0_DAMSEL4 0x0000000800000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) #define PA6T_MMCR0_DAMSEL5 0x0000001000000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) #define PA6T_MMCR0_HANDDIS 0x0000002000000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) #define PA6T_MMCR0_PCTEN 0x0000004000000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) #define PA6T_MMCR0_SOCEN 0x0000008000000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) #define PA6T_MMCR0_SOCMOD 0x0000010000000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) #define SPRN_PA6T_MMCR1 798
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) #define PA6T_MMCR1_ES2 0x00000000000000ffUL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) #define PA6T_MMCR1_ES3 0x000000000000ff00UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) #define PA6T_MMCR1_ES4 0x0000000000ff0000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) #define PA6T_MMCR1_ES5 0x00000000ff000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) #define SPRN_PA6T_UPMC0 771 /* User PerfMon Counter 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) #define SPRN_PA6T_UPMC1 772 /* ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) #define SPRN_PA6T_UPMC2 773
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) #define SPRN_PA6T_UPMC3 774
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) #define SPRN_PA6T_UPMC4 775
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) #define SPRN_PA6T_UPMC5 776
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) #define SPRN_PA6T_UMMCR0 779 /* User Monitor Mode Control Register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) #define SPRN_PA6T_SIAR 780 /* Sampled Instruction Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) #define SPRN_PA6T_UMMCR1 782 /* User Monitor Mode Control Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) #define SPRN_PA6T_SIER 785 /* Sampled Instruction Event Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) #define SPRN_PA6T_PMC0 787
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) #define SPRN_PA6T_PMC1 788
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) #define SPRN_PA6T_PMC2 789
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) #define SPRN_PA6T_PMC3 790
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) #define SPRN_PA6T_PMC4 791
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) #define SPRN_PA6T_PMC5 792
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) #define SPRN_PA6T_TSR0 793 /* Timestamp Register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) #define SPRN_PA6T_TSR1 794 /* Timestamp Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) #define SPRN_PA6T_TSR2 799 /* Timestamp Register 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) #define SPRN_PA6T_TSR3 784 /* Timestamp Register 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) #define SPRN_PA6T_IER 981 /* Icache Error Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) #define SPRN_PA6T_DER 982 /* Dcache Error Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) #define SPRN_PA6T_BER 862 /* BIU Error Address Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) #define SPRN_PA6T_MER 849 /* MMU Error Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) #define SPRN_PA6T_IMA0 880 /* Instruction Match Array 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) #define SPRN_PA6T_IMA1 881 /* ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) #define SPRN_PA6T_IMA2 882
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) #define SPRN_PA6T_IMA3 883
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) #define SPRN_PA6T_IMA4 884
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) #define SPRN_PA6T_IMA5 885
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) #define SPRN_PA6T_IMA6 886
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) #define SPRN_PA6T_IMA7 887
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) #define SPRN_PA6T_IMA8 888
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) #define SPRN_PA6T_IMA9 889
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) #define SPRN_PA6T_BTCR 978 /* Breakpoint and Tagging Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) #define SPRN_PA6T_IMAAT 979 /* Instruction Match Array Action Table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) #define SPRN_PA6T_PCCR 1019 /* Power Counter Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) #define SPRN_BKMK 1020 /* Cell Bookmark Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) #define SPRN_PA6T_RPCCR 1021 /* Retire PC Trace Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) #else /* 32-bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) #define SPRN_MMCR0 952 /* Monitor Mode Control Register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) #define MMCR0_FC 0x80000000UL /* freeze counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) #define MMCR0_FCS 0x40000000UL /* freeze in supervisor state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) #define MMCR0_FCP 0x20000000UL /* freeze in problem state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) #define MMCR0_FCM1 0x10000000UL /* freeze counters while MSR mark = 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) #define MMCR0_FCM0 0x08000000UL /* freeze counters while MSR mark = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) #define MMCR0_PMXE 0x04000000UL /* performance monitor exception enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) #define MMCR0_FCECE 0x02000000UL /* freeze ctrs on enabled cond or event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) #define MMCR0_TBEE 0x00400000UL /* time base exception enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) #define MMCR0_PMC1CE 0x00008000UL /* PMC1 count enable*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) #define MMCR0_PMCnCE 0x00004000UL /* count enable for all but PMC 1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) #define MMCR0_TRIGGER 0x00002000UL /* TRIGGER enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) #define MMCR0_PMC1SEL 0x00001fc0UL /* PMC 1 Event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) #define MMCR0_PMC2SEL 0x0000003fUL /* PMC 2 Event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) #define SPRN_MMCR1 956
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) #define MMCR1_PMC3SEL 0xf8000000UL /* PMC 3 Event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) #define MMCR1_PMC4SEL 0x07c00000UL /* PMC 4 Event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) #define MMCR1_PMC5SEL 0x003e0000UL /* PMC 5 Event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) #define MMCR1_PMC6SEL 0x0001f800UL /* PMC 6 Event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) #define SPRN_MMCR2 944
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) #define SPRN_PMC1 953 /* Performance Counter Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) #define SPRN_PMC2 954 /* Performance Counter Register 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) #define SPRN_PMC3 957 /* Performance Counter Register 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) #define SPRN_PMC4 958 /* Performance Counter Register 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) #define SPRN_PMC5 945 /* Performance Counter Register 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) #define SPRN_PMC6 946 /* Performance Counter Register 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) #define SPRN_SIAR 955 /* Sampled Instruction Address Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) /* Bit definitions for MMCR0 and PMC1 / PMC2. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) #define MMCR0_PMC1_CYCLES (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) #define MMCR0_PMC1_ICACHEMISS (5 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) #define MMCR0_PMC1_DTLB (6 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) #define MMCR0_PMC2_DCACHEMISS 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) #define MMCR0_PMC2_CYCLES 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) #define MMCR0_PMC2_ITLB 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) #define MMCR0_PMC2_LOADMISSTIME 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) * SPRG usage:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) * All 64-bit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) * - SPRG1 stores PACA pointer except 64-bit server in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) * HV mode in which case it is HSPRG0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) * 64-bit server:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) * - SPRG0 scratch for TM recheckpoint/reclaim (reserved for HV on Power4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) * - SPRG2 scratch for exception vectors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) * - SPRG3 CPU and NUMA node for VDSO getcpu (user visible)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) * - HSPRG0 stores PACA in HV mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) * - HSPRG1 scratch for "HV" exceptions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) * 64-bit embedded
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) * - SPRG0 generic exception scratch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) * - SPRG2 TLB exception stack
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) * - SPRG3 critical exception scratch (user visible, sorry!)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) * - SPRG4 unused (user visible)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) * - SPRG6 TLB miss scratch (user visible, sorry !)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) * - SPRG7 CPU and NUMA node for VDSO getcpu (user visible)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) * - SPRG8 machine check exception scratch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) * - SPRG9 debug exception scratch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) * All 32-bit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) * - SPRG3 current thread_struct physical addr pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) * (virtual on BookE, physical on others)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) * 32-bit classic:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) * - SPRG0 scratch for exception vectors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) * - SPRG1 scratch for exception vectors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) * - SPRG2 indicator that we are in RTAS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) * - SPRG4 (603 only) pseudo TLB LRU data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) * 32-bit 40x:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) * - SPRG0 scratch for exception vectors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) * - SPRG1 scratch for exception vectors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) * - SPRG2 scratch for exception vectors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) * - SPRG4 scratch for exception vectors (not 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) * - SPRG5 scratch for exception vectors (not 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) * - SPRG6 scratch for exception vectors (not 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) * - SPRG7 scratch for exception vectors (not 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) * 32-bit 440 and FSL BookE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) * - SPRG0 scratch for exception vectors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) * - SPRG1 scratch for exception vectors (*)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) * - SPRG2 scratch for crit interrupts handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) * - SPRG4 scratch for exception vectors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) * - SPRG5 scratch for exception vectors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) * - SPRG6 scratch for machine check handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) * - SPRG7 scratch for exception vectors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) * - SPRG9 scratch for debug vectors (e500 only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) * Additionally, BookE separates "read" and "write"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) * of those registers. That allows to use the userspace
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) * readable variant for reads, which can avoid a fault
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) * with KVM type virtualization.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) * 32-bit 8xx:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) * - SPRG0 scratch for exception vectors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) * - SPRG1 scratch for exception vectors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) * - SPRG2 scratch for exception vectors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) #ifdef CONFIG_PPC64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) #define SPRN_SPRG_PACA SPRN_SPRG1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) #define SPRN_SPRG_THREAD SPRN_SPRG3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) #ifdef CONFIG_PPC_BOOK3S_64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) #define SPRN_SPRG_SCRATCH0 SPRN_SPRG2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) #define SPRN_SPRG_HPACA SPRN_HSPRG0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) #define SPRN_SPRG_HSCRATCH0 SPRN_HSPRG1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) #define SPRN_SPRG_VDSO_READ SPRN_USPRG3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) #define SPRN_SPRG_VDSO_WRITE SPRN_SPRG3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) #define GET_PACA(rX) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) BEGIN_FTR_SECTION_NESTED(66); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) mfspr rX,SPRN_SPRG_PACA; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) FTR_SECTION_ELSE_NESTED(66); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) mfspr rX,SPRN_SPRG_HPACA; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) #define SET_PACA(rX) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) BEGIN_FTR_SECTION_NESTED(66); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) mtspr SPRN_SPRG_PACA,rX; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) FTR_SECTION_ELSE_NESTED(66); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) mtspr SPRN_SPRG_HPACA,rX; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) #define GET_SCRATCH0(rX) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) BEGIN_FTR_SECTION_NESTED(66); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) mfspr rX,SPRN_SPRG_SCRATCH0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) FTR_SECTION_ELSE_NESTED(66); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) mfspr rX,SPRN_SPRG_HSCRATCH0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) #define SET_SCRATCH0(rX) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) BEGIN_FTR_SECTION_NESTED(66); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) mtspr SPRN_SPRG_SCRATCH0,rX; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) FTR_SECTION_ELSE_NESTED(66); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) mtspr SPRN_SPRG_HSCRATCH0,rX; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) #else /* CONFIG_PPC_BOOK3S_64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) #define GET_SCRATCH0(rX) mfspr rX,SPRN_SPRG_SCRATCH0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) #define SET_SCRATCH0(rX) mtspr SPRN_SPRG_SCRATCH0,rX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) #ifdef CONFIG_PPC_BOOK3E_64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) #define SPRN_SPRG_MC_SCRATCH SPRN_SPRG8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) #define SPRN_SPRG_CRIT_SCRATCH SPRN_SPRG3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) #define SPRN_SPRG_DBG_SCRATCH SPRN_SPRG9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) #define SPRN_SPRG_TLB_EXFRAME SPRN_SPRG2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) #define SPRN_SPRG_TLB_SCRATCH SPRN_SPRG6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) #define SPRN_SPRG_GEN_SCRATCH SPRN_SPRG0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) #define SPRN_SPRG_GDBELL_SCRATCH SPRN_SPRG_GEN_SCRATCH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) #define SPRN_SPRG_VDSO_READ SPRN_USPRG7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) #define SPRN_SPRG_VDSO_WRITE SPRN_SPRG7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) #define SET_PACA(rX) mtspr SPRN_SPRG_PACA,rX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) #define GET_PACA(rX) mfspr rX,SPRN_SPRG_PACA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) #ifdef CONFIG_PPC_BOOK3S_32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) #define SPRN_SPRG_SCRATCH0 SPRN_SPRG0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) #define SPRN_SPRG_SCRATCH1 SPRN_SPRG1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) #define SPRN_SPRG_PGDIR SPRN_SPRG2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) #define SPRN_SPRG_603_LRU SPRN_SPRG4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) #ifdef CONFIG_40x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) #define SPRN_SPRG_SCRATCH0 SPRN_SPRG0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) #define SPRN_SPRG_SCRATCH1 SPRN_SPRG1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) #define SPRN_SPRG_SCRATCH2 SPRN_SPRG2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) #define SPRN_SPRG_SCRATCH3 SPRN_SPRG4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) #define SPRN_SPRG_SCRATCH4 SPRN_SPRG5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) #define SPRN_SPRG_SCRATCH5 SPRN_SPRG6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) #define SPRN_SPRG_SCRATCH6 SPRN_SPRG7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) #ifdef CONFIG_BOOKE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) #define SPRN_SPRG_RSCRATCH0 SPRN_SPRG0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) #define SPRN_SPRG_WSCRATCH0 SPRN_SPRG0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) #define SPRN_SPRG_RSCRATCH1 SPRN_SPRG1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) #define SPRN_SPRG_WSCRATCH1 SPRN_SPRG1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) #define SPRN_SPRG_RSCRATCH_CRIT SPRN_SPRG2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) #define SPRN_SPRG_WSCRATCH_CRIT SPRN_SPRG2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) #define SPRN_SPRG_RSCRATCH2 SPRN_SPRG4R
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) #define SPRN_SPRG_WSCRATCH2 SPRN_SPRG4W
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) #define SPRN_SPRG_RSCRATCH3 SPRN_SPRG5R
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) #define SPRN_SPRG_WSCRATCH3 SPRN_SPRG5W
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) #define SPRN_SPRG_RSCRATCH_MC SPRN_SPRG1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) #define SPRN_SPRG_WSCRATCH_MC SPRN_SPRG1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) #define SPRN_SPRG_RSCRATCH4 SPRN_SPRG7R
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) #define SPRN_SPRG_WSCRATCH4 SPRN_SPRG7W
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) #ifdef CONFIG_E200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) #define SPRN_SPRG_RSCRATCH_DBG SPRN_SPRG6R
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) #define SPRN_SPRG_WSCRATCH_DBG SPRN_SPRG6W
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) #define SPRN_SPRG_RSCRATCH_DBG SPRN_SPRG9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) #define SPRN_SPRG_WSCRATCH_DBG SPRN_SPRG9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) #ifdef CONFIG_PPC_8xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) #define SPRN_SPRG_SCRATCH0 SPRN_SPRG0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) #define SPRN_SPRG_SCRATCH1 SPRN_SPRG1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) #define SPRN_SPRG_SCRATCH2 SPRN_SPRG2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) * An mtfsf instruction with the L bit set. On CPUs that support this a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) * full 64bits of FPSCR is restored and on other CPUs the L bit is ignored.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) * Until binutils gets the new form of mtfsf, hardwire the instruction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) #ifdef CONFIG_PPC64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) #define MTFSF_L(REG) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) .long (0xfc00058e | ((0xff) << 17) | ((REG) << 11) | (1 << 25))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) #define MTFSF_L(REG) mtfsf 0xff, (REG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) /* Processor Version Register (PVR) field extraction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) #define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) #define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF) /* Revison field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) #define pvr_version_is(pvr) (PVR_VER(mfspr(SPRN_PVR)) == (pvr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) * IBM has further subdivided the standard PowerPC 16-bit version and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) * revision subfields of the PVR for the PowerPC 403s into the following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) #define PVR_FAM(pvr) (((pvr) >> 20) & 0xFFF) /* Family field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) #define PVR_MEM(pvr) (((pvr) >> 16) & 0xF) /* Member field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) #define PVR_CORE(pvr) (((pvr) >> 12) & 0xF) /* Core field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) #define PVR_CFG(pvr) (((pvr) >> 8) & 0xF) /* Configuration field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) #define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF) /* Major revision field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) #define PVR_MIN(pvr) (((pvr) >> 0) & 0xF) /* Minor revision field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) /* Processor Version Numbers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) #define PVR_403GA 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) #define PVR_403GB 0x00200100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) #define PVR_403GC 0x00200200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) #define PVR_403GCX 0x00201400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) #define PVR_405GP 0x40110000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) #define PVR_476 0x11a52000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) #define PVR_476FPE 0x7ff50000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) #define PVR_STB03XXX 0x40310000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) #define PVR_NP405H 0x41410000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) #define PVR_NP405L 0x41610000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) #define PVR_601 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) #define PVR_602 0x00050000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) #define PVR_603 0x00030000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) #define PVR_603e 0x00060000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) #define PVR_603ev 0x00070000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) #define PVR_603r 0x00071000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) #define PVR_604 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) #define PVR_604e 0x00090000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) #define PVR_604r 0x000A0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) #define PVR_620 0x00140000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) #define PVR_740 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) #define PVR_750 PVR_740
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) #define PVR_740P 0x10080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) #define PVR_750P PVR_740P
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) #define PVR_7400 0x000C0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) #define PVR_7410 0x800C0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) #define PVR_7450 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) #define PVR_8540 0x80200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) #define PVR_8560 0x80200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) #define PVR_VER_E500V1 0x8020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) #define PVR_VER_E500V2 0x8021
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) #define PVR_VER_E500MC 0x8023
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) #define PVR_VER_E5500 0x8024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) #define PVR_VER_E6500 0x8040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) * For the 8xx processors, all of them report the same PVR family for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) * the PowerPC core. The various versions of these processors must be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) * differentiated by the version number in the Communication Processor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) * Module (CPM).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) #define PVR_8xx 0x00500000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) #define PVR_8240 0x00810100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) #define PVR_8245 0x80811014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) #define PVR_8260 PVR_8240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) /* 476 Simulator seems to currently have the PVR of the 602... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) #define PVR_476_ISS 0x00052000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) /* 64-bit processors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) #define PVR_NORTHSTAR 0x0033
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) #define PVR_PULSAR 0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) #define PVR_POWER4 0x0035
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) #define PVR_ICESTAR 0x0036
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) #define PVR_SSTAR 0x0037
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) #define PVR_POWER4p 0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) #define PVR_970 0x0039
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) #define PVR_POWER5 0x003A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) #define PVR_POWER5p 0x003B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) #define PVR_970FX 0x003C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) #define PVR_POWER6 0x003E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) #define PVR_POWER7 0x003F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) #define PVR_630 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) #define PVR_630p 0x0041
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) #define PVR_970MP 0x0044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) #define PVR_970GX 0x0045
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) #define PVR_POWER7p 0x004A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) #define PVR_POWER8E 0x004B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) #define PVR_POWER8NVL 0x004C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) #define PVR_POWER8 0x004D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) #define PVR_POWER9 0x004E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) #define PVR_POWER10 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) #define PVR_BE 0x0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) #define PVR_PA6T 0x0090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) /* "Logical" PVR values defined in PAPR, representing architecture levels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) #define PVR_ARCH_204 0x0f000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) #define PVR_ARCH_205 0x0f000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) #define PVR_ARCH_206 0x0f000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) #define PVR_ARCH_206p 0x0f100003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) #define PVR_ARCH_207 0x0f000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) #define PVR_ARCH_300 0x0f000005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) #define PVR_ARCH_31 0x0f000006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) /* Macros for setting and retrieving special purpose registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) #ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) #define mfmsr() ({unsigned long rval; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) asm volatile("mfmsr %0" : "=r" (rval) : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) : "memory"); rval;})
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) #ifdef CONFIG_PPC_BOOK3S_64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) #define __mtmsrd(v, l) asm volatile("mtmsrd %0," __stringify(l) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) : : "r" (v) : "memory")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) #define mtmsr(v) __mtmsrd((v), 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) #define __MTMSR "mtmsrd"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) #define mtmsr(v) asm volatile("mtmsr %0" : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) : "r" ((unsigned long)(v)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) : "memory")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) #define __MTMSR "mtmsr"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) static inline void mtmsr_isync(unsigned long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) asm volatile(__MTMSR " %0; " ASM_FTR_IFCLR("isync", "nop", %1) : :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) "r" (val), "i" (CPU_FTR_ARCH_206) : "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) #define mfspr(rn) ({unsigned long rval; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) asm volatile("mfspr %0," __stringify(rn) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) : "=r" (rval)); rval;})
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) #ifndef mtspr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) #define mtspr(rn, v) asm volatile("mtspr " __stringify(rn) ",%0" : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) : "r" ((unsigned long)(v)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) : "memory")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) #define wrtspr(rn) asm volatile("mtspr " __stringify(rn) ",0" : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) : : "memory")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) static inline void wrtee(unsigned long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) if (__builtin_constant_p(val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) asm volatile("wrteei %0" : : "i" ((val & MSR_EE) ? 1 : 0) : "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) asm volatile("wrtee %0" : : "r" (val) : "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) extern unsigned long msr_check_and_set(unsigned long bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) extern bool strict_msr_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) extern void __msr_check_and_clear(unsigned long bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) static inline void msr_check_and_clear(unsigned long bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) if (strict_msr_control)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) __msr_check_and_clear(bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) #if defined(CONFIG_PPC_CELL) || defined(CONFIG_E500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) #define mftb() ({unsigned long rval; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) asm volatile( \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) "90: mfspr %0, %2;\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) ASM_FTR_IFSET( \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) "97: cmpwi %0,0;\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) " beq- 90b;\n", "", %1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) : "=r" (rval) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) : "i" (CPU_FTR_CELL_TB_BUG), "i" (SPRN_TBRL) : "cr0"); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) rval;})
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) #elif defined(CONFIG_PPC_8xx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) #define mftb() ({unsigned long rval; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) asm volatile("mftbl %0" : "=r" (rval)); rval;})
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) #define mftb() ({unsigned long rval; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) asm volatile("mfspr %0, %1" : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) "=r" (rval) : "i" (SPRN_TBRL)); rval;})
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) #endif /* !CONFIG_PPC_CELL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) #if defined(CONFIG_PPC_8xx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) #define mftbu() ({unsigned long rval; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) asm volatile("mftbu %0" : "=r" (rval)); rval;})
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) #define mftbu() ({unsigned long rval; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) asm volatile("mfspr %0, %1" : "=r" (rval) : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) "i" (SPRN_TBRU)); rval;})
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) #define mttbl(v) asm volatile("mttbl %0":: "r"(v))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) #define mttbu(v) asm volatile("mttbu %0":: "r"(v))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) #ifdef CONFIG_PPC32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) #define mfsrin(v) ({unsigned int rval; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) asm volatile("mfsrin %0,%1" : "=r" (rval) : "r" (v)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) rval;})
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) static inline void mtsrin(u32 val, u32 idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) asm volatile("mtsrin %0, %1" : : "r" (val), "r" (idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) #define proc_trap() asm volatile("trap")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) extern unsigned long current_stack_frame(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) register unsigned long current_stack_pointer asm("r1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) extern unsigned long scom970_read(unsigned int address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) extern void scom970_write(unsigned int address, unsigned long value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) struct pt_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) extern void ppc_save_regs(struct pt_regs *regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) static inline void update_power8_hid0(unsigned long hid0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) * The HID0 update on Power8 should at the very least be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) * preceded by a SYNC instruction followed by an ISYNC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) * instruction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) asm volatile("sync; mtspr %0,%1; isync":: "i"(SPRN_HID0), "r"(hid0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) #endif /* __ASSEMBLY__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) #endif /* __KERNEL__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) #endif /* _ASM_POWERPC_REG_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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