Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *  PS3 GPU declarations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *  Copyright 2009 Sony Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #ifndef _ASM_POWERPC_PS3GPU_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define _ASM_POWERPC_PS3GPU_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/lv1call.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define L1GPU_CONTEXT_ATTRIBUTE_DISPLAY_SYNC	0x101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define L1GPU_CONTEXT_ATTRIBUTE_DISPLAY_FLIP	0x102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define L1GPU_CONTEXT_ATTRIBUTE_FB_SETUP	0x600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT		0x601
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT_SYNC	0x602
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define L1GPU_CONTEXT_ATTRIBUTE_FB_CLOSE	0x603
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define L1GPU_FB_BLIT_WAIT_FOR_COMPLETION	(1ULL << 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define L1GPU_DISPLAY_SYNC_HSYNC		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define L1GPU_DISPLAY_SYNC_VSYNC		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* mutex synchronizing GPU accesses and video mode changes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) extern struct mutex ps3_gpu_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static inline int lv1_gpu_display_sync(u64 context_handle, u64 head,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 				       u64 ddr_offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	return lv1_gpu_context_attribute(context_handle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 					 L1GPU_CONTEXT_ATTRIBUTE_DISPLAY_SYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 					 head, ddr_offset, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static inline int lv1_gpu_display_flip(u64 context_handle, u64 head,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 				       u64 ddr_offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	return lv1_gpu_context_attribute(context_handle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 					 L1GPU_CONTEXT_ATTRIBUTE_DISPLAY_FLIP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 					 head, ddr_offset, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static inline int lv1_gpu_fb_setup(u64 context_handle, u64 xdr_lpar,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 				   u64 xdr_size, u64 ioif_offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	return lv1_gpu_context_attribute(context_handle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 					 L1GPU_CONTEXT_ATTRIBUTE_FB_SETUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 					 xdr_lpar, xdr_size, ioif_offset, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static inline int lv1_gpu_fb_blit(u64 context_handle, u64 ddr_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 				  u64 ioif_offset, u64 sync_width, u64 pitch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	return lv1_gpu_context_attribute(context_handle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 					 L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 					 ddr_offset, ioif_offset, sync_width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 					 pitch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static inline int lv1_gpu_fb_close(u64 context_handle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 	return lv1_gpu_context_attribute(context_handle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 					 L1GPU_CONTEXT_ATTRIBUTE_FB_CLOSE, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 					 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #endif /* _ASM_POWERPC_PS3GPU_H */