^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2009 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * provides masks and opcode images for use by code generation, emulation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * and for instructions that older assemblers might not know about
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef _ASM_POWERPC_PPC_OPCODE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define _ASM_POWERPC_PPC_OPCODE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/asm-const.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define __REG_R0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define __REG_R1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define __REG_R2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define __REG_R3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define __REG_R4 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define __REG_R5 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define __REG_R6 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define __REG_R7 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define __REG_R8 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define __REG_R9 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define __REG_R10 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define __REG_R11 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define __REG_R12 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define __REG_R13 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define __REG_R14 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define __REG_R15 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define __REG_R16 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define __REG_R17 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define __REG_R18 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define __REG_R19 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define __REG_R20 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define __REG_R21 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define __REG_R22 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define __REG_R23 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define __REG_R24 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define __REG_R25 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define __REG_R26 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define __REG_R27 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define __REG_R28 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define __REG_R29 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define __REG_R30 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define __REG_R31 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define __REGA0_0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define __REGA0_R1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define __REGA0_R2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define __REGA0_R3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define __REGA0_R4 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define __REGA0_R5 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define __REGA0_R6 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define __REGA0_R7 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define __REGA0_R8 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define __REGA0_R9 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define __REGA0_R10 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define __REGA0_R11 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define __REGA0_R12 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define __REGA0_R13 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define __REGA0_R14 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define __REGA0_R15 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define __REGA0_R16 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define __REGA0_R17 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define __REGA0_R18 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define __REGA0_R19 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define __REGA0_R20 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define __REGA0_R21 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define __REGA0_R22 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define __REGA0_R23 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define __REGA0_R24 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define __REGA0_R25 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define __REGA0_R26 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define __REGA0_R27 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define __REGA0_R28 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define __REGA0_R29 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define __REGA0_R30 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define __REGA0_R31 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define IMM_L(i) ((uintptr_t)(i) & 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define IMM_DS(i) ((uintptr_t)(i) & 0xfffc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * 16-bit immediate helper macros: HA() is for use with sign-extending instrs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * (e.g. LD, ADDI). If the bottom 16 bits is "-ve", add another bit into the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * top half to negate the effect (i.e. 0xffff + 1 = 0x(1)0000).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define IMM_H(i) ((uintptr_t)(i)>>16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define IMM_HA(i) (((uintptr_t)(i)>>16) + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) (((uintptr_t)(i) & 0x8000) >> 15))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* opcode and xopcode for instructions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define OP_TRAP 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define OP_TRAP_64 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define OP_31_XOP_TRAP 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define OP_31_XOP_LDX 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define OP_31_XOP_LWZX 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define OP_31_XOP_LDUX 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define OP_31_XOP_DCBST 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define OP_31_XOP_LWZUX 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define OP_31_XOP_TRAP_64 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define OP_31_XOP_DCBF 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define OP_31_XOP_LBZX 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define OP_31_XOP_STDX 149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define OP_31_XOP_STWX 151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define OP_31_XOP_STDUX 181
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define OP_31_XOP_STWUX 183
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define OP_31_XOP_STBX 215
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define OP_31_XOP_LBZUX 119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define OP_31_XOP_STBUX 247
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define OP_31_XOP_LHZX 279
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define OP_31_XOP_LHZUX 311
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define OP_31_XOP_MSGSNDP 142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define OP_31_XOP_MSGCLRP 174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define OP_31_XOP_TLBIE 306
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define OP_31_XOP_MFSPR 339
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define OP_31_XOP_LWAX 341
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define OP_31_XOP_LHAX 343
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define OP_31_XOP_LWAUX 373
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define OP_31_XOP_LHAUX 375
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define OP_31_XOP_STHX 407
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define OP_31_XOP_STHUX 439
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define OP_31_XOP_MTSPR 467
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define OP_31_XOP_DCBI 470
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define OP_31_XOP_LDBRX 532
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define OP_31_XOP_LWBRX 534
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define OP_31_XOP_TLBSYNC 566
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define OP_31_XOP_STDBRX 660
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define OP_31_XOP_STWBRX 662
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define OP_31_XOP_STFSX 663
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define OP_31_XOP_STFSUX 695
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define OP_31_XOP_STFDX 727
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define OP_31_XOP_STFDUX 759
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define OP_31_XOP_LHBRX 790
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define OP_31_XOP_LFIWAX 855
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define OP_31_XOP_LFIWZX 887
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define OP_31_XOP_STHBRX 918
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define OP_31_XOP_STFIWX 983
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* VSX Scalar Load Instructions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define OP_31_XOP_LXSDX 588
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define OP_31_XOP_LXSSPX 524
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define OP_31_XOP_LXSIWAX 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define OP_31_XOP_LXSIWZX 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* VSX Scalar Store Instructions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define OP_31_XOP_STXSDX 716
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define OP_31_XOP_STXSSPX 652
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define OP_31_XOP_STXSIWX 140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* VSX Vector Load Instructions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define OP_31_XOP_LXVD2X 844
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define OP_31_XOP_LXVW4X 780
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* VSX Vector Load and Splat Instruction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define OP_31_XOP_LXVDSX 332
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* VSX Vector Store Instructions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define OP_31_XOP_STXVD2X 972
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define OP_31_XOP_STXVW4X 908
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define OP_31_XOP_LFSX 535
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define OP_31_XOP_LFSUX 567
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define OP_31_XOP_LFDX 599
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define OP_31_XOP_LFDUX 631
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* VMX Vector Load Instructions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define OP_31_XOP_LVX 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* VMX Vector Store Instructions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define OP_31_XOP_STVX 231
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* Prefixed Instructions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define OP_PREFIX 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define OP_31 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define OP_LWZ 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define OP_STFS 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define OP_STFSU 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define OP_STFD 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define OP_STFDU 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define OP_LD 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define OP_LWZU 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define OP_LBZ 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define OP_LBZU 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define OP_STW 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define OP_STWU 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define OP_STD 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define OP_STB 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define OP_STBU 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define OP_LHZ 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define OP_LHZU 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define OP_LHA 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define OP_LHAU 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define OP_STH 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define OP_STHU 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define OP_LMW 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define OP_STMW 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define OP_LFS 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define OP_LFSU 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define OP_LFD 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define OP_LFDU 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define OP_STFS 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define OP_STFSU 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define OP_STFD 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define OP_STFDU 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define OP_LQ 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* sorted alphabetically */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define PPC_INST_BCCTR_FLUSH 0x4c400420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define PPC_INST_COPY 0x7c20060c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define PPC_INST_DCBA 0x7c0005ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define PPC_INST_DCBA_MASK 0xfc0007fe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define PPC_INST_ISEL 0x7c00001e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define PPC_INST_ISEL_MASK 0xfc00003e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define PPC_INST_LSWI 0x7c0004aa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define PPC_INST_LSWX 0x7c00042a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define PPC_INST_LWSYNC 0x7c2004ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define PPC_INST_SYNC 0x7c0004ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define PPC_INST_SYNC_MASK 0xfc0007fe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define PPC_INST_ISYNC 0x4c00012c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define PPC_INST_MCRXR 0x7c000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define PPC_INST_MCRXR_MASK 0xfc0007fe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define PPC_INST_MFSPR_PVR 0x7c1f42a6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define PPC_INST_MFSPR_PVR_MASK 0xfc1ffffe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define PPC_INST_MTMSRD 0x7c000164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define PPC_INST_NOP 0x60000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define PPC_INST_POPCNTB 0x7c0000f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define PPC_INST_POPCNTB_MASK 0xfc0007fe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define PPC_INST_RFEBB 0x4c000124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define PPC_INST_RFID 0x4c000024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define PPC_INST_MFSPR 0x7c0002a6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define PPC_INST_MFSPR_DSCR 0x7c1102a6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define PPC_INST_MFSPR_DSCR_MASK 0xfc1ffffe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define PPC_INST_MTSPR_DSCR 0x7c1103a6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define PPC_INST_MTSPR_DSCR_MASK 0xfc1ffffe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define PPC_INST_MFSPR_DSCR_USER 0x7c0302a6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define PPC_INST_MFSPR_DSCR_USER_MASK 0xfc1ffffe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define PPC_INST_MTSPR_DSCR_USER 0x7c0303a6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define PPC_INST_MTSPR_DSCR_USER_MASK 0xfc1ffffe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define PPC_INST_SC 0x44000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define PPC_INST_STRING 0x7c00042a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define PPC_INST_STRING_MASK 0xfc0007fe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define PPC_INST_STRING_GEN_MASK 0xfc00067e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define PPC_INST_STSWI 0x7c0005aa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define PPC_INST_STSWX 0x7c00052a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define PPC_INST_TRECHKPT 0x7c0007dd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define PPC_INST_TRECLAIM 0x7c00075d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define PPC_INST_TSR 0x7c0005dd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define PPC_INST_LD 0xe8000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define PPC_INST_STD 0xf8000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define PPC_INST_MFLR 0x7c0802a6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define PPC_INST_MTCTR 0x7c0903a6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define PPC_INST_ADDI 0x38000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define PPC_INST_ADDIS 0x3c000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define PPC_INST_ADD 0x7c000214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define PPC_INST_BLR 0x4e800020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define PPC_INST_BCTR 0x4e800420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define PPC_INST_BCTRL 0x4e800421
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define PPC_INST_DIVD 0x7c0003d2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define PPC_INST_RLDICR 0x78000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define PPC_INST_ORI 0x60000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define PPC_INST_ORIS 0x64000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define PPC_INST_BRANCH 0x48000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define PPC_INST_BRANCH_COND 0x40800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* Prefixes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define PPC_INST_LFS 0xc0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define PPC_INST_STFS 0xd0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define PPC_INST_LFD 0xc8000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define PPC_INST_STFD 0xd8000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define PPC_PREFIX_MLS 0x06000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define PPC_PREFIX_8LS 0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* Prefixed instructions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define PPC_INST_PLD 0xe4000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define PPC_INST_PSTD 0xf4000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* macros to insert fields into opcodes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define ___PPC_RA(a) (((a) & 0x1f) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define ___PPC_RB(b) (((b) & 0x1f) << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define ___PPC_RC(c) (((c) & 0x1f) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define ___PPC_RS(s) (((s) & 0x1f) << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define ___PPC_RT(t) ___PPC_RS(t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define ___PPC_R(r) (((r) & 0x1) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define ___PPC_PRS(prs) (((prs) & 0x1) << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define ___PPC_RIC(ric) (((ric) & 0x3) << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define __PPC_RA(a) ___PPC_RA(__REG_##a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define __PPC_RA0(a) ___PPC_RA(__REGA0_##a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define __PPC_RB(b) ___PPC_RB(__REG_##b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define __PPC_RS(s) ___PPC_RS(__REG_##s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define __PPC_RT(t) ___PPC_RT(__REG_##t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define __PPC_XA(a) ((((a) & 0x1f) << 16) | (((a) & 0x20) >> 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define __PPC_XB(b) ((((b) & 0x1f) << 11) | (((b) & 0x20) >> 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define __PPC_XS(s) ((((s) & 0x1f) << 21) | (((s) & 0x20) >> 5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define __PPC_XT(s) __PPC_XS(s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define __PPC_T_TLB(t) (((t) & 0x3) << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define __PPC_WC(w) (((w) & 0x3) << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define __PPC_WS(w) (((w) & 0x1f) << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define __PPC_SH(s) __PPC_WS(s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define __PPC_SH64(s) (__PPC_SH(s) | (((s) & 0x20) >> 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define __PPC_MB(s) ___PPC_RC(s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define __PPC_ME(s) (((s) & 0x1f) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define __PPC_MB64(s) (__PPC_MB(s) | ((s) & 0x20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define __PPC_ME64(s) __PPC_MB64(s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define __PPC_BI(s) (((s) & 0x1f) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define __PPC_CT(t) (((t) & 0x0f) << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define __PPC_SPR(r) ((((r) & 0x1f) << 16) | ((((r) >> 5) & 0x1f) << 11))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define __PPC_RC21 (0x1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define __PPC_PRFX_R(r) (((r) & 0x1) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * Both low and high 16 bits are added as SIGNED additions, so if low 16 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * has high bit set, high 16 bits must be adjusted. These macros do that (stolen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * from binutils).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define PPC_LO(v) ((v) & 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define PPC_HI(v) (((v) >> 16) & 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define PPC_HA(v) PPC_HI((v) + 0x8000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) * Only use the larx hint bit on 64bit CPUs. e500v1/v2 based CPUs will treat a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * larx with EH set as an illegal instruction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #ifdef CONFIG_PPC64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define __PPC_EH(eh) (((eh) & 0x1) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define __PPC_EH(eh) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /* Base instruction encoding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define PPC_RAW_CP_ABORT (0x7c00068c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define PPC_RAW_COPY(a, b) (PPC_INST_COPY | ___PPC_RA(a) | ___PPC_RB(b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define PPC_RAW_DARN(t, l) (0x7c0005e6 | ___PPC_RT(t) | (((l) & 0x3) << 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define PPC_RAW_DCBAL(a, b) (0x7c2005ec | __PPC_RA(a) | __PPC_RB(b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define PPC_RAW_DCBZL(a, b) (0x7c2007ec | __PPC_RA(a) | __PPC_RB(b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define PPC_RAW_LQARX(t, a, b, eh) (0x7c000228 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | __PPC_EH(eh))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define PPC_RAW_LDARX(t, a, b, eh) (0x7c0000a8 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | __PPC_EH(eh))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define PPC_RAW_LWARX(t, a, b, eh) (0x7c000028 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | __PPC_EH(eh))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define PPC_RAW_PHWSYNC (0x7c8004ac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define PPC_RAW_PLWSYNC (0x7ca004ac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define PPC_RAW_STQCX(t, a, b) (0x7c00016d | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define PPC_RAW_MADDHD(t, a, b, c) (0x10000030 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | ___PPC_RC(c))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define PPC_RAW_MADDHDU(t, a, b, c) (0x10000031 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | ___PPC_RC(c))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define PPC_RAW_MADDLD(t, a, b, c) (0x10000033 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | ___PPC_RC(c))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define PPC_RAW_MSGSND(b) (0x7c00019c | ___PPC_RB(b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define PPC_RAW_MSGSYNC (0x7c0006ec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define PPC_RAW_MSGCLR(b) (0x7c0001dc | ___PPC_RB(b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define PPC_RAW_MSGSNDP(b) (0x7c00011c | ___PPC_RB(b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define PPC_RAW_MSGCLRP(b) (0x7c00015c | ___PPC_RB(b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define PPC_RAW_PASTE(a, b) (0x7c20070d | ___PPC_RA(a) | ___PPC_RB(b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define PPC_RAW_POPCNTB(a, s) (PPC_INST_POPCNTB | __PPC_RA(a) | __PPC_RS(s))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define PPC_RAW_POPCNTD(a, s) (0x7c0003f4 | __PPC_RA(a) | __PPC_RS(s))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define PPC_RAW_POPCNTW(a, s) (0x7c0002f4 | __PPC_RA(a) | __PPC_RS(s))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define PPC_RAW_RFCI (0x4c000066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define PPC_RAW_RFDI (0x4c00004e)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define PPC_RAW_RFMCI (0x4c00004c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define PPC_RAW_TLBILX(t, a, b) (0x7c000024 | __PPC_T_TLB(t) | __PPC_RA0(a) | __PPC_RB(b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define PPC_RAW_WAIT(w) (0x7c00007c | __PPC_WC(w))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define PPC_RAW_TLBIE(lp, a) (0x7c000264 | ___PPC_RB(a) | ___PPC_RS(lp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define PPC_RAW_TLBIE_5(rb, rs, ric, prs, r) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) (0x7c000264 | ___PPC_RB(rb) | ___PPC_RS(rs) | ___PPC_RIC(ric) | ___PPC_PRS(prs) | ___PPC_R(r))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define PPC_RAW_TLBIEL(rb, rs, ric, prs, r) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) (0x7c000224 | ___PPC_RB(rb) | ___PPC_RS(rs) | ___PPC_RIC(ric) | ___PPC_PRS(prs) | ___PPC_R(r))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define PPC_RAW_TLBSRX_DOT(a, b) (0x7c0006a5 | __PPC_RA0(a) | __PPC_RB(b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define PPC_RAW_TLBIVAX(a, b) (0x7c000624 | __PPC_RA0(a) | __PPC_RB(b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define PPC_RAW_ERATWE(s, a, w) (0x7c0001a6 | __PPC_RS(s) | __PPC_RA(a) | __PPC_WS(w))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define PPC_RAW_ERATRE(s, a, w) (0x7c000166 | __PPC_RS(s) | __PPC_RA(a) | __PPC_WS(w))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define PPC_RAW_ERATILX(t, a, b) (0x7c000066 | __PPC_T_TLB(t) | __PPC_RA0(a) | __PPC_RB(b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define PPC_RAW_ERATIVAX(s, a, b) (0x7c000666 | __PPC_RS(s) | __PPC_RA0(a) | __PPC_RB(b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define PPC_RAW_ERATSX(t, a, w) (0x7c000126 | __PPC_RS(t) | __PPC_RA0(a) | __PPC_RB(b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define PPC_RAW_ERATSX_DOT(t, a, w) (0x7c000127 | __PPC_RS(t) | __PPC_RA0(a) | __PPC_RB(b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define PPC_RAW_SLBFEE_DOT(t, b) (0x7c0007a7 | __PPC_RT(t) | __PPC_RB(b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define __PPC_RAW_SLBFEE_DOT(t, b) (0x7c0007a7 | ___PPC_RT(t) | ___PPC_RB(b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define PPC_RAW_ICBT(c, a, b) (0x7c00002c | __PPC_CT(c) | __PPC_RA0(a) | __PPC_RB(b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define PPC_RAW_LBZCIX(t, a, b) (0x7c0006aa | __PPC_RT(t) | __PPC_RA(a) | __PPC_RB(b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define PPC_RAW_STBCIX(s, a, b) (0x7c0007aa | __PPC_RS(s) | __PPC_RA(a) | __PPC_RB(b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define PPC_RAW_DCBFPS(a, b) (0x7c0000ac | ___PPC_RA(a) | ___PPC_RB(b) | (4 << 21))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define PPC_RAW_DCBSTPS(a, b) (0x7c0000ac | ___PPC_RA(a) | ___PPC_RB(b) | (6 << 21))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) * Define what the VSX XX1 form instructions will look like, then add
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) * the 128 bit load store instructions based on that.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define VSX_XX1(s, a, b) (__PPC_XS(s) | __PPC_RA(a) | __PPC_RB(b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define VSX_XX3(t, a, b) (__PPC_XT(t) | __PPC_XA(a) | __PPC_XB(b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define PPC_RAW_STXVD2X(s, a, b) (0x7c000798 | VSX_XX1((s), a, b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define PPC_RAW_LXVD2X(s, a, b) (0x7c000698 | VSX_XX1((s), a, b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define PPC_RAW_MFVRD(a, t) (0x7c000066 | VSX_XX1((t) + 32, a, R0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define PPC_RAW_MTVRD(t, a) (0x7c000166 | VSX_XX1((t) + 32, a, R0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define PPC_RAW_VPMSUMW(t, a, b) (0x10000488 | VSX_XX3((t), a, b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define PPC_RAW_VPMSUMD(t, a, b) (0x100004c8 | VSX_XX3((t), a, b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define PPC_RAW_XXLOR(t, a, b) (0xf0000490 | VSX_XX3((t), a, b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define PPC_RAW_XXSWAPD(t, a) (0xf0000250 | VSX_XX3((t), a, a))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define PPC_RAW_XVCPSGNDP(t, a, b) ((0xf0000780 | VSX_XX3((t), (a), (b))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define PPC_RAW_VPERMXOR(vrt, vra, vrb, vrc) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) ((0x1000002d | ___PPC_RT(vrt) | ___PPC_RA(vra) | ___PPC_RB(vrb) | (((vrc) & 0x1f) << 6)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define PPC_RAW_NAP (0x4c000364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define PPC_RAW_SLEEP (0x4c0003a4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define PPC_RAW_WINKLE (0x4c0003e4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define PPC_RAW_STOP (0x4c0002e4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define PPC_RAW_CLRBHRB (0x7c00035c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define PPC_RAW_MFBHRBE(r, n) (0x7c00025c | __PPC_RT(r) | (((n) & 0x3ff) << 11))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define PPC_RAW_TRECHKPT (PPC_INST_TRECHKPT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define PPC_RAW_TRECLAIM(r) (PPC_INST_TRECLAIM | __PPC_RA(r))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define PPC_RAW_TABORT(r) (0x7c00071d | __PPC_RA(r))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define TMRN(x) ((((x) & 0x1f) << 16) | (((x) & 0x3e0) << 6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define PPC_RAW_MTTMR(tmr, r) (0x7c0003dc | TMRN(tmr) | ___PPC_RS(r))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define PPC_RAW_MFTMR(tmr, r) (0x7c0002dc | TMRN(tmr) | ___PPC_RT(r))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define PPC_RAW_ICSWX(s, a, b) (0x7c00032d | ___PPC_RS(s) | ___PPC_RA(a) | ___PPC_RB(b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define PPC_RAW_ICSWEPX(s, a, b) (0x7c00076d | ___PPC_RS(s) | ___PPC_RA(a) | ___PPC_RB(b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define PPC_RAW_SLBIA(IH) (0x7c0003e4 | (((IH) & 0x7) << 21))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define PPC_RAW_VCMPEQUD_RC(vrt, vra, vrb) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) (0x100000c7 | ___PPC_RT(vrt) | ___PPC_RA(vra) | ___PPC_RB(vrb) | __PPC_RC21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define PPC_RAW_VCMPEQUB_RC(vrt, vra, vrb) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) (0x10000006 | ___PPC_RT(vrt) | ___PPC_RA(vra) | ___PPC_RB(vrb) | __PPC_RC21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define PPC_RAW_LD(r, base, i) (PPC_INST_LD | ___PPC_RT(r) | ___PPC_RA(base) | IMM_DS(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define PPC_RAW_LWZ(r, base, i) (0x80000000 | ___PPC_RT(r) | ___PPC_RA(base) | IMM_L(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define PPC_RAW_LWZX(t, a, b) (0x7c00002e | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define PPC_RAW_STD(r, base, i) (PPC_INST_STD | ___PPC_RS(r) | ___PPC_RA(base) | IMM_DS(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define PPC_RAW_STDCX(s, a, b) (0x7c0001ad | ___PPC_RS(s) | ___PPC_RA(a) | ___PPC_RB(b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define PPC_RAW_LFSX(t, a, b) (0x7c00042e | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define PPC_RAW_STFSX(s, a, b) (0x7c00052e | ___PPC_RS(s) | ___PPC_RA(a) | ___PPC_RB(b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define PPC_RAW_LFDX(t, a, b) (0x7c0004ae | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define PPC_RAW_STFDX(s, a, b) (0x7c0005ae | ___PPC_RS(s) | ___PPC_RA(a) | ___PPC_RB(b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define PPC_RAW_LVX(t, a, b) (0x7c0000ce | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define PPC_RAW_STVX(s, a, b) (0x7c0001ce | ___PPC_RS(s) | ___PPC_RA(a) | ___PPC_RB(b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define PPC_RAW_ADD(t, a, b) (PPC_INST_ADD | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define PPC_RAW_ADD_DOT(t, a, b) (PPC_INST_ADD | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define PPC_RAW_ADDC(t, a, b) (0x7c000014 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define PPC_RAW_ADDC_DOT(t, a, b) (0x7c000014 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define PPC_RAW_NOP() (PPC_INST_NOP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define PPC_RAW_BLR() (PPC_INST_BLR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define PPC_RAW_BLRL() (0x4e800021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define PPC_RAW_MTLR(r) (0x7c0803a6 | ___PPC_RT(r))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define PPC_RAW_BCTR() (PPC_INST_BCTR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define PPC_RAW_MTCTR(r) (PPC_INST_MTCTR | ___PPC_RT(r))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define PPC_RAW_ADDI(d, a, i) (PPC_INST_ADDI | ___PPC_RT(d) | ___PPC_RA(a) | IMM_L(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define PPC_RAW_LI(r, i) PPC_RAW_ADDI(r, 0, i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define PPC_RAW_ADDIS(d, a, i) (PPC_INST_ADDIS | ___PPC_RT(d) | ___PPC_RA(a) | IMM_L(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define PPC_RAW_LIS(r, i) PPC_RAW_ADDIS(r, 0, i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define PPC_RAW_STDX(r, base, b) (0x7c00012a | ___PPC_RS(r) | ___PPC_RA(base) | ___PPC_RB(b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define PPC_RAW_STDU(r, base, i) (0xf8000001 | ___PPC_RS(r) | ___PPC_RA(base) | ((i) & 0xfffc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define PPC_RAW_STW(r, base, i) (0x90000000 | ___PPC_RS(r) | ___PPC_RA(base) | IMM_L(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define PPC_RAW_STWU(r, base, i) (0x94000000 | ___PPC_RS(r) | ___PPC_RA(base) | IMM_L(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define PPC_RAW_STH(r, base, i) (0xb0000000 | ___PPC_RS(r) | ___PPC_RA(base) | IMM_L(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define PPC_RAW_STB(r, base, i) (0x98000000 | ___PPC_RS(r) | ___PPC_RA(base) | IMM_L(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define PPC_RAW_LBZ(r, base, i) (0x88000000 | ___PPC_RT(r) | ___PPC_RA(base) | IMM_L(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define PPC_RAW_LDX(r, base, b) (0x7c00002a | ___PPC_RT(r) | ___PPC_RA(base) | ___PPC_RB(b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define PPC_RAW_LHZ(r, base, i) (0xa0000000 | ___PPC_RT(r) | ___PPC_RA(base) | IMM_L(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define PPC_RAW_LHBRX(r, base, b) (0x7c00062c | ___PPC_RT(r) | ___PPC_RA(base) | ___PPC_RB(b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define PPC_RAW_LWBRX(r, base, b) (0x7c00042c | ___PPC_RT(r) | ___PPC_RA(base) | ___PPC_RB(b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define PPC_RAW_LDBRX(r, base, b) (0x7c000428 | ___PPC_RT(r) | ___PPC_RA(base) | ___PPC_RB(b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define PPC_RAW_STWCX(s, a, b) (0x7c00012d | ___PPC_RS(s) | ___PPC_RA(a) | ___PPC_RB(b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define PPC_RAW_CMPWI(a, i) (0x2c000000 | ___PPC_RA(a) | IMM_L(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define PPC_RAW_CMPDI(a, i) (0x2c200000 | ___PPC_RA(a) | IMM_L(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define PPC_RAW_CMPW(a, b) (0x7c000000 | ___PPC_RA(a) | ___PPC_RB(b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define PPC_RAW_CMPD(a, b) (0x7c200000 | ___PPC_RA(a) | ___PPC_RB(b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define PPC_RAW_CMPLWI(a, i) (0x28000000 | ___PPC_RA(a) | IMM_L(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define PPC_RAW_CMPLDI(a, i) (0x28200000 | ___PPC_RA(a) | IMM_L(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define PPC_RAW_CMPLW(a, b) (0x7c000040 | ___PPC_RA(a) | ___PPC_RB(b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define PPC_RAW_CMPLD(a, b) (0x7c200040 | ___PPC_RA(a) | ___PPC_RB(b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define PPC_RAW_SUB(d, a, b) (0x7c000050 | ___PPC_RT(d) | ___PPC_RB(a) | ___PPC_RA(b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define PPC_RAW_MULD(d, a, b) (0x7c0001d2 | ___PPC_RT(d) | ___PPC_RA(a) | ___PPC_RB(b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define PPC_RAW_MULW(d, a, b) (0x7c0001d6 | ___PPC_RT(d) | ___PPC_RA(a) | ___PPC_RB(b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define PPC_RAW_MULHWU(d, a, b) (0x7c000016 | ___PPC_RT(d) | ___PPC_RA(a) | ___PPC_RB(b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define PPC_RAW_MULI(d, a, i) (0x1c000000 | ___PPC_RT(d) | ___PPC_RA(a) | IMM_L(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define PPC_RAW_DIVWU(d, a, b) (0x7c000396 | ___PPC_RT(d) | ___PPC_RA(a) | ___PPC_RB(b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define PPC_RAW_DIVDU(d, a, b) (0x7c000392 | ___PPC_RT(d) | ___PPC_RA(a) | ___PPC_RB(b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define PPC_RAW_DIVDE(t, a, b) (0x7c000352 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define PPC_RAW_DIVDE_DOT(t, a, b) (0x7c000352 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define PPC_RAW_DIVDEU(t, a, b) (0x7c000312 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define PPC_RAW_DIVDEU_DOT(t, a, b) (0x7c000312 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define PPC_RAW_AND(d, a, b) (0x7c000038 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define PPC_RAW_ANDI(d, a, i) (0x70000000 | ___PPC_RA(d) | ___PPC_RS(a) | IMM_L(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define PPC_RAW_AND_DOT(d, a, b) (0x7c000039 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define PPC_RAW_OR(d, a, b) (0x7c000378 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define PPC_RAW_MR(d, a) PPC_RAW_OR(d, a, a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define PPC_RAW_ORI(d, a, i) (PPC_INST_ORI | ___PPC_RA(d) | ___PPC_RS(a) | IMM_L(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define PPC_RAW_ORIS(d, a, i) (PPC_INST_ORIS | ___PPC_RA(d) | ___PPC_RS(a) | IMM_L(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define PPC_RAW_XOR(d, a, b) (0x7c000278 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define PPC_RAW_XORI(d, a, i) (0x68000000 | ___PPC_RA(d) | ___PPC_RS(a) | IMM_L(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define PPC_RAW_XORIS(d, a, i) (0x6c000000 | ___PPC_RA(d) | ___PPC_RS(a) | IMM_L(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define PPC_RAW_EXTSW(d, a) (0x7c0007b4 | ___PPC_RA(d) | ___PPC_RS(a))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define PPC_RAW_SLW(d, a, s) (0x7c000030 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(s))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define PPC_RAW_SLD(d, a, s) (0x7c000036 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(s))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define PPC_RAW_SRW(d, a, s) (0x7c000430 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(s))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define PPC_RAW_SRAW(d, a, s) (0x7c000630 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(s))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define PPC_RAW_SRAWI(d, a, i) (0x7c000670 | ___PPC_RA(d) | ___PPC_RS(a) | __PPC_SH(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define PPC_RAW_SRD(d, a, s) (0x7c000436 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(s))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define PPC_RAW_SRAD(d, a, s) (0x7c000634 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(s))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define PPC_RAW_SRADI(d, a, i) (0x7c000674 | ___PPC_RA(d) | ___PPC_RS(a) | __PPC_SH64(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define PPC_RAW_RLWINM(d, a, i, mb, me) (0x54000000 | ___PPC_RA(d) | ___PPC_RS(a) | __PPC_SH(i) | __PPC_MB(mb) | __PPC_ME(me))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define PPC_RAW_RLWINM_DOT(d, a, i, mb, me) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) (0x54000001 | ___PPC_RA(d) | ___PPC_RS(a) | __PPC_SH(i) | __PPC_MB(mb) | __PPC_ME(me))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define PPC_RAW_RLWIMI(d, a, i, mb, me) (0x50000000 | ___PPC_RA(d) | ___PPC_RS(a) | __PPC_SH(i) | __PPC_MB(mb) | __PPC_ME(me))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define PPC_RAW_RLDICL(d, a, i, mb) (0x78000000 | ___PPC_RA(d) | ___PPC_RS(a) | __PPC_SH64(i) | __PPC_MB64(mb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define PPC_RAW_RLDICR(d, a, i, me) (PPC_INST_RLDICR | ___PPC_RA(d) | ___PPC_RS(a) | __PPC_SH64(i) | __PPC_ME64(me))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) /* slwi = rlwinm Rx, Ry, n, 0, 31-n */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define PPC_RAW_SLWI(d, a, i) PPC_RAW_RLWINM(d, a, i, 0, 31-(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) /* srwi = rlwinm Rx, Ry, 32-n, n, 31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define PPC_RAW_SRWI(d, a, i) PPC_RAW_RLWINM(d, a, 32-(i), i, 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) /* sldi = rldicr Rx, Ry, n, 63-n */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define PPC_RAW_SLDI(d, a, i) PPC_RAW_RLDICR(d, a, i, 63-(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) /* sldi = rldicl Rx, Ry, 64-n, n */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define PPC_RAW_SRDI(d, a, i) PPC_RAW_RLDICL(d, a, 64-(i), i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define PPC_RAW_NEG(d, a) (0x7c0000d0 | ___PPC_RT(d) | ___PPC_RA(a))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) /* Deal with instructions that older assemblers aren't aware of */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define PPC_BCCTR_FLUSH stringify_in_c(.long PPC_INST_BCCTR_FLUSH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define PPC_CP_ABORT stringify_in_c(.long PPC_RAW_CP_ABORT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define PPC_COPY(a, b) stringify_in_c(.long PPC_RAW_COPY(a, b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define PPC_DARN(t, l) stringify_in_c(.long PPC_RAW_DARN(t, l))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define PPC_DCBAL(a, b) stringify_in_c(.long PPC_RAW_DCBAL(a, b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define PPC_DCBZL(a, b) stringify_in_c(.long PPC_RAW_DCBZL(a, b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define PPC_DIVDE(t, a, b) stringify_in_c(.long PPC_RAW_DIVDE(t, a, b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define PPC_DIVDEU(t, a, b) stringify_in_c(.long PPC_RAW_DIVDEU(t, a, b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define PPC_LQARX(t, a, b, eh) stringify_in_c(.long PPC_RAW_LQARX(t, a, b, eh))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define PPC_LDARX(t, a, b, eh) stringify_in_c(.long PPC_RAW_LDARX(t, a, b, eh))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define PPC_LWARX(t, a, b, eh) stringify_in_c(.long PPC_RAW_LWARX(t, a, b, eh))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define PPC_STQCX(t, a, b) stringify_in_c(.long PPC_RAW_STQCX(t, a, b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define PPC_MADDHD(t, a, b, c) stringify_in_c(.long PPC_RAW_MADDHD(t, a, b, c))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define PPC_MADDHDU(t, a, b, c) stringify_in_c(.long PPC_RAW_MADDHDU(t, a, b, c))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define PPC_MADDLD(t, a, b, c) stringify_in_c(.long PPC_RAW_MADDLD(t, a, b, c))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define PPC_MSGSND(b) stringify_in_c(.long PPC_RAW_MSGSND(b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define PPC_MSGSYNC stringify_in_c(.long PPC_RAW_MSGSYNC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define PPC_MSGCLR(b) stringify_in_c(.long PPC_RAW_MSGCLR(b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define PPC_MSGSNDP(b) stringify_in_c(.long PPC_RAW_MSGSNDP(b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define PPC_MSGCLRP(b) stringify_in_c(.long PPC_RAW_MSGCLRP(b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define PPC_PASTE(a, b) stringify_in_c(.long PPC_RAW_PASTE(a, b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define PPC_POPCNTB(a, s) stringify_in_c(.long PPC_RAW_POPCNTB(a, s))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define PPC_POPCNTD(a, s) stringify_in_c(.long PPC_RAW_POPCNTD(a, s))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define PPC_POPCNTW(a, s) stringify_in_c(.long PPC_RAW_POPCNTW(a, s))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define PPC_RFCI stringify_in_c(.long PPC_RAW_RFCI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define PPC_RFDI stringify_in_c(.long PPC_RAW_RFDI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define PPC_RFMCI stringify_in_c(.long PPC_RAW_RFMCI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define PPC_TLBILX(t, a, b) stringify_in_c(.long PPC_RAW_TLBILX(t, a, b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define PPC_TLBILX_ALL(a, b) PPC_TLBILX(0, a, b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define PPC_TLBILX_PID(a, b) PPC_TLBILX(1, a, b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define PPC_TLBILX_VA(a, b) PPC_TLBILX(3, a, b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define PPC_WAIT(w) stringify_in_c(.long PPC_RAW_WAIT(w))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define PPC_TLBIE(lp, a) stringify_in_c(.long PPC_RAW_TLBIE(lp, a))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define PPC_TLBIE_5(rb, rs, ric, prs, r) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) stringify_in_c(.long PPC_RAW_TLBIE_5(rb, rs, ric, prs, r))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define PPC_TLBIEL(rb,rs,ric,prs,r) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) stringify_in_c(.long PPC_RAW_TLBIEL(rb, rs, ric, prs, r))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define PPC_TLBSRX_DOT(a, b) stringify_in_c(.long PPC_RAW_TLBSRX_DOT(a, b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define PPC_TLBIVAX(a, b) stringify_in_c(.long PPC_RAW_TLBIVAX(a, b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define PPC_ERATWE(s, a, w) stringify_in_c(.long PPC_RAW_ERATWE(s, a, w))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define PPC_ERATRE(s, a, w) stringify_in_c(.long PPC_RAW_ERATRE(a, a, w))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define PPC_ERATILX(t, a, b) stringify_in_c(.long PPC_RAW_ERATILX(t, a, b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define PPC_ERATIVAX(s, a, b) stringify_in_c(.long PPC_RAW_ERATIVAX(s, a, b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define PPC_ERATSX(t, a, w) stringify_in_c(.long PPC_RAW_ERATSX(t, a, w))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define PPC_ERATSX_DOT(t, a, w) stringify_in_c(.long PPC_RAW_ERATSX_DOT(t, a, w))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define PPC_SLBFEE_DOT(t, b) stringify_in_c(.long PPC_RAW_SLBFEE_DOT(t, b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define __PPC_SLBFEE_DOT(t, b) stringify_in_c(.long __PPC_RAW_SLBFEE_DOT(t, b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define PPC_ICBT(c, a, b) stringify_in_c(.long PPC_RAW_ICBT(c, a, b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) /* PASemi instructions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define LBZCIX(t, a, b) stringify_in_c(.long PPC_RAW_LBZCIX(t, a, b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define STBCIX(s, a, b) stringify_in_c(.long PPC_RAW_STBCIX(s, a, b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define PPC_DCBFPS(a, b) stringify_in_c(.long PPC_RAW_DCBFPS(a, b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define PPC_DCBSTPS(a, b) stringify_in_c(.long PPC_RAW_DCBSTPS(a, b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define PPC_PHWSYNC stringify_in_c(.long PPC_RAW_PHWSYNC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define PPC_PLWSYNC stringify_in_c(.long PPC_RAW_PLWSYNC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define STXVD2X(s, a, b) stringify_in_c(.long PPC_RAW_STXVD2X(s, a, b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define LXVD2X(s, a, b) stringify_in_c(.long PPC_RAW_LXVD2X(s, a, b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define MFVRD(a, t) stringify_in_c(.long PPC_RAW_MFVRD(a, t))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define MTVRD(t, a) stringify_in_c(.long PPC_RAW_MTVRD(t, a))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #define VPMSUMW(t, a, b) stringify_in_c(.long PPC_RAW_VPMSUMW(t, a, b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define VPMSUMD(t, a, b) stringify_in_c(.long PPC_RAW_VPMSUMD(t, a, b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define XXLOR(t, a, b) stringify_in_c(.long PPC_RAW_XXLOR(t, a, b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define XXSWAPD(t, a) stringify_in_c(.long PPC_RAW_XXSWAPD(t, a))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define XVCPSGNDP(t, a, b) stringify_in_c(.long (PPC_RAW_XVCPSGNDP(t, a, b)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define VPERMXOR(vrt, vra, vrb, vrc) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) stringify_in_c(.long (PPC_RAW_VPERMXOR(vrt, vra, vrb, vrc)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define PPC_NAP stringify_in_c(.long PPC_RAW_NAP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define PPC_SLEEP stringify_in_c(.long PPC_RAW_SLEEP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define PPC_WINKLE stringify_in_c(.long PPC_RAW_WINKLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #define PPC_STOP stringify_in_c(.long PPC_RAW_STOP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) /* BHRB instructions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define PPC_CLRBHRB stringify_in_c(.long PPC_RAW_CLRBHRB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #define PPC_MFBHRBE(r, n) stringify_in_c(.long PPC_RAW_MFBHRBE(r, n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) /* Transactional memory instructions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #define TRECHKPT stringify_in_c(.long PPC_RAW_TRECHKPT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #define TRECLAIM(r) stringify_in_c(.long PPC_RAW_TRECLAIM(r))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define TABORT(r) stringify_in_c(.long PPC_RAW_TABORT(r))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) /* book3e thread control instructions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #define MTTMR(tmr, r) stringify_in_c(.long PPC_RAW_MTTMR(tmr, r))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) #define MFTMR(tmr, r) stringify_in_c(.long PPC_RAW_MFTMR(tmr, r))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) /* Coprocessor instructions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #define PPC_ICSWX(s, a, b) stringify_in_c(.long PPC_RAW_ICSWX(s, a, b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #define PPC_ICSWEPX(s, a, b) stringify_in_c(.long PPC_RAW_ICSWEPX(s, a, b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #define PPC_SLBIA(IH) stringify_in_c(.long PPC_RAW_SLBIA(IH))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) * These may only be used on ISA v3.0 or later (aka. CPU_FTR_ARCH_300, radix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) * implies CPU_FTR_ARCH_300). USER/GUEST invalidates may only be used by radix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) * mode (on HPT these would also invalidate various SLBEs which may not be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) * desired).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #define PPC_ISA_3_0_INVALIDATE_ERAT PPC_SLBIA(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define PPC_RADIX_INVALIDATE_ERAT_USER PPC_SLBIA(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #define PPC_RADIX_INVALIDATE_ERAT_GUEST PPC_SLBIA(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define VCMPEQUD_RC(vrt, vra, vrb) stringify_in_c(.long PPC_RAW_VCMPEQUD_RC(vrt, vra, vrb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define VCMPEQUB_RC(vrt, vra, vrb) stringify_in_c(.long PPC_RAW_VCMPEQUB_RC(vrt, vra, vrb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #endif /* _ASM_POWERPC_PPC_OPCODE_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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