Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) // Copyright 2017 IBM Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) #ifndef _ASM_PNV_OCXL_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) #define _ASM_PNV_OCXL_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #define PNV_OCXL_TL_MAX_TEMPLATE        63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define PNV_OCXL_TL_BITS_PER_RATE       4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define PNV_OCXL_TL_RATE_BUF_SIZE       ((PNV_OCXL_TL_MAX_TEMPLATE+1) * PNV_OCXL_TL_BITS_PER_RATE / 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) int pnv_ocxl_get_actag(struct pci_dev *dev, u16 *base, u16 *enabled, u16 *supported);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) int pnv_ocxl_get_pasid_count(struct pci_dev *dev, int *count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) int pnv_ocxl_get_tl_cap(struct pci_dev *dev, long *cap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 			char *rate_buf, int rate_buf_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) int pnv_ocxl_set_tl_conf(struct pci_dev *dev, long cap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 			 uint64_t rate_buf_phys, int rate_buf_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) int pnv_ocxl_get_xsl_irq(struct pci_dev *dev, int *hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) void pnv_ocxl_unmap_xsl_regs(void __iomem *dsisr, void __iomem *dar,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 			     void __iomem *tfc, void __iomem *pe_handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) int pnv_ocxl_map_xsl_regs(struct pci_dev *dev, void __iomem **dsisr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 			  void __iomem **dar, void __iomem **tfc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 			  void __iomem **pe_handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) int pnv_ocxl_spa_setup(struct pci_dev *dev, void *spa_mem, int PE_mask, void **platform_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) void pnv_ocxl_spa_release(void *platform_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) int pnv_ocxl_spa_remove_pe_from_cache(void *platform_data, int pe_handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #endif /* _ASM_PNV_OCXL_H */