^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef __ASM_POWERPC_PCI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define __ASM_POWERPC_PCI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #ifdef __KERNEL__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/dma-map-ops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/scatterlist.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/machdep.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/prom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/pci-bridge.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* Return values for pci_controller_ops.probe_mode function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PCI_PROBE_NONE -1 /* Don't look at this bus at all */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PCI_PROBE_NORMAL 0 /* Do normal PCI probing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PCI_PROBE_DEVTREE 1 /* Instantiate from device tree */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PCIBIOS_MIN_IO 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PCIBIOS_MIN_MEM 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* Values for the `which' argument to sys_pciconfig_iobase syscall. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define IOBASE_BRIDGE_NUMBER 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define IOBASE_MEMORY 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define IOBASE_IO 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define IOBASE_ISA_IO 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define IOBASE_ISA_MEM 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * Set this to 1 if you want the kernel to re-assign all PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * bus numbers (don't do that on ppc64 yet !)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define pcibios_assign_all_busses() \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) (pci_has_flag(PCI_REASSIGN_ALL_BUS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define HAVE_ARCH_PCI_GET_LEGACY_IDE_IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) if (ppc_md.pci_get_legacy_ide_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) return ppc_md.pci_get_legacy_ide_irq(dev, channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) return channel ? 15 : 14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) extern void set_pci_dma_ops(const struct dma_map_ops *dma_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #else /* CONFIG_PCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define set_pci_dma_ops(d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #ifdef CONFIG_PPC64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * We want to avoid touching the cacheline size or MWI bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * pSeries firmware sets the cacheline size (which is not the cpu cacheline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * size in all cases) and hardware treats MWI the same as memory write.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PCI_DISABLE_MWI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #endif /* CONFIG_PPC64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) extern int pci_domain_nr(struct pci_bus *bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* Decide whether to display the domain number in /proc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) extern int pci_proc_domain(struct pci_bus *bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct vm_area_struct;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* Tell PCI code what kind of PCI resource mappings we support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define HAVE_PCI_MMAP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define ARCH_GENERIC_PCI_MMAP_RESOURCE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define arch_can_pci_mmap_io() 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define arch_can_pci_mmap_wc() 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) extern int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) size_t count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) extern int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) size_t count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) extern int pci_mmap_legacy_page_range(struct pci_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct vm_area_struct *vma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) enum pci_mmap_state mmap_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define HAVE_PCI_LEGACY 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) extern void pcibios_claim_one_bus(struct pci_bus *b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) extern void pcibios_finish_adding_to_bus(struct pci_bus *bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) extern void pcibios_resource_survey(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) extern struct pci_controller *init_phb_dynamic(struct device_node *dn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) extern int remove_phb_dynamic(struct pci_controller *phb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) extern struct pci_dev *of_create_pci_dev(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct pci_bus *bus, int devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) extern unsigned int pci_parse_of_flags(u32 addr0, int bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) extern void of_scan_pci_bridge(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) extern void of_scan_bus(struct device_node *node, struct pci_bus *bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) extern void of_rescan_bus(struct device_node *node, struct pci_bus *bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct file;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) extern pgprot_t pci_phys_mem_access_prot(struct file *file,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) unsigned long pfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) unsigned long size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) pgprot_t prot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) extern resource_size_t pcibios_io_space_offset(struct pci_controller *hose);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) extern void pcibios_setup_bus_self(struct pci_bus *bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) extern void pcibios_setup_phb_io_space(struct pci_controller *hose);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) extern void pcibios_scan_phb(struct pci_controller *hose);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #endif /* __KERNEL__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) extern struct pci_dev *pnv_pci_get_gpu_dev(struct pci_dev *npdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) extern struct pci_dev *pnv_pci_get_npu_dev(struct pci_dev *gpdev, int index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) extern int pnv_npu2_init(struct pci_controller *hose);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) extern int pnv_npu2_map_lpar_dev(struct pci_dev *gpdev, unsigned int lparid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) unsigned long msr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) extern int pnv_npu2_unmap_lpar_dev(struct pci_dev *gpdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #endif /* __ASM_POWERPC_PCI_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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