^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef _ASM_POWERPC_PCI_BRIDGE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define _ASM_POWERPC_PCI_BRIDGE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #ifdef __KERNEL__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/numa.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) struct device_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * PCI controller operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) struct pci_controller_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) void (*dma_dev_setup)(struct pci_dev *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) void (*dma_bus_setup)(struct pci_bus *bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) bool (*iommu_bypass_supported)(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) u64 mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) int (*probe_mode)(struct pci_bus *bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* Called when pci_enable_device() is called. Returns true to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * allow assignment/enabling of the device. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) bool (*enable_device_hook)(struct pci_dev *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) void (*disable_device)(struct pci_dev *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) void (*release_device)(struct pci_dev *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* Called during PCI resource reassignment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) resource_size_t (*window_alignment)(struct pci_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) unsigned long type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) void (*setup_bridge)(struct pci_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) unsigned long type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) void (*reset_secondary_bus)(struct pci_dev *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #ifdef CONFIG_PCI_MSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) int (*setup_msi_irqs)(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) int nvec, int type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) void (*teardown_msi_irqs)(struct pci_dev *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) void (*shutdown)(struct pci_controller *hose);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * Structure of a PCI controller (host bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct pci_controller {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct pci_bus *bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) char is_dynamic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #ifdef CONFIG_PPC64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) int node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct device_node *dn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct list_head list_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct device *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) int first_busno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) int last_busno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) int self_busno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct resource busn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) void __iomem *io_base_virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #ifdef CONFIG_PPC64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) void __iomem *io_base_alloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) resource_size_t io_base_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) resource_size_t pci_io_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* Some machines have a special region to forward the ISA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * "memory" cycles such as VGA memory regions. Left to 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * if unsupported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) resource_size_t isa_mem_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) resource_size_t isa_mem_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct pci_controller_ops controller_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct pci_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) unsigned int __iomem *cfg_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) void __iomem *cfg_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * Used for variants of PCI indirect handling and possible quirks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * EXT_REG - provides access to PCI-e extended registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * SURPRESS_PRIMARY_BUS - we suppress the setting of PCI_PRIMARY_BUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * to determine which bus number to match on when generating type0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * config cycles
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * NO_PCIE_LINK - the Freescale PCI-e controllers have issues with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * hanging if we don't have link and try to do config cycles to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * anything but the PHB. Only allow talking to the PHB if this is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * BIG_ENDIAN - cfg_addr is a big endian register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * the PLB4. Effectively disable MRM commands by setting this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * FSL_CFG_REG_LINK - Freescale controller version in which the PCIe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * link status is in a RC PCIe cfg register (vs being a SoC register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define PPC_INDIRECT_TYPE_SET_CFG_TYPE 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define PPC_INDIRECT_TYPE_EXT_REG 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define PPC_INDIRECT_TYPE_NO_PCIE_LINK 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define PPC_INDIRECT_TYPE_BIG_ENDIAN 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define PPC_INDIRECT_TYPE_BROKEN_MRM 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u32 indirect_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* Currently, we limit ourselves to 1 IO range and 3 mem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * ranges since the common pci_bus structure can't handle more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct resource io_resource;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct resource mem_resources[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) resource_size_t mem_offset[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) int global_number; /* PCI domain number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) resource_size_t dma_window_base_cur;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) resource_size_t dma_window_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #ifdef CONFIG_PPC64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) unsigned long buid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct pci_dn *pci_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #endif /* CONFIG_PPC64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) void *private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct npu *npu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* These are used for config access before all the PCI probing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) has been done. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) extern int early_read_config_byte(struct pci_controller *hose, int bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) int dev_fn, int where, u8 *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) extern int early_read_config_word(struct pci_controller *hose, int bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) int dev_fn, int where, u16 *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) extern int early_read_config_dword(struct pci_controller *hose, int bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) int dev_fn, int where, u32 *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) extern int early_write_config_byte(struct pci_controller *hose, int bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) int dev_fn, int where, u8 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) extern int early_write_config_word(struct pci_controller *hose, int bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) int dev_fn, int where, u16 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) extern int early_write_config_dword(struct pci_controller *hose, int bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) int dev_fn, int where, u32 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) extern int early_find_capability(struct pci_controller *hose, int bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) int dev_fn, int cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) extern void setup_indirect_pci(struct pci_controller* hose,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) resource_size_t cfg_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) resource_size_t cfg_data, u32 flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) extern int indirect_read_config(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) int offset, int len, u32 *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) extern int __indirect_read_config(struct pci_controller *hose,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) unsigned char bus_number, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) int offset, int len, u32 *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) extern int indirect_write_config(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) int offset, int len, u32 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return bus->sysdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #ifndef CONFIG_PPC64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) extern int pci_device_from_OF_node(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u8 *bus, u8 *devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) extern void pci_create_OF_bus_map(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #else /* CONFIG_PPC64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * PCI stuff, for nodes representing PCI devices, pointed to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * by device_node->data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct iommu_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct pci_dn {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) int flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define PCI_DN_FLAG_IOV_VF 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define PCI_DN_FLAG_DEAD 0x02 /* Device has been hot-removed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) int busno; /* pci bus number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) int devfn; /* pci device and function number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) int vendor_id; /* Vendor ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) int device_id; /* Device ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) int class_code; /* Device class code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct pci_dn *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct pci_controller *phb; /* for pci devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct iommu_table_group *table_group; /* for phb's or bridges */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) int pci_ext_config_space; /* for pci devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #ifdef CONFIG_EEH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct eeh_dev *edev; /* eeh device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define IODA_INVALID_PE 0xFFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) unsigned int pe_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #ifdef CONFIG_PCI_IOV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u16 vfs_expanded; /* number of VFs IOV BAR expanded */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) u16 num_vfs; /* number of VFs enabled*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) unsigned int *pe_num_map; /* PE# for the first VF PE or array */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) bool m64_single_mode; /* Use M64 BAR in Single Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define IODA_INVALID_M64 (-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) int (*m64_map)[PCI_SRIOV_NUM_BARS]; /* Only used on powernv */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) int last_allow_rc; /* Only used on pseries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #endif /* CONFIG_PCI_IOV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) int mps; /* Maximum Payload Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct list_head child_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct resource holes[PCI_SRIOV_NUM_BARS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* Get the pointer to a device_node's pci_dn */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define PCI_DN(dn) ((struct pci_dn *) (dn)->data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) extern struct pci_dn *pci_get_pdn_by_devfn(struct pci_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) int devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) extern struct pci_dn *pci_get_pdn(struct pci_dev *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) extern struct pci_dn *pci_add_device_node_info(struct pci_controller *hose,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct device_node *dn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) extern void pci_remove_device_node_info(struct device_node *dn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #ifdef CONFIG_PCI_IOV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct pci_dn *add_sriov_vf_pdns(struct pci_dev *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) void remove_sriov_vf_pdns(struct pci_dev *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static inline int pci_device_from_OF_node(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) u8 *bus, u8 *devfn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (!PCI_DN(np))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) *bus = PCI_DN(np)->busno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) *devfn = PCI_DN(np)->devfn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #if defined(CONFIG_EEH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static inline struct eeh_dev *pdn_to_eeh_dev(struct pci_dn *pdn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return pdn ? pdn->edev : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define pdn_to_eeh_dev(x) (NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /** Find the bus corresponding to the indicated device node */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) extern struct pci_bus *pci_find_bus_by_node(struct device_node *dn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /** Remove all of the PCI devices under this bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) extern void pci_hp_remove_devices(struct pci_bus *bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /** Discover new pci devices under this bus, and add them */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) extern void pci_hp_add_devices(struct pci_bus *bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) extern int pcibios_unmap_io_space(struct pci_bus *bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) extern int pcibios_map_io_space(struct pci_bus *bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #ifdef CONFIG_NUMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define PHB_SET_NODE(PHB, NODE) ((PHB)->node = (NODE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define PHB_SET_NODE(PHB, NODE) ((PHB)->node = NUMA_NO_NODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #endif /* CONFIG_PPC64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* Get the PCI host controller for an OF device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) extern struct pci_controller *pci_find_hose_for_OF_device(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) struct device_node* node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) extern struct pci_controller *pci_find_controller_for_domain(int domain_nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* Fill up host controller resources from the OF node */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) struct device_node *dev, int primary);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* Allocate & free a PCI host bridge structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) extern void pcibios_free_controller(struct pci_controller *phb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) extern void pcibios_free_controller_deferred(struct pci_host_bridge *bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) extern int pcibios_vaddr_is_ioport(void __iomem *address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static inline int pcibios_vaddr_is_ioport(void __iomem *address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #endif /* CONFIG_PCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #endif /* __KERNEL__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #endif /* _ASM_POWERPC_PCI_BRIDGE_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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