^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * PowerNV OPAL definitions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2011 IBM Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef _ASM_POWERPC_OPAL_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define _ASM_POWERPC_OPAL_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/opal-api.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/notifier.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* We calculate number of sg entries based on PAGE_SIZE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SG_ENTRIES_PER_NODE ((PAGE_SIZE - 16) / sizeof(struct opal_sg_entry))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* Default time to sleep or delay between OPAL_BUSY/OPAL_BUSY_EVENT loops */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define OPAL_BUSY_DELAY_MS 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* /sys/firmware/opal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) extern struct kobject *opal_kobj;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* /ibm,opal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) extern struct device_node *opal_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* API functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) int64_t opal_invalid_call(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) int64_t opal_npu_destroy_context(uint64_t phb_id, uint64_t pid, uint64_t bdf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) int64_t opal_npu_init_context(uint64_t phb_id, int pasid, uint64_t msr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) uint64_t bdf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) int64_t opal_npu_map_lpar(uint64_t phb_id, uint64_t bdf, uint64_t lparid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) uint64_t lpcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) int64_t opal_npu_spa_setup(uint64_t phb_id, uint32_t bdfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) uint64_t addr, uint64_t PE_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) int64_t opal_npu_spa_clear_cache(uint64_t phb_id, uint32_t bdfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) uint64_t PE_handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) int64_t opal_npu_tl_set(uint64_t phb_id, uint32_t bdfn, long cap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) uint64_t rate_phys, uint32_t size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) int64_t opal_console_write(int64_t term_number, __be64 *length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) const uint8_t *buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) int64_t opal_console_read(int64_t term_number, __be64 *length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) uint8_t *buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) int64_t opal_console_write_buffer_space(int64_t term_number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) __be64 *length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) int64_t opal_console_flush(int64_t term_number);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) int64_t opal_rtc_read(__be32 *year_month_day,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) __be64 *hour_minute_second_millisecond);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) int64_t opal_rtc_write(uint32_t year_month_day,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) uint64_t hour_minute_second_millisecond);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) int64_t opal_tpo_read(uint64_t token, __be32 *year_mon_day, __be32 *hour_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) int64_t opal_tpo_write(uint64_t token, uint32_t year_mon_day,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) uint32_t hour_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) int64_t opal_cec_power_down(uint64_t request);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) int64_t opal_cec_reboot(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) int64_t opal_cec_reboot2(uint32_t reboot_type, const char *diag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) int64_t opal_read_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) int64_t opal_write_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) int64_t opal_handle_interrupt(uint64_t isn, __be64 *outstanding_event_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) int64_t opal_poll_events(__be64 *outstanding_event_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) int64_t opal_pci_set_hub_tce_memory(uint64_t hub_id, uint64_t tce_mem_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) uint64_t tce_mem_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) int64_t opal_pci_set_phb_tce_memory(uint64_t phb_id, uint64_t tce_mem_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) uint64_t tce_mem_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) int64_t opal_pci_config_read_byte(uint64_t phb_id, uint64_t bus_dev_func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) uint64_t offset, uint8_t *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) int64_t opal_pci_config_read_half_word(uint64_t phb_id, uint64_t bus_dev_func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) uint64_t offset, __be16 *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) int64_t opal_pci_config_read_word(uint64_t phb_id, uint64_t bus_dev_func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) uint64_t offset, __be32 *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) int64_t opal_pci_config_write_byte(uint64_t phb_id, uint64_t bus_dev_func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) uint64_t offset, uint8_t data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) int64_t opal_pci_config_write_half_word(uint64_t phb_id, uint64_t bus_dev_func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) uint64_t offset, uint16_t data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) int64_t opal_pci_config_write_word(uint64_t phb_id, uint64_t bus_dev_func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) uint64_t offset, uint32_t data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) int64_t opal_set_xive(uint32_t isn, uint16_t server, uint8_t priority);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) int64_t opal_get_xive(uint32_t isn, __be16 *server, uint8_t *priority);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) int64_t opal_register_exception_handler(uint64_t opal_exception,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) uint64_t handler_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) uint64_t glue_cache_line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) int64_t opal_pci_eeh_freeze_status(uint64_t phb_id, uint64_t pe_number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) uint8_t *freeze_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) __be16 *pci_error_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) __be64 *phb_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) int64_t opal_pci_eeh_freeze_clear(uint64_t phb_id, uint64_t pe_number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) uint64_t eeh_action_token);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) int64_t opal_pci_eeh_freeze_set(uint64_t phb_id, uint64_t pe_number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) uint64_t eeh_action_token);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) int64_t opal_pci_err_inject(uint64_t phb_id, uint32_t pe_no, uint32_t type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) uint32_t func, uint64_t addr, uint64_t mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) int64_t opal_pci_shpc(uint64_t phb_id, uint64_t shpc_action, uint8_t *state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) int64_t opal_pci_phb_mmio_enable(uint64_t phb_id, uint16_t window_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) uint16_t window_num, uint16_t enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) int64_t opal_pci_set_phb_mem_window(uint64_t phb_id, uint16_t window_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) uint16_t window_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) uint64_t starting_real_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) uint64_t starting_pci_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) uint64_t size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) int64_t opal_pci_map_pe_mmio_window(uint64_t phb_id, uint16_t pe_number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) uint16_t window_type, uint16_t window_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) uint16_t segment_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) int64_t opal_pci_set_phb_table_memory(uint64_t phb_id, uint64_t rtt_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) uint64_t ivt_addr, uint64_t ivt_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) uint64_t reject_array_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) uint64_t peltv_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) int64_t opal_pci_set_pe(uint64_t phb_id, uint64_t pe_number, uint64_t bus_dev_func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) uint8_t bus_compare, uint8_t dev_compare, uint8_t func_compare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) uint8_t pe_action);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) int64_t opal_pci_set_peltv(uint64_t phb_id, uint32_t parent_pe, uint32_t child_pe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) uint8_t state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) int64_t opal_pci_set_mve(uint64_t phb_id, uint32_t mve_number, uint32_t pe_number);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) int64_t opal_pci_set_mve_enable(uint64_t phb_id, uint32_t mve_number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) uint32_t state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) int64_t opal_pci_get_xive_reissue(uint64_t phb_id, uint32_t xive_number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) uint8_t *p_bit, uint8_t *q_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) int64_t opal_pci_set_xive_reissue(uint64_t phb_id, uint32_t xive_number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) uint8_t p_bit, uint8_t q_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) int64_t opal_pci_msi_eoi(uint64_t phb_id, uint32_t hw_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) int64_t opal_pci_set_xive_pe(uint64_t phb_id, uint32_t pe_number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) uint32_t xive_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) int64_t opal_get_xive_source(uint64_t phb_id, uint32_t xive_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) __be32 *interrupt_source_number);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) int64_t opal_get_msi_32(uint64_t phb_id, uint32_t mve_number, uint32_t xive_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) uint8_t msi_range, __be32 *msi_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) __be32 *message_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) int64_t opal_get_msi_64(uint64_t phb_id, uint32_t mve_number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) uint32_t xive_num, uint8_t msi_range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) __be64 *msi_address, __be32 *message_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) int64_t opal_start_cpu(uint64_t thread_number, uint64_t start_address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) int64_t opal_query_cpu_status(uint64_t thread_number, uint8_t *thread_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) int64_t opal_write_oppanel(oppanel_line_t *lines, uint64_t num_lines);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) int64_t opal_pci_map_pe_dma_window(uint64_t phb_id, uint16_t pe_number, uint16_t window_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) uint16_t tce_levels, uint64_t tce_table_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) uint64_t tce_table_size, uint64_t tce_page_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) int64_t opal_pci_map_pe_dma_window_real(uint64_t phb_id, uint16_t pe_number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) uint16_t dma_window_number, uint64_t pci_start_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) uint64_t pci_mem_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) int64_t opal_pci_reset(uint64_t id, uint8_t reset_scope, uint8_t assert_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) int64_t opal_pci_get_hub_diag_data(uint64_t hub_id, void *diag_buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) uint64_t diag_buffer_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) int64_t opal_pci_get_phb_diag_data(uint64_t phb_id, void *diag_buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) uint64_t diag_buffer_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) int64_t opal_pci_get_phb_diag_data2(uint64_t phb_id, void *diag_buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) uint64_t diag_buffer_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) int64_t opal_pci_fence_phb(uint64_t phb_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) int64_t opal_pci_reinit(uint64_t phb_id, uint64_t reinit_scope, uint64_t data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) int64_t opal_pci_mask_pe_error(uint64_t phb_id, uint16_t pe_number, uint8_t error_type, uint8_t mask_action);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) int64_t opal_set_slot_led_status(uint64_t phb_id, uint64_t slot_id, uint8_t led_type, uint8_t led_action);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) int64_t opal_get_epow_status(__be16 *epow_status, __be16 *num_epow_classes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) int64_t opal_get_dpo_status(__be64 *dpo_timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) int64_t opal_set_system_attention_led(uint8_t led_action);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) int64_t opal_pci_next_error(uint64_t phb_id, __be64 *first_frozen_pe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) __be16 *pci_error_type, __be16 *severity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) int64_t opal_pci_poll(uint64_t id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) int64_t opal_return_cpu(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) int64_t opal_check_token(uint64_t token);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) int64_t opal_reinit_cpus(uint64_t flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) int64_t opal_xscom_read(uint32_t gcid, uint64_t pcb_addr, __be64 *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) int64_t opal_xscom_write(uint32_t gcid, uint64_t pcb_addr, uint64_t val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) int64_t opal_lpc_write(uint32_t chip_id, enum OpalLPCAddressType addr_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) uint32_t addr, uint32_t data, uint32_t sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) int64_t opal_lpc_read(uint32_t chip_id, enum OpalLPCAddressType addr_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) uint32_t addr, __be32 *data, uint32_t sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) int64_t opal_read_elog(uint64_t buffer, uint64_t size, uint64_t log_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) int64_t opal_get_elog_size(__be64 *log_id, __be64 *size, __be64 *elog_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) int64_t opal_write_elog(uint64_t buffer, uint64_t size, uint64_t offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) int64_t opal_send_ack_elog(uint64_t log_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) void opal_resend_pending_logs(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) int64_t opal_validate_flash(uint64_t buffer, uint32_t *size, uint32_t *result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) int64_t opal_manage_flash(uint8_t op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) int64_t opal_update_flash(uint64_t blk_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) int64_t opal_dump_init(uint8_t dump_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) int64_t opal_dump_info(__be32 *dump_id, __be32 *dump_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) int64_t opal_dump_info2(__be32 *dump_id, __be32 *dump_size, __be32 *dump_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) int64_t opal_dump_read(uint32_t dump_id, uint64_t buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) int64_t opal_dump_ack(uint32_t dump_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) int64_t opal_dump_resend_notification(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) int64_t opal_get_msg(uint64_t buffer, uint64_t size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) int64_t opal_write_oppanel_async(uint64_t token, oppanel_line_t *lines,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) uint64_t num_lines);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) int64_t opal_check_completion(uint64_t buffer, uint64_t size, uint64_t token);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) int64_t opal_sync_host_reboot(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) int64_t opal_get_param(uint64_t token, uint32_t param_id, uint64_t buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) uint64_t length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) int64_t opal_set_param(uint64_t token, uint32_t param_id, uint64_t buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) uint64_t length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) int64_t opal_sensor_read(uint32_t sensor_hndl, int token, __be32 *sensor_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) int64_t opal_sensor_read_u64(u32 sensor_hndl, int token, __be64 *sensor_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) int64_t opal_handle_hmi(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) int64_t opal_handle_hmi2(__be64 *out_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) int64_t opal_register_dump_region(uint32_t id, uint64_t start, uint64_t end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) int64_t opal_unregister_dump_region(uint32_t id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) int64_t opal_slw_set_reg(uint64_t cpu_pir, uint64_t sprn, uint64_t val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) int64_t opal_config_cpu_idle_state(uint64_t state, uint64_t flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) int64_t opal_pci_set_phb_cxl_mode(uint64_t phb_id, uint64_t mode, uint64_t pe_number);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) int64_t opal_pci_get_pbcq_tunnel_bar(uint64_t phb_id, uint64_t *addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) int64_t opal_pci_set_pbcq_tunnel_bar(uint64_t phb_id, uint64_t addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) int64_t opal_ipmi_send(uint64_t interface, struct opal_ipmi_msg *msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) uint64_t msg_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) int64_t opal_ipmi_recv(uint64_t interface, struct opal_ipmi_msg *msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) uint64_t *msg_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) int64_t opal_i2c_request(uint64_t async_token, uint32_t bus_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct opal_i2c_request *oreq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) int64_t opal_prd_msg(struct opal_prd_msg *msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) int64_t opal_leds_get_ind(char *loc_code, __be64 *led_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) __be64 *led_value, __be64 *max_led_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) int64_t opal_leds_set_ind(uint64_t token, char *loc_code, const u64 led_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) const u64 led_value, __be64 *max_led_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) int64_t opal_flash_read(uint64_t id, uint64_t offset, uint64_t buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) uint64_t size, uint64_t token);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) int64_t opal_flash_write(uint64_t id, uint64_t offset, uint64_t buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) uint64_t size, uint64_t token);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) int64_t opal_flash_erase(uint64_t id, uint64_t offset, uint64_t size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) uint64_t token);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) int64_t opal_get_device_tree(uint32_t phandle, uint64_t buf, uint64_t len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) int64_t opal_pci_get_presence_state(uint64_t id, uint64_t data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) int64_t opal_pci_get_power_state(uint64_t id, uint64_t data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) int64_t opal_pci_set_power_state(uint64_t async_token, uint64_t id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) uint64_t data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) int64_t opal_pci_poll2(uint64_t id, uint64_t data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) int64_t opal_int_get_xirr(uint32_t *out_xirr, bool just_poll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) int64_t opal_int_set_cppr(uint8_t cppr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) int64_t opal_int_eoi(uint32_t xirr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) int64_t opal_int_set_mfrr(uint32_t cpu, uint8_t mfrr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) int64_t opal_pci_tce_kill(uint64_t phb_id, uint32_t kill_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) uint32_t pe_num, uint32_t tce_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) uint64_t dma_addr, uint32_t npages);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) int64_t opal_nmmu_set_ptcr(uint64_t chip_id, uint64_t ptcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) int64_t opal_xive_reset(uint64_t version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) int64_t opal_xive_get_irq_info(uint32_t girq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) __be64 *out_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) __be64 *out_eoi_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) __be64 *out_trig_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) __be32 *out_esb_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) __be32 *out_src_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) int64_t opal_xive_get_irq_config(uint32_t girq, __be64 *out_vp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) uint8_t *out_prio, __be32 *out_lirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) int64_t opal_xive_set_irq_config(uint32_t girq, uint64_t vp, uint8_t prio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) uint32_t lirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) int64_t opal_xive_get_queue_info(uint64_t vp, uint32_t prio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) __be64 *out_qpage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) __be64 *out_qsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) __be64 *out_qeoi_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) __be32 *out_escalate_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) __be64 *out_qflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) int64_t opal_xive_set_queue_info(uint64_t vp, uint32_t prio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) uint64_t qpage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) uint64_t qsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) uint64_t qflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) int64_t opal_xive_donate_page(uint32_t chip_id, uint64_t addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) int64_t opal_xive_alloc_vp_block(uint32_t alloc_order);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) int64_t opal_xive_free_vp_block(uint64_t vp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) int64_t opal_xive_get_vp_info(uint64_t vp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) __be64 *out_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) __be64 *out_cam_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) __be64 *out_report_cl_pair,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) __be32 *out_chip_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) int64_t opal_xive_set_vp_info(uint64_t vp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) uint64_t flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) uint64_t report_cl_pair);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) int64_t opal_xive_allocate_irq_raw(uint32_t chip_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) int64_t opal_xive_free_irq(uint32_t girq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) int64_t opal_xive_sync(uint32_t type, uint32_t id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) int64_t opal_xive_dump(uint32_t type, uint32_t id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) int64_t opal_xive_get_queue_state(uint64_t vp, uint32_t prio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) __be32 *out_qtoggle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) __be32 *out_qindex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) int64_t opal_xive_set_queue_state(uint64_t vp, uint32_t prio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) uint32_t qtoggle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) uint32_t qindex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) int64_t opal_xive_get_vp_state(uint64_t vp, __be64 *out_w01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) int64_t opal_imc_counters_init(uint32_t type, uint64_t address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) uint64_t cpu_pir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) int64_t opal_imc_counters_start(uint32_t type, uint64_t cpu_pir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) int64_t opal_imc_counters_stop(uint32_t type, uint64_t cpu_pir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) int opal_get_powercap(u32 handle, int token, u32 *pcap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) int opal_set_powercap(u32 handle, int token, u32 pcap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) int opal_get_power_shift_ratio(u32 handle, int token, u32 *psr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) int opal_set_power_shift_ratio(u32 handle, int token, u32 psr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) int opal_sensor_group_clear(u32 group_hndl, int token);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) int opal_sensor_group_enable(u32 group_hndl, int token, bool enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) int opal_nx_coproc_init(uint32_t chip_id, uint32_t ct);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) int opal_secvar_get(const char *key, uint64_t key_len, u8 *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) uint64_t *data_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) int opal_secvar_get_next(const char *key, uint64_t *key_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) uint64_t key_buf_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) int opal_secvar_enqueue_update(const char *key, uint64_t key_len, u8 *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) uint64_t data_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) s64 opal_mpipl_update(enum opal_mpipl_ops op, u64 src, u64 dest, u64 size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) s64 opal_mpipl_register_tag(enum opal_mpipl_tags tag, u64 addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) s64 opal_mpipl_query_tag(enum opal_mpipl_tags tag, u64 *addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) s64 opal_signal_system_reset(s32 cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) s64 opal_quiesce(u64 shutdown_type, s32 cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /* Internal functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) extern int early_init_dt_scan_opal(unsigned long node, const char *uname,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) int depth, void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) extern int early_init_dt_scan_recoverable_ranges(unsigned long node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) const char *uname, int depth, void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) extern void opal_configure_cores(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) extern int opal_get_chars(uint32_t vtermno, char *buf, int count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) extern int opal_put_chars(uint32_t vtermno, const char *buf, int total_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) extern int opal_put_chars_atomic(uint32_t vtermno, const char *buf, int total_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) extern int opal_flush_chars(uint32_t vtermno, bool wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) extern int opal_flush_console(uint32_t vtermno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) extern void hvc_opal_init_early(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) extern int opal_notifier_register(struct notifier_block *nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) extern int opal_notifier_unregister(struct notifier_block *nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) extern int opal_message_notifier_register(enum opal_msg_type msg_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) struct notifier_block *nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) extern int opal_message_notifier_unregister(enum opal_msg_type msg_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) struct notifier_block *nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) extern void opal_notifier_enable(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) extern void opal_notifier_disable(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) extern void opal_notifier_update_evt(uint64_t evt_mask, uint64_t evt_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) extern int opal_async_get_token_interruptible(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) extern int opal_async_release_token(int token);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) extern int opal_async_wait_response(uint64_t token, struct opal_msg *msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) extern int opal_async_wait_response_interruptible(uint64_t token,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) struct opal_msg *msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) extern int opal_get_sensor_data(u32 sensor_hndl, u32 *sensor_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) extern int opal_get_sensor_data_u64(u32 sensor_hndl, u64 *sensor_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) extern int sensor_group_enable(u32 grp_hndl, bool enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) struct rtc_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) extern time64_t opal_get_boot_time(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) extern void opal_nvram_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) extern void opal_flash_update_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) extern void opal_flash_update_print_message(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) extern int opal_elog_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) extern void opal_platform_dump_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) extern void opal_sys_param_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) extern void opal_msglog_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) extern void opal_msglog_sysfs_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) extern int opal_async_comp_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) extern int opal_sensor_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) extern int opal_hmi_handler_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) extern int opal_event_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) int opal_power_control_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) extern int opal_machine_check(struct pt_regs *regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) extern bool opal_mce_check_early_recovery(struct pt_regs *regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) extern int opal_hmi_exception_early(struct pt_regs *regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) extern int opal_hmi_exception_early2(struct pt_regs *regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) extern int opal_handle_hmi_exception(struct pt_regs *regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) extern void opal_shutdown(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) extern int opal_resync_timebase(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) extern void opal_lpc_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) extern void opal_kmsg_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) extern int opal_event_request(unsigned int opal_event_nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) struct opal_sg_list *opal_vmalloc_to_sg_list(void *vmalloc_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) unsigned long vmalloc_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) void opal_free_sg_list(struct opal_sg_list *sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) extern int opal_error_code(int rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) ssize_t opal_msglog_copy(char *to, loff_t pos, size_t count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static inline int opal_get_async_rc(struct opal_msg msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (msg.msg_type != OPAL_MSG_ASYNC_COMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) return OPAL_PARAMETER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return be64_to_cpu(msg.params[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) void opal_wake_poller(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) void opal_powercap_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) void opal_psr_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) void opal_sensor_groups_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #endif /* __ASSEMBLY__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #endif /* _ASM_POWERPC_OPAL_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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