^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * OPAL API definitions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2011-2015 IBM Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef __OPAL_API_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define __OPAL_API_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /****** OPAL APIs ******/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /* Return codes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define OPAL_SUCCESS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define OPAL_PARAMETER -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define OPAL_BUSY -2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define OPAL_PARTIAL -3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define OPAL_CONSTRAINED -4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define OPAL_CLOSED -5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define OPAL_HARDWARE -6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define OPAL_UNSUPPORTED -7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define OPAL_PERMISSION -8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define OPAL_NO_MEM -9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define OPAL_RESOURCE -10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define OPAL_INTERNAL_ERROR -11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define OPAL_BUSY_EVENT -12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define OPAL_HARDWARE_FROZEN -13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define OPAL_WRONG_STATE -14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define OPAL_ASYNC_COMPLETION -15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define OPAL_EMPTY -16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define OPAL_I2C_TIMEOUT -17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define OPAL_I2C_INVALID_CMD -18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define OPAL_I2C_LBUS_PARITY -19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define OPAL_I2C_BKEND_OVERRUN -20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define OPAL_I2C_BKEND_ACCESS -21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define OPAL_I2C_ARBT_LOST -22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define OPAL_I2C_NACK_RCVD -23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define OPAL_I2C_STOP_ERR -24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define OPAL_XIVE_PROVISIONING -31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define OPAL_XIVE_FREE_ACTIVE -32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define OPAL_TIMEOUT -33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* API Tokens (in r0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define OPAL_INVALID_CALL -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define OPAL_TEST 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define OPAL_CONSOLE_WRITE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define OPAL_CONSOLE_READ 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define OPAL_RTC_READ 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define OPAL_RTC_WRITE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define OPAL_CEC_POWER_DOWN 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define OPAL_CEC_REBOOT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define OPAL_READ_NVRAM 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define OPAL_WRITE_NVRAM 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define OPAL_HANDLE_INTERRUPT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define OPAL_POLL_EVENTS 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define OPAL_PCI_SET_HUB_TCE_MEMORY 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define OPAL_PCI_SET_PHB_TCE_MEMORY 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define OPAL_PCI_CONFIG_READ_BYTE 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define OPAL_PCI_CONFIG_READ_HALF_WORD 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define OPAL_PCI_CONFIG_READ_WORD 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define OPAL_PCI_CONFIG_WRITE_BYTE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define OPAL_PCI_CONFIG_WRITE_HALF_WORD 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define OPAL_PCI_CONFIG_WRITE_WORD 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define OPAL_SET_XIVE 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define OPAL_GET_XIVE 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define OPAL_GET_COMPLETION_TOKEN_STATUS 21 /* obsolete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define OPAL_REGISTER_OPAL_EXCEPTION_HANDLER 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define OPAL_PCI_EEH_FREEZE_STATUS 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define OPAL_PCI_SHPC 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define OPAL_CONSOLE_WRITE_BUFFER_SPACE 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define OPAL_PCI_EEH_FREEZE_CLEAR 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define OPAL_PCI_PHB_MMIO_ENABLE 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define OPAL_PCI_SET_PHB_MEM_WINDOW 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define OPAL_PCI_MAP_PE_MMIO_WINDOW 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define OPAL_PCI_SET_PHB_TABLE_MEMORY 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define OPAL_PCI_SET_PE 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define OPAL_PCI_SET_PELTV 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define OPAL_PCI_SET_MVE 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define OPAL_PCI_SET_MVE_ENABLE 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define OPAL_PCI_GET_XIVE_REISSUE 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define OPAL_PCI_SET_XIVE_REISSUE 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define OPAL_PCI_SET_XIVE_PE 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define OPAL_GET_XIVE_SOURCE 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define OPAL_GET_MSI_32 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define OPAL_GET_MSI_64 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define OPAL_START_CPU 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define OPAL_QUERY_CPU_STATUS 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define OPAL_WRITE_OPPANEL 43 /* unimplemented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define OPAL_PCI_MAP_PE_DMA_WINDOW 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define OPAL_PCI_MAP_PE_DMA_WINDOW_REAL 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define OPAL_PCI_RESET 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define OPAL_PCI_GET_HUB_DIAG_DATA 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define OPAL_PCI_GET_PHB_DIAG_DATA 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define OPAL_PCI_FENCE_PHB 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define OPAL_PCI_REINIT 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define OPAL_PCI_MASK_PE_ERROR 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define OPAL_SET_SLOT_LED_STATUS 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define OPAL_GET_EPOW_STATUS 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define OPAL_SET_SYSTEM_ATTENTION_LED 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define OPAL_RESERVED1 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define OPAL_RESERVED2 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define OPAL_PCI_NEXT_ERROR 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define OPAL_PCI_EEH_FREEZE_STATUS2 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define OPAL_PCI_POLL 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define OPAL_PCI_MSI_EOI 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define OPAL_PCI_GET_PHB_DIAG_DATA2 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define OPAL_XSCOM_READ 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define OPAL_XSCOM_WRITE 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define OPAL_LPC_READ 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define OPAL_LPC_WRITE 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define OPAL_RETURN_CPU 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define OPAL_REINIT_CPUS 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define OPAL_ELOG_READ 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define OPAL_ELOG_WRITE 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define OPAL_ELOG_ACK 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define OPAL_ELOG_RESEND 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define OPAL_ELOG_SIZE 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define OPAL_FLASH_VALIDATE 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define OPAL_FLASH_MANAGE 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define OPAL_FLASH_UPDATE 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define OPAL_RESYNC_TIMEBASE 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define OPAL_CHECK_TOKEN 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define OPAL_DUMP_INIT 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define OPAL_DUMP_INFO 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define OPAL_DUMP_READ 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define OPAL_DUMP_ACK 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define OPAL_GET_MSG 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define OPAL_CHECK_ASYNC_COMPLETION 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define OPAL_SYNC_HOST_REBOOT 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define OPAL_SENSOR_READ 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define OPAL_GET_PARAM 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define OPAL_SET_PARAM 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define OPAL_DUMP_RESEND 91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define OPAL_ELOG_SEND 92 /* Deprecated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define OPAL_PCI_SET_PHB_CAPI_MODE 93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define OPAL_DUMP_INFO2 94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define OPAL_WRITE_OPPANEL_ASYNC 95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define OPAL_PCI_ERR_INJECT 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define OPAL_PCI_EEH_FREEZE_SET 97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define OPAL_HANDLE_HMI 98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define OPAL_CONFIG_CPU_IDLE_STATE 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define OPAL_SLW_SET_REG 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define OPAL_REGISTER_DUMP_REGION 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define OPAL_UNREGISTER_DUMP_REGION 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define OPAL_WRITE_TPO 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define OPAL_READ_TPO 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define OPAL_GET_DPO_STATUS 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define OPAL_OLD_I2C_REQUEST 106 /* Deprecated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define OPAL_IPMI_SEND 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define OPAL_IPMI_RECV 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define OPAL_I2C_REQUEST 109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define OPAL_FLASH_READ 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define OPAL_FLASH_WRITE 111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define OPAL_FLASH_ERASE 112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define OPAL_PRD_MSG 113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define OPAL_LEDS_GET_INDICATOR 114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define OPAL_LEDS_SET_INDICATOR 115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define OPAL_CEC_REBOOT2 116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define OPAL_CONSOLE_FLUSH 117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define OPAL_GET_DEVICE_TREE 118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define OPAL_PCI_GET_PRESENCE_STATE 119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define OPAL_PCI_GET_POWER_STATE 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define OPAL_PCI_SET_POWER_STATE 121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define OPAL_INT_GET_XIRR 122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define OPAL_INT_SET_CPPR 123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define OPAL_INT_EOI 124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define OPAL_INT_SET_MFRR 125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define OPAL_PCI_TCE_KILL 126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define OPAL_NMMU_SET_PTCR 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define OPAL_XIVE_RESET 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define OPAL_XIVE_GET_IRQ_INFO 129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define OPAL_XIVE_GET_IRQ_CONFIG 130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define OPAL_XIVE_SET_IRQ_CONFIG 131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define OPAL_XIVE_GET_QUEUE_INFO 132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define OPAL_XIVE_SET_QUEUE_INFO 133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define OPAL_XIVE_DONATE_PAGE 134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define OPAL_XIVE_ALLOCATE_VP_BLOCK 135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define OPAL_XIVE_FREE_VP_BLOCK 136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define OPAL_XIVE_GET_VP_INFO 137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define OPAL_XIVE_SET_VP_INFO 138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define OPAL_XIVE_ALLOCATE_IRQ 139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define OPAL_XIVE_FREE_IRQ 140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define OPAL_XIVE_SYNC 141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define OPAL_XIVE_DUMP 142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define OPAL_XIVE_GET_QUEUE_STATE 143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define OPAL_XIVE_SET_QUEUE_STATE 144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define OPAL_SIGNAL_SYSTEM_RESET 145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define OPAL_NPU_INIT_CONTEXT 146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define OPAL_NPU_DESTROY_CONTEXT 147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define OPAL_NPU_MAP_LPAR 148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define OPAL_IMC_COUNTERS_INIT 149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define OPAL_IMC_COUNTERS_START 150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define OPAL_IMC_COUNTERS_STOP 151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define OPAL_GET_POWERCAP 152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define OPAL_SET_POWERCAP 153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define OPAL_GET_POWER_SHIFT_RATIO 154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define OPAL_SET_POWER_SHIFT_RATIO 155
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define OPAL_SENSOR_GROUP_CLEAR 156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define OPAL_PCI_SET_P2P 157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define OPAL_QUIESCE 158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define OPAL_NPU_SPA_SETUP 159
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define OPAL_NPU_SPA_CLEAR_CACHE 160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define OPAL_NPU_TL_SET 161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define OPAL_SENSOR_READ_U64 162
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define OPAL_SENSOR_GROUP_ENABLE 163
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define OPAL_PCI_GET_PBCQ_TUNNEL_BAR 164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define OPAL_PCI_SET_PBCQ_TUNNEL_BAR 165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define OPAL_HANDLE_HMI2 166
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define OPAL_NX_COPROC_INIT 167
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define OPAL_XIVE_GET_VP_STATE 170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define OPAL_MPIPL_UPDATE 173
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define OPAL_MPIPL_REGISTER_TAG 174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define OPAL_MPIPL_QUERY_TAG 175
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define OPAL_SECVAR_GET 176
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define OPAL_SECVAR_GET_NEXT 177
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define OPAL_SECVAR_ENQUEUE_UPDATE 178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define OPAL_LAST 178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define QUIESCE_HOLD 1 /* Spin all calls at entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define QUIESCE_REJECT 2 /* Fail all calls with OPAL_BUSY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define QUIESCE_LOCK_BREAK 3 /* Set to ignore locks. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define QUIESCE_RESUME 4 /* Un-quiesce */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define QUIESCE_RESUME_FAST_REBOOT 5 /* Un-quiesce, fast reboot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* Device tree flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * Flags set in power-mgmt nodes in device tree describing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * idle states that are supported in the platform.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define OPAL_PM_TIMEBASE_STOP 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define OPAL_PM_LOSE_HYP_CONTEXT 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define OPAL_PM_LOSE_FULL_CONTEXT 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define OPAL_PM_NAP_ENABLED 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define OPAL_PM_SLEEP_ENABLED 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define OPAL_PM_WINKLE_ENABLED 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define OPAL_PM_SLEEP_ENABLED_ER1 0x00080000 /* with workaround */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define OPAL_PM_STOP_INST_FAST 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define OPAL_PM_STOP_INST_DEEP 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * OPAL_CONFIG_CPU_IDLE_STATE parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define OPAL_CONFIG_IDLE_FASTSLEEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define OPAL_CONFIG_IDLE_UNDO 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define OPAL_CONFIG_IDLE_APPLY 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* Other enums */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) enum OpalFreezeState {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) OPAL_EEH_STOPPED_NOT_FROZEN = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) OPAL_EEH_STOPPED_MMIO_FREEZE = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) OPAL_EEH_STOPPED_DMA_FREEZE = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) OPAL_EEH_STOPPED_MMIO_DMA_FREEZE = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) OPAL_EEH_STOPPED_RESET = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) OPAL_EEH_STOPPED_TEMP_UNAVAIL = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) OPAL_EEH_STOPPED_PERM_UNAVAIL = 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) enum OpalEehFreezeActionToken {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) OPAL_EEH_ACTION_CLEAR_FREEZE_DMA = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) OPAL_EEH_ACTION_CLEAR_FREEZE_ALL = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) OPAL_EEH_ACTION_SET_FREEZE_MMIO = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) OPAL_EEH_ACTION_SET_FREEZE_DMA = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) OPAL_EEH_ACTION_SET_FREEZE_ALL = 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) enum OpalPciStatusToken {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) OPAL_EEH_NO_ERROR = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) OPAL_EEH_IOC_ERROR = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) OPAL_EEH_PHB_ERROR = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) OPAL_EEH_PE_ERROR = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) OPAL_EEH_PE_MMIO_ERROR = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) OPAL_EEH_PE_DMA_ERROR = 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) enum OpalPciErrorSeverity {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) OPAL_EEH_SEV_NO_ERROR = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) OPAL_EEH_SEV_IOC_DEAD = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) OPAL_EEH_SEV_PHB_DEAD = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) OPAL_EEH_SEV_PHB_FENCED = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) OPAL_EEH_SEV_PE_ER = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) OPAL_EEH_SEV_INF = 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) enum OpalErrinjectType {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) enum OpalErrinjectFunc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* IOA bus specific errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_ADDR = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_DATA = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) OPAL_ERR_INJECT_FUNC_IOA_LD_IO_ADDR = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) OPAL_ERR_INJECT_FUNC_IOA_LD_IO_DATA = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) OPAL_ERR_INJECT_FUNC_IOA_LD_CFG_ADDR = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) OPAL_ERR_INJECT_FUNC_IOA_LD_CFG_DATA = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) OPAL_ERR_INJECT_FUNC_IOA_ST_MEM_ADDR = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) OPAL_ERR_INJECT_FUNC_IOA_ST_MEM_DATA = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) OPAL_ERR_INJECT_FUNC_IOA_ST_IO_ADDR = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) OPAL_ERR_INJECT_FUNC_IOA_ST_IO_DATA = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) OPAL_ERR_INJECT_FUNC_IOA_ST_CFG_ADDR = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) OPAL_ERR_INJECT_FUNC_IOA_ST_CFG_DATA = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_ADDR = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_DATA = 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_MASTER = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_TARGET = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_ADDR = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_DATA = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_MASTER = 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_TARGET = 19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) enum OpalMmioWindowType {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) OPAL_M32_WINDOW_TYPE = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) OPAL_M64_WINDOW_TYPE = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) OPAL_IO_WINDOW_TYPE = 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) enum OpalExceptionHandler {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) OPAL_MACHINE_CHECK_HANDLER = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) OPAL_HYPERVISOR_MAINTENANCE_HANDLER = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) OPAL_SOFTPATCH_HANDLER = 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) enum OpalPendingState {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) OPAL_EVENT_OPAL_INTERNAL = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) OPAL_EVENT_NVRAM = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) OPAL_EVENT_RTC = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) OPAL_EVENT_CONSOLE_OUTPUT = 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) OPAL_EVENT_CONSOLE_INPUT = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) OPAL_EVENT_ERROR_LOG_AVAIL = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) OPAL_EVENT_ERROR_LOG = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) OPAL_EVENT_EPOW = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) OPAL_EVENT_LED_STATUS = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) OPAL_EVENT_PCI_ERROR = 0x200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) OPAL_EVENT_DUMP_AVAIL = 0x400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) OPAL_EVENT_MSG_PENDING = 0x800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) enum OpalThreadStatus {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) OPAL_THREAD_INACTIVE = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) OPAL_THREAD_STARTED = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) OPAL_THREAD_UNAVAILABLE = 0x2 /* opal-v3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) enum OpalPciBusCompare {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) OpalPciBusAny = 0, /* Any bus number match */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) OpalPciBus3Bits = 2, /* Match top 3 bits of bus number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) OpalPciBus4Bits = 3, /* Match top 4 bits of bus number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) OpalPciBus5Bits = 4, /* Match top 5 bits of bus number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) OpalPciBus6Bits = 5, /* Match top 6 bits of bus number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) OpalPciBus7Bits = 6, /* Match top 7 bits of bus number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) OpalPciBusAll = 7, /* Match bus number exactly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) enum OpalDeviceCompare {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) OPAL_IGNORE_RID_DEVICE_NUMBER = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) OPAL_COMPARE_RID_DEVICE_NUMBER = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) enum OpalFuncCompare {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) OPAL_IGNORE_RID_FUNCTION_NUMBER = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) OPAL_COMPARE_RID_FUNCTION_NUMBER = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) enum OpalPeAction {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) OPAL_UNMAP_PE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) OPAL_MAP_PE = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) enum OpalPeltvAction {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) OPAL_REMOVE_PE_FROM_DOMAIN = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) OPAL_ADD_PE_TO_DOMAIN = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) enum OpalMveEnableAction {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) OPAL_DISABLE_MVE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) OPAL_ENABLE_MVE = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) enum OpalM64Action {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) OPAL_DISABLE_M64 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) OPAL_ENABLE_M64_SPLIT = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) OPAL_ENABLE_M64_NON_SPLIT = 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) enum OpalPciResetScope {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) OPAL_RESET_PHB_COMPLETE = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) OPAL_RESET_PCI_LINK = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) OPAL_RESET_PHB_ERROR = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) OPAL_RESET_PCI_HOT = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) OPAL_RESET_PCI_FUNDAMENTAL = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) OPAL_RESET_PCI_IODA_TABLE = 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) enum OpalPciReinitScope {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * Note: we chose values that do not overlap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) * OpalPciResetScope as OPAL v2 used the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * enum for both
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) OPAL_REINIT_PCI_DEV = 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) enum OpalPciResetState {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) OPAL_DEASSERT_RESET = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) OPAL_ASSERT_RESET = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) enum OpalPciSlotPresence {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) OPAL_PCI_SLOT_EMPTY = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) OPAL_PCI_SLOT_PRESENT = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) enum OpalPciSlotPower {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) OPAL_PCI_SLOT_POWER_OFF = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) OPAL_PCI_SLOT_POWER_ON = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) OPAL_PCI_SLOT_OFFLINE = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) OPAL_PCI_SLOT_ONLINE = 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) enum OpalSlotLedType {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) OPAL_SLOT_LED_TYPE_ID = 0, /* IDENTIFY LED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) OPAL_SLOT_LED_TYPE_FAULT = 1, /* FAULT LED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) OPAL_SLOT_LED_TYPE_ATTN = 2, /* System Attention LED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) OPAL_SLOT_LED_TYPE_MAX = 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) enum OpalSlotLedState {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) OPAL_SLOT_LED_STATE_OFF = 0, /* LED is OFF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) OPAL_SLOT_LED_STATE_ON = 1 /* LED is ON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * Address cycle types for LPC accesses. These also correspond
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) * to the content of the first cell of the "reg" property for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * device nodes on the LPC bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) enum OpalLPCAddressType {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) OPAL_LPC_MEM = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) OPAL_LPC_IO = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) OPAL_LPC_FW = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) enum opal_msg_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) OPAL_MSG_ASYNC_COMP = 0, /* params[0] = token, params[1] = rc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) * additional params function-specific
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) OPAL_MSG_MEM_ERR = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) OPAL_MSG_EPOW = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) OPAL_MSG_SHUTDOWN = 3, /* params[0] = 1 reboot, 0 shutdown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) OPAL_MSG_HMI_EVT = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) OPAL_MSG_DPO = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) OPAL_MSG_PRD = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) OPAL_MSG_OCC = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) OPAL_MSG_PRD2 = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) OPAL_MSG_TYPE_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) struct opal_msg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) __be32 msg_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) __be32 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) __be64 params[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /* System parameter permission */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) enum OpalSysparamPerm {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) OPAL_SYSPARAM_READ = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) OPAL_SYSPARAM_WRITE = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) OPAL_SYSPARAM_RW = (OPAL_SYSPARAM_READ | OPAL_SYSPARAM_WRITE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) OPAL_IPMI_MSG_FORMAT_VERSION_1 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) struct opal_ipmi_msg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) uint8_t version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) uint8_t netfn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) uint8_t cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) uint8_t data[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) /* FSP memory errors handling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) enum OpalMemErr_Version {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) OpalMemErr_V1 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) enum OpalMemErrType {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) OPAL_MEM_ERR_TYPE_RESILIENCE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) OPAL_MEM_ERR_TYPE_DYN_DALLOC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) /* Memory Reilience error type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) enum OpalMemErr_ResilErrType {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) OPAL_MEM_RESILIENCE_CE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) OPAL_MEM_RESILIENCE_UE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) OPAL_MEM_RESILIENCE_UE_SCRUB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) /* Dynamic Memory Deallocation type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) enum OpalMemErr_DynErrType {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) OPAL_MEM_DYNAMIC_DEALLOC = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) struct OpalMemoryErrorData {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) enum OpalMemErr_Version version:8; /* 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) enum OpalMemErrType type:8; /* 0x01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) __be16 flags; /* 0x02 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) uint8_t reserved_1[4]; /* 0x04 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) /* Memory Resilience corrected/uncorrected error info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) enum OpalMemErr_ResilErrType resil_err_type:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) uint8_t reserved_1[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) __be64 physical_address_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) __be64 physical_address_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) } resilience;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /* Dynamic memory deallocation error info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) enum OpalMemErr_DynErrType dyn_err_type:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) uint8_t reserved_1[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) __be64 physical_address_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) __be64 physical_address_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) } dyn_dealloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) } u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) /* HMI interrupt event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) enum OpalHMI_Version {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) OpalHMIEvt_V1 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) OpalHMIEvt_V2 = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) enum OpalHMI_Severity {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) OpalHMI_SEV_NO_ERROR = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) OpalHMI_SEV_WARNING = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) OpalHMI_SEV_ERROR_SYNC = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) OpalHMI_SEV_FATAL = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) enum OpalHMI_Disposition {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) OpalHMI_DISPOSITION_RECOVERED = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) OpalHMI_DISPOSITION_NOT_RECOVERED = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) enum OpalHMI_ErrType {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) OpalHMI_ERROR_MALFUNC_ALERT = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) OpalHMI_ERROR_PROC_RECOV_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) OpalHMI_ERROR_PROC_RECOV_DONE_AGAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) OpalHMI_ERROR_PROC_RECOV_MASKED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) OpalHMI_ERROR_TFAC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) OpalHMI_ERROR_TFMR_PARITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) OpalHMI_ERROR_HA_OVERFLOW_WARN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) OpalHMI_ERROR_XSCOM_FAIL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) OpalHMI_ERROR_XSCOM_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) OpalHMI_ERROR_SCOM_FIR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) OpalHMI_ERROR_DEBUG_TRIG_FIR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) OpalHMI_ERROR_HYP_RESOURCE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) OpalHMI_ERROR_CAPP_RECOVERY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) enum OpalHMI_XstopType {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) CHECKSTOP_TYPE_UNKNOWN = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) CHECKSTOP_TYPE_CORE = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) CHECKSTOP_TYPE_NX = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) CHECKSTOP_TYPE_NPU = 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) enum OpalHMI_CoreXstopReason {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) CORE_CHECKSTOP_IFU_REGFILE = 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) CORE_CHECKSTOP_IFU_LOGIC = 0x00000002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) CORE_CHECKSTOP_PC_DURING_RECOV = 0x00000004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) CORE_CHECKSTOP_ISU_REGFILE = 0x00000008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) CORE_CHECKSTOP_ISU_LOGIC = 0x00000010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) CORE_CHECKSTOP_FXU_LOGIC = 0x00000020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) CORE_CHECKSTOP_VSU_LOGIC = 0x00000040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) CORE_CHECKSTOP_PC_RECOV_IN_MAINT_MODE = 0x00000080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) CORE_CHECKSTOP_LSU_REGFILE = 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) CORE_CHECKSTOP_PC_FWD_PROGRESS = 0x00000200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) CORE_CHECKSTOP_LSU_LOGIC = 0x00000400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) CORE_CHECKSTOP_PC_LOGIC = 0x00000800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) CORE_CHECKSTOP_PC_HYP_RESOURCE = 0x00001000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) CORE_CHECKSTOP_PC_HANG_RECOV_FAILED = 0x00002000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) CORE_CHECKSTOP_PC_AMBI_HANG_DETECTED = 0x00004000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) CORE_CHECKSTOP_PC_DEBUG_TRIG_ERR_INJ = 0x00008000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) CORE_CHECKSTOP_PC_SPRD_HYP_ERR_INJ = 0x00010000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) enum OpalHMI_NestAccelXstopReason {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) NX_CHECKSTOP_SHM_INVAL_STATE_ERR = 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) NX_CHECKSTOP_DMA_INVAL_STATE_ERR_1 = 0x00000002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) NX_CHECKSTOP_DMA_INVAL_STATE_ERR_2 = 0x00000004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) NX_CHECKSTOP_DMA_CH0_INVAL_STATE_ERR = 0x00000008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) NX_CHECKSTOP_DMA_CH1_INVAL_STATE_ERR = 0x00000010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) NX_CHECKSTOP_DMA_CH2_INVAL_STATE_ERR = 0x00000020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) NX_CHECKSTOP_DMA_CH3_INVAL_STATE_ERR = 0x00000040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) NX_CHECKSTOP_DMA_CH4_INVAL_STATE_ERR = 0x00000080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) NX_CHECKSTOP_DMA_CH5_INVAL_STATE_ERR = 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) NX_CHECKSTOP_DMA_CH6_INVAL_STATE_ERR = 0x00000200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) NX_CHECKSTOP_DMA_CH7_INVAL_STATE_ERR = 0x00000400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) NX_CHECKSTOP_DMA_CRB_UE = 0x00000800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) NX_CHECKSTOP_DMA_CRB_SUE = 0x00001000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) NX_CHECKSTOP_PBI_ISN_UE = 0x00002000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) struct OpalHMIEvent {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) uint8_t version; /* 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) uint8_t severity; /* 0x01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) uint8_t type; /* 0x02 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) uint8_t disposition; /* 0x03 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) uint8_t reserved_1[4]; /* 0x04 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) __be64 hmer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) /* TFMR register. Valid only for TFAC and TFMR_PARITY error type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) __be64 tfmr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) /* version 2 and later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) * checkstop info (Core/NX).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) * Valid for OpalHMI_ERROR_MALFUNC_ALERT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) uint8_t xstop_type; /* enum OpalHMI_XstopType */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) uint8_t reserved_1[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) __be32 xstop_reason;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) __be32 pir; /* for CHECKSTOP_TYPE_CORE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) __be32 chip_id; /* for CHECKSTOP_TYPE_NX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) } u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) } xstop_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) } u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) /* OPAL_HANDLE_HMI2 out_flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) OPAL_HMI_FLAGS_TB_RESYNC = (1ull << 0), /* Timebase has been resynced */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) OPAL_HMI_FLAGS_DEC_LOST = (1ull << 1), /* DEC lost, needs to be reprogrammed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) OPAL_HMI_FLAGS_HDEC_LOST = (1ull << 2), /* HDEC lost, needs to be reprogrammed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) OPAL_HMI_FLAGS_TOD_TB_FAIL = (1ull << 3), /* TOD/TB recovery failed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) OPAL_HMI_FLAGS_NEW_EVENT = (1ull << 63), /* An event has been created */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) OPAL_P7IOC_DIAG_TYPE_NONE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) OPAL_P7IOC_DIAG_TYPE_RGC = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) OPAL_P7IOC_DIAG_TYPE_BI = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) OPAL_P7IOC_DIAG_TYPE_CI = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) OPAL_P7IOC_DIAG_TYPE_MISC = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) OPAL_P7IOC_DIAG_TYPE_I2C = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) OPAL_P7IOC_DIAG_TYPE_LAST = 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) struct OpalIoP7IOCErrorData {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) __be16 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) /* GEM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) __be64 gemXfir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) __be64 gemRfir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) __be64 gemRirqfir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) __be64 gemMask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) __be64 gemRwof;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) /* LEM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) __be64 lemFir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) __be64 lemErrMask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) __be64 lemAction0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) __be64 lemAction1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) __be64 lemWof;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) struct OpalIoP7IOCRgcErrorData {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) __be64 rgcStatus; /* 3E1C10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) __be64 rgcLdcp; /* 3E1C18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) }rgc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) struct OpalIoP7IOCBiErrorData {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) __be64 biLdcp0; /* 3C0100, 3C0118 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) __be64 biLdcp1; /* 3C0108, 3C0120 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) __be64 biLdcp2; /* 3C0110, 3C0128 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) __be64 biFenceStatus; /* 3C0130, 3C0130 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) uint8_t biDownbound; /* BI Downbound or Upbound */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) }bi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) struct OpalIoP7IOCCiErrorData {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) __be64 ciPortStatus; /* 3Dn008 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) __be64 ciPortLdcp; /* 3Dn010 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) uint8_t ciPort; /* Index of CI port: 0/1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) }ci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) * This structure defines the overlay which will be used to store PHB error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) * data upon request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) OPAL_PHB_ERROR_DATA_VERSION_1 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) OPAL_PHB_ERROR_DATA_TYPE_P7IOC = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) OPAL_PHB_ERROR_DATA_TYPE_PHB3 = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) OPAL_PHB_ERROR_DATA_TYPE_PHB4 = 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) OPAL_P7IOC_NUM_PEST_REGS = 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) OPAL_PHB3_NUM_PEST_REGS = 256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) OPAL_PHB4_NUM_PEST_REGS = 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) struct OpalIoPhbErrorCommon {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) __be32 version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) __be32 ioType;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) __be32 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) struct OpalIoP7IOCPhbErrorData {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) struct OpalIoPhbErrorCommon common;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) __be32 brdgCtl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) // P7IOC utl regs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) __be32 portStatusReg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) __be32 rootCmplxStatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) __be32 busAgentStatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) // P7IOC cfg regs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) __be32 deviceStatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) __be32 slotStatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) __be32 linkStatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) __be32 devCmdStatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) __be32 devSecStatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) // cfg AER regs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) __be32 rootErrorStatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) __be32 uncorrErrorStatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) __be32 corrErrorStatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) __be32 tlpHdr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) __be32 tlpHdr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) __be32 tlpHdr3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) __be32 tlpHdr4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) __be32 sourceId;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) __be32 rsv3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) // Record data about the call to allocate a buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) __be64 errorClass;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) __be64 correlator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) //P7IOC MMIO Error Regs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) __be64 p7iocPlssr; // n120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) __be64 p7iocCsr; // n110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) __be64 lemFir; // nC00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) __be64 lemErrorMask; // nC18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) __be64 lemWOF; // nC40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) __be64 phbErrorStatus; // nC80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) __be64 phbFirstErrorStatus; // nC88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) __be64 phbErrorLog0; // nCC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) __be64 phbErrorLog1; // nCC8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) __be64 mmioErrorStatus; // nD00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) __be64 mmioFirstErrorStatus; // nD08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) __be64 mmioErrorLog0; // nD40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) __be64 mmioErrorLog1; // nD48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) __be64 dma0ErrorStatus; // nD80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) __be64 dma0FirstErrorStatus; // nD88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) __be64 dma0ErrorLog0; // nDC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) __be64 dma0ErrorLog1; // nDC8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) __be64 dma1ErrorStatus; // nE00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) __be64 dma1FirstErrorStatus; // nE08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) __be64 dma1ErrorLog0; // nE40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) __be64 dma1ErrorLog1; // nE48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) __be64 pestA[OPAL_P7IOC_NUM_PEST_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) __be64 pestB[OPAL_P7IOC_NUM_PEST_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) struct OpalIoPhb3ErrorData {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) struct OpalIoPhbErrorCommon common;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) __be32 brdgCtl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) /* PHB3 UTL regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) __be32 portStatusReg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) __be32 rootCmplxStatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) __be32 busAgentStatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) /* PHB3 cfg regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) __be32 deviceStatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) __be32 slotStatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) __be32 linkStatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) __be32 devCmdStatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) __be32 devSecStatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) /* cfg AER regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) __be32 rootErrorStatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) __be32 uncorrErrorStatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) __be32 corrErrorStatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) __be32 tlpHdr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) __be32 tlpHdr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) __be32 tlpHdr3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) __be32 tlpHdr4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) __be32 sourceId;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) __be32 rsv3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) /* Record data about the call to allocate a buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) __be64 errorClass;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) __be64 correlator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) /* PHB3 MMIO Error Regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) __be64 nFir; /* 000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) __be64 nFirMask; /* 003 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) __be64 nFirWOF; /* 008 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) __be64 phbPlssr; /* 120 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) __be64 phbCsr; /* 110 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) __be64 lemFir; /* C00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) __be64 lemErrorMask; /* C18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) __be64 lemWOF; /* C40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) __be64 phbErrorStatus; /* C80 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) __be64 phbFirstErrorStatus; /* C88 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) __be64 phbErrorLog0; /* CC0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) __be64 phbErrorLog1; /* CC8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) __be64 mmioErrorStatus; /* D00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) __be64 mmioFirstErrorStatus; /* D08 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) __be64 mmioErrorLog0; /* D40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) __be64 mmioErrorLog1; /* D48 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) __be64 dma0ErrorStatus; /* D80 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) __be64 dma0FirstErrorStatus; /* D88 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) __be64 dma0ErrorLog0; /* DC0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) __be64 dma0ErrorLog1; /* DC8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) __be64 dma1ErrorStatus; /* E00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) __be64 dma1FirstErrorStatus; /* E08 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) __be64 dma1ErrorLog0; /* E40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) __be64 dma1ErrorLog1; /* E48 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) __be64 pestA[OPAL_PHB3_NUM_PEST_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) __be64 pestB[OPAL_PHB3_NUM_PEST_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) struct OpalIoPhb4ErrorData {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) struct OpalIoPhbErrorCommon common;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) __be32 brdgCtl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) /* PHB4 cfg regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) __be32 deviceStatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) __be32 slotStatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) __be32 linkStatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) __be32 devCmdStatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) __be32 devSecStatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) /* cfg AER regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) __be32 rootErrorStatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) __be32 uncorrErrorStatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) __be32 corrErrorStatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) __be32 tlpHdr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) __be32 tlpHdr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) __be32 tlpHdr3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) __be32 tlpHdr4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) __be32 sourceId;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) /* PHB4 ETU Error Regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) __be64 nFir; /* 000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) __be64 nFirMask; /* 003 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) __be64 nFirWOF; /* 008 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) __be64 phbPlssr; /* 120 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) __be64 phbCsr; /* 110 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) __be64 lemFir; /* C00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) __be64 lemErrorMask; /* C18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) __be64 lemWOF; /* C40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) __be64 phbErrorStatus; /* C80 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) __be64 phbFirstErrorStatus; /* C88 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) __be64 phbErrorLog0; /* CC0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) __be64 phbErrorLog1; /* CC8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) __be64 phbTxeErrorStatus; /* D00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) __be64 phbTxeFirstErrorStatus; /* D08 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) __be64 phbTxeErrorLog0; /* D40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) __be64 phbTxeErrorLog1; /* D48 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) __be64 phbRxeArbErrorStatus; /* D80 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) __be64 phbRxeArbFirstErrorStatus; /* D88 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) __be64 phbRxeArbErrorLog0; /* DC0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) __be64 phbRxeArbErrorLog1; /* DC8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) __be64 phbRxeMrgErrorStatus; /* E00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) __be64 phbRxeMrgFirstErrorStatus; /* E08 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) __be64 phbRxeMrgErrorLog0; /* E40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) __be64 phbRxeMrgErrorLog1; /* E48 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) __be64 phbRxeTceErrorStatus; /* E80 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) __be64 phbRxeTceFirstErrorStatus; /* E88 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) __be64 phbRxeTceErrorLog0; /* EC0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) __be64 phbRxeTceErrorLog1; /* EC8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) /* PHB4 REGB Error Regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) __be64 phbPblErrorStatus; /* 1900 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) __be64 phbPblFirstErrorStatus; /* 1908 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) __be64 phbPblErrorLog0; /* 1940 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) __be64 phbPblErrorLog1; /* 1948 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) __be64 phbPcieDlpErrorLog1; /* 1AA0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) __be64 phbPcieDlpErrorLog2; /* 1AA8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) __be64 phbPcieDlpErrorStatus; /* 1AB0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) __be64 phbRegbErrorStatus; /* 1C00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) __be64 phbRegbFirstErrorStatus; /* 1C08 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) __be64 phbRegbErrorLog0; /* 1C40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) __be64 phbRegbErrorLog1; /* 1C48 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) __be64 pestA[OPAL_PHB4_NUM_PEST_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) __be64 pestB[OPAL_PHB4_NUM_PEST_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) OPAL_REINIT_CPUS_HILE_BE = (1 << 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) OPAL_REINIT_CPUS_HILE_LE = (1 << 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) /* These two define the base MMU mode of the host on P9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) * On P9 Nimbus DD2.0 and Cumlus (and later), KVM can still
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) * create hash guests in "radix" mode with care (full core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) * switch only).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) OPAL_REINIT_CPUS_MMU_HASH = (1 << 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) OPAL_REINIT_CPUS_MMU_RADIX = (1 << 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) OPAL_REINIT_CPUS_TM_SUSPEND_DISABLED = (1 << 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) typedef struct oppanel_line {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) __be64 line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) __be64 line_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) } oppanel_line_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) enum opal_prd_msg_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) OPAL_PRD_MSG_TYPE_INIT = 0, /* HBRT --> OPAL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) OPAL_PRD_MSG_TYPE_FINI, /* HBRT/kernel --> OPAL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) OPAL_PRD_MSG_TYPE_ATTN, /* HBRT <-- OPAL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) OPAL_PRD_MSG_TYPE_ATTN_ACK, /* HBRT --> OPAL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) OPAL_PRD_MSG_TYPE_OCC_ERROR, /* HBRT <-- OPAL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) OPAL_PRD_MSG_TYPE_OCC_RESET, /* HBRT <-- OPAL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) struct opal_prd_msg_header {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) uint8_t type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) uint8_t pad[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) __be16 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) struct opal_prd_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) #define OCC_RESET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) #define OCC_LOAD 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) #define OCC_THROTTLE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) #define OCC_MAX_THROTTLE_STATUS 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) struct opal_occ_msg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) __be64 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) __be64 chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) __be64 throttle_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) * SG entries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) * WARNING: The current implementation requires each entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) * to represent a block that is 4k aligned *and* each block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) * size except the last one in the list to be as well.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) struct opal_sg_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) __be64 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) __be64 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) * Candidate image SG list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) * length = VER | length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) struct opal_sg_list {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) __be64 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) __be64 next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) struct opal_sg_entry entry[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) * Dump region ID range usable by the OS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) #define OPAL_DUMP_REGION_HOST_START 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) #define OPAL_DUMP_REGION_LOG_BUF 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) #define OPAL_DUMP_REGION_HOST_END 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) /* CAPI modes for PHB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) OPAL_PHB_CAPI_MODE_PCIE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) OPAL_PHB_CAPI_MODE_CAPI = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) OPAL_PHB_CAPI_MODE_SNOOP_OFF = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) OPAL_PHB_CAPI_MODE_SNOOP_ON = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) OPAL_PHB_CAPI_MODE_DMA = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) OPAL_PHB_CAPI_MODE_DMA_TVT1 = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) /* OPAL I2C request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) struct opal_i2c_request {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) uint8_t type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) #define OPAL_I2C_RAW_READ 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) #define OPAL_I2C_RAW_WRITE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) #define OPAL_I2C_SM_READ 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) #define OPAL_I2C_SM_WRITE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) uint8_t flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) #define OPAL_I2C_ADDR_10 0x01 /* Not supported yet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) uint8_t subaddr_sz; /* Max 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) uint8_t reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) __be16 addr; /* 7 or 10 bit address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) __be16 reserved2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) __be32 subaddr; /* Sub-address if any */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) __be32 size; /* Data size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) __be64 buffer_ra; /* Buffer real address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) * EPOW status sharing (OPAL and the host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) * The host will pass on OPAL, a buffer of length OPAL_SYSEPOW_MAX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) * with individual elements being 16 bits wide to fetch the system
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) * wide EPOW status. Each element in the buffer will contain the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) * EPOW status in it's bit representation for a particular EPOW sub
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) * class as defined here. So multiple detailed EPOW status bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) * specific for any sub class can be represented in a single buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) * element as it's bit representation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) /* System EPOW type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) enum OpalSysEpow {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) OPAL_SYSEPOW_POWER = 0, /* Power EPOW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) OPAL_SYSEPOW_TEMP = 1, /* Temperature EPOW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) OPAL_SYSEPOW_COOLING = 2, /* Cooling EPOW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) OPAL_SYSEPOW_MAX = 3, /* Max EPOW categories */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) /* Power EPOW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) enum OpalSysPower {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) OPAL_SYSPOWER_UPS = 0x0001, /* System on UPS power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) OPAL_SYSPOWER_CHNG = 0x0002, /* System power config change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) OPAL_SYSPOWER_FAIL = 0x0004, /* System impending power failure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) OPAL_SYSPOWER_INCL = 0x0008, /* System incomplete power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) /* Temperature EPOW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) enum OpalSysTemp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) OPAL_SYSTEMP_AMB = 0x0001, /* System over ambient temperature */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) OPAL_SYSTEMP_INT = 0x0002, /* System over internal temperature */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) OPAL_SYSTEMP_HMD = 0x0004, /* System over ambient humidity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) /* Cooling EPOW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) enum OpalSysCooling {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) OPAL_SYSCOOL_INSF = 0x0001, /* System insufficient cooling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) /* Argument to OPAL_CEC_REBOOT2() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) OPAL_REBOOT_NORMAL = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) OPAL_REBOOT_PLATFORM_ERROR = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) OPAL_REBOOT_FULL_IPL = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) OPAL_REBOOT_MPIPL = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) OPAL_REBOOT_FAST = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) /* Argument to OPAL_PCI_TCE_KILL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) OPAL_PCI_TCE_KILL_PAGES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) OPAL_PCI_TCE_KILL_PE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) OPAL_PCI_TCE_KILL_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) /* The xive operation mode indicates the active "API" and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) * corresponds to the "mode" parameter of the opal_xive_reset()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) * call
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) OPAL_XIVE_MODE_EMU = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) OPAL_XIVE_MODE_EXPL = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) /* Flags for OPAL_XIVE_GET_IRQ_INFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) OPAL_XIVE_IRQ_TRIGGER_PAGE = 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) OPAL_XIVE_IRQ_STORE_EOI = 0x00000002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) OPAL_XIVE_IRQ_LSI = 0x00000004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) OPAL_XIVE_IRQ_SHIFT_BUG = 0x00000008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) OPAL_XIVE_IRQ_MASK_VIA_FW = 0x00000010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) OPAL_XIVE_IRQ_EOI_VIA_FW = 0x00000020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) /* Flags for OPAL_XIVE_GET/SET_QUEUE_INFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) OPAL_XIVE_EQ_ENABLED = 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) OPAL_XIVE_EQ_ALWAYS_NOTIFY = 0x00000002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) OPAL_XIVE_EQ_ESCALATE = 0x00000004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) /* Flags for OPAL_XIVE_GET/SET_VP_INFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) OPAL_XIVE_VP_ENABLED = 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) OPAL_XIVE_VP_SINGLE_ESCALATION = 0x00000002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) /* "Any chip" replacement for chip ID for allocation functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) OPAL_XIVE_ANY_CHIP = 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) /* Xive sync options */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) /* This bits are cumulative, arg is a girq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) XIVE_SYNC_EAS = 0x00000001, /* Sync irq source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) XIVE_SYNC_QUEUE = 0x00000002, /* Sync irq target */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) /* Dump options */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) XIVE_DUMP_TM_HYP = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) XIVE_DUMP_TM_POOL = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) XIVE_DUMP_TM_OS = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) XIVE_DUMP_TM_USER = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) XIVE_DUMP_VP = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) XIVE_DUMP_EMU_STATE = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) /* "type" argument options for OPAL_IMC_COUNTERS_* calls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) OPAL_IMC_COUNTERS_NEST = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) OPAL_IMC_COUNTERS_CORE = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) OPAL_IMC_COUNTERS_TRACE = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) /* PCI p2p descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) #define OPAL_PCI_P2P_ENABLE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) #define OPAL_PCI_P2P_LOAD 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) #define OPAL_PCI_P2P_STORE 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) /* MPIPL update operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) enum opal_mpipl_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) OPAL_MPIPL_ADD_RANGE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) OPAL_MPIPL_REMOVE_RANGE = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) OPAL_MPIPL_REMOVE_ALL = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) OPAL_MPIPL_FREE_PRESERVED_MEMORY = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) /* Tag will point to various metadata area. Kernel will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) * use tag to get metadata value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) enum opal_mpipl_tags {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) OPAL_MPIPL_TAG_CPU = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) OPAL_MPIPL_TAG_OPAL = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) OPAL_MPIPL_TAG_KERNEL = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) OPAL_MPIPL_TAG_BOOT_MEM = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) /* Preserved memory details */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) struct opal_mpipl_region {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) __be64 src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) __be64 dest;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) __be64 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) /* Structure version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) #define OPAL_MPIPL_VERSION 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) struct opal_mpipl_fadump {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) u8 version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) u8 reserved[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) __be32 crashing_pir; /* OPAL crashing CPU PIR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) __be32 cpu_data_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) __be32 cpu_data_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) __be32 region_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) struct opal_mpipl_region region[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) #endif /* __ASSEMBLY__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) #endif /* __OPAL_API_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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