^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef _ASM_POWERPC_MPIC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define _ASM_POWERPC_MPIC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #ifdef __KERNEL__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <asm/dcr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <asm/msi_bitmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Global registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define MPIC_GREG_BASE 0x01000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define MPIC_GREG_FEATURE_0 0x00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MPIC_GREG_FEATURE_LAST_SRC_MASK 0x07ff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MPIC_GREG_FEATURE_LAST_SRC_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MPIC_GREG_FEATURE_LAST_CPU_MASK 0x00001f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MPIC_GREG_FEATURE_LAST_CPU_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MPIC_GREG_FEATURE_VERSION_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MPIC_GREG_FEATURE_1 0x00010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MPIC_GREG_GLOBAL_CONF_0 0x00020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MPIC_GREG_GCONF_RESET 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* On the FSL mpic implementations the Mode field is expand to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * 2 bits wide:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * 0b00 = pass through (interrupts routed to IRQ0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * 0b01 = Mixed mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * 0b10 = reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * 0b11 = External proxy / coreint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MPIC_GREG_GCONF_COREINT 0x60000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MPIC_GREG_GCONF_8259_PTHROU_DIS 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MPIC_GREG_GCONF_NO_BIAS 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MPIC_GREG_GCONF_BASE_MASK 0x000fffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MPIC_GREG_GCONF_MCK 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MPIC_GREG_GLOBAL_CONF_1 0x00030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MPIC_GREG_VENDOR_0 0x00040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MPIC_GREG_VENDOR_1 0x00050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MPIC_GREG_VENDOR_2 0x00060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MPIC_GREG_VENDOR_3 0x00070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MPIC_GREG_VENDOR_ID 0x00080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MPIC_GREG_VENDOR_ID_STEPPING_MASK 0x00ff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MPIC_GREG_VENDOR_ID_STEPPING_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MPIC_GREG_VENDOR_ID_DEVICE_ID_MASK 0x0000ff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MPIC_GREG_VENDOR_ID_DEVICE_ID_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MPIC_GREG_VENDOR_ID_VENDOR_ID_MASK 0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MPIC_GREG_PROCESSOR_INIT 0x00090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MPIC_GREG_IPI_VECTOR_PRI_0 0x000a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MPIC_GREG_IPI_VECTOR_PRI_1 0x000b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MPIC_GREG_IPI_VECTOR_PRI_2 0x000c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MPIC_GREG_IPI_VECTOR_PRI_3 0x000d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MPIC_GREG_IPI_STRIDE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MPIC_GREG_SPURIOUS 0x000e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MPIC_GREG_TIMER_FREQ 0x000f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * Timer registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MPIC_TIMER_BASE 0x01100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MPIC_TIMER_STRIDE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MPIC_TIMER_GROUP_STRIDE 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MPIC_TIMER_CURRENT_CNT 0x00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MPIC_TIMER_BASE_CNT 0x00010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MPIC_TIMER_VECTOR_PRI 0x00020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MPIC_TIMER_DESTINATION 0x00030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * Per-Processor registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MPIC_CPU_THISBASE 0x00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MPIC_CPU_BASE 0x20000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define MPIC_CPU_STRIDE 0x01000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MPIC_CPU_IPI_DISPATCH_0 0x00040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define MPIC_CPU_IPI_DISPATCH_1 0x00050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define MPIC_CPU_IPI_DISPATCH_2 0x00060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MPIC_CPU_IPI_DISPATCH_3 0x00070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define MPIC_CPU_IPI_DISPATCH_STRIDE 0x00010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define MPIC_CPU_CURRENT_TASK_PRI 0x00080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define MPIC_CPU_TASKPRI_MASK 0x0000000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define MPIC_CPU_WHOAMI 0x00090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define MPIC_CPU_WHOAMI_MASK 0x0000001f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define MPIC_CPU_INTACK 0x000a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define MPIC_CPU_EOI 0x000b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define MPIC_CPU_MCACK 0x000c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * Per-source registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define MPIC_IRQ_BASE 0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define MPIC_IRQ_STRIDE 0x00020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define MPIC_IRQ_VECTOR_PRI 0x00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define MPIC_VECPRI_MASK 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define MPIC_VECPRI_ACTIVITY 0x40000000 /* Read Only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define MPIC_VECPRI_PRIORITY_MASK 0x000f0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define MPIC_VECPRI_PRIORITY_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define MPIC_VECPRI_VECTOR_MASK 0x000007ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define MPIC_VECPRI_POLARITY_POSITIVE 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define MPIC_VECPRI_POLARITY_NEGATIVE 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define MPIC_VECPRI_POLARITY_MASK 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define MPIC_VECPRI_SENSE_LEVEL 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define MPIC_VECPRI_SENSE_EDGE 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define MPIC_VECPRI_SENSE_MASK 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define MPIC_IRQ_DESTINATION 0x00010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define MPIC_FSL_BRR1 0x00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define MPIC_FSL_BRR1_VER 0x0000ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define MPIC_MAX_IRQ_SOURCES 2048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define MPIC_MAX_CPUS 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define MPIC_MAX_ISU 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define MPIC_MAX_ERR 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define MPIC_FSL_ERR_INT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * Tsi108 implementation of MPIC has many differences from the original one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * Global registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define TSI108_GREG_BASE 0x00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define TSI108_GREG_FEATURE_0 0x00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define TSI108_GREG_GLOBAL_CONF_0 0x00004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define TSI108_GREG_VENDOR_ID 0x0000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define TSI108_GREG_IPI_VECTOR_PRI_0 0x00204 /* Doorbell 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define TSI108_GREG_IPI_STRIDE 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define TSI108_GREG_SPURIOUS 0x00010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define TSI108_GREG_TIMER_FREQ 0x00014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * Timer registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define TSI108_TIMER_BASE 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define TSI108_TIMER_STRIDE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define TSI108_TIMER_CURRENT_CNT 0x00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define TSI108_TIMER_BASE_CNT 0x00004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define TSI108_TIMER_VECTOR_PRI 0x00008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define TSI108_TIMER_DESTINATION 0x0000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * Per-Processor registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define TSI108_CPU_BASE 0x00300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define TSI108_CPU_STRIDE 0x00040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define TSI108_CPU_IPI_DISPATCH_0 0x00200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define TSI108_CPU_IPI_DISPATCH_STRIDE 0x00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define TSI108_CPU_CURRENT_TASK_PRI 0x00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define TSI108_CPU_WHOAMI 0xffffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define TSI108_CPU_INTACK 0x00004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define TSI108_CPU_EOI 0x00008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define TSI108_CPU_MCACK 0x00004 /* Doesn't really exist here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * Per-source registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define TSI108_IRQ_BASE 0x00100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define TSI108_IRQ_STRIDE 0x00008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define TSI108_IRQ_VECTOR_PRI 0x00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define TSI108_VECPRI_VECTOR_MASK 0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define TSI108_VECPRI_POLARITY_POSITIVE 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define TSI108_VECPRI_POLARITY_NEGATIVE 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define TSI108_VECPRI_SENSE_LEVEL 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define TSI108_VECPRI_SENSE_EDGE 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define TSI108_VECPRI_POLARITY_MASK 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define TSI108_VECPRI_SENSE_MASK 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define TSI108_IRQ_DESTINATION 0x00004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* weird mpic register indices and mask bits in the HW info array */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) MPIC_IDX_GREG_BASE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) MPIC_IDX_GREG_FEATURE_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) MPIC_IDX_GREG_GLOBAL_CONF_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) MPIC_IDX_GREG_VENDOR_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) MPIC_IDX_GREG_IPI_VECTOR_PRI_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) MPIC_IDX_GREG_IPI_STRIDE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) MPIC_IDX_GREG_SPURIOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) MPIC_IDX_GREG_TIMER_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) MPIC_IDX_TIMER_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) MPIC_IDX_TIMER_STRIDE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) MPIC_IDX_TIMER_CURRENT_CNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) MPIC_IDX_TIMER_BASE_CNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) MPIC_IDX_TIMER_VECTOR_PRI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) MPIC_IDX_TIMER_DESTINATION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) MPIC_IDX_CPU_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) MPIC_IDX_CPU_STRIDE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) MPIC_IDX_CPU_IPI_DISPATCH_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) MPIC_IDX_CPU_IPI_DISPATCH_STRIDE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) MPIC_IDX_CPU_CURRENT_TASK_PRI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) MPIC_IDX_CPU_WHOAMI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) MPIC_IDX_CPU_INTACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) MPIC_IDX_CPU_EOI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) MPIC_IDX_CPU_MCACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) MPIC_IDX_IRQ_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) MPIC_IDX_IRQ_STRIDE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) MPIC_IDX_IRQ_VECTOR_PRI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) MPIC_IDX_VECPRI_VECTOR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) MPIC_IDX_VECPRI_POLARITY_POSITIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) MPIC_IDX_VECPRI_POLARITY_NEGATIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) MPIC_IDX_VECPRI_SENSE_LEVEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) MPIC_IDX_VECPRI_SENSE_EDGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) MPIC_IDX_VECPRI_POLARITY_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) MPIC_IDX_VECPRI_SENSE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) MPIC_IDX_IRQ_DESTINATION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) MPIC_IDX_END
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #ifdef CONFIG_MPIC_U3_HT_IRQS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* Fixup table entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct mpic_irq_fixup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) u8 __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) u8 __iomem *applebase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) unsigned int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #endif /* CONFIG_MPIC_U3_HT_IRQS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) enum mpic_reg_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) mpic_access_mmio_le,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) mpic_access_mmio_be,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #ifdef CONFIG_PPC_DCR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) mpic_access_dcr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct mpic_reg_bank {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) u32 __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #ifdef CONFIG_PPC_DCR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) dcr_host_t dhost;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #endif /* CONFIG_PPC_DCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct mpic_irq_save {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) u32 vecprio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) dest;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #ifdef CONFIG_MPIC_U3_HT_IRQS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) u32 fixup_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* The instance data of a given MPIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) struct mpic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* The OpenFirmware dt node for this MPIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct device_node *node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* The remapper for this MPIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) struct irq_domain *irqhost;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* The "linux" controller struct */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) struct irq_chip hc_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #ifdef CONFIG_MPIC_U3_HT_IRQS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) struct irq_chip hc_ht_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) struct irq_chip hc_ipi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct irq_chip hc_tm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct irq_chip hc_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /* Flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) unsigned int flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /* How many irq sources in a given ISU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) unsigned int isu_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) unsigned int isu_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) unsigned int isu_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* Number of sources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) unsigned int num_sources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /* vector numbers used for internal sources (ipi/timers) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) unsigned int ipi_vecs[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) unsigned int timer_vecs[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* vector numbers used for FSL MPIC error interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) unsigned int err_int_vecs[MPIC_MAX_ERR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /* Spurious vector to program into unused sources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) unsigned int spurious_vec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #ifdef CONFIG_MPIC_U3_HT_IRQS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /* The fixup table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) struct mpic_irq_fixup *fixups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) raw_spinlock_t fixup_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /* Register access method */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) enum mpic_reg_type reg_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /* The physical base address of the MPIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) phys_addr_t paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /* The various ioremap'ed bases */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct mpic_reg_bank thiscpuregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct mpic_reg_bank gregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) struct mpic_reg_bank tmregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) struct mpic_reg_bank cpuregs[MPIC_MAX_CPUS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) struct mpic_reg_bank isus[MPIC_MAX_ISU];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* ioremap'ed base for error interrupt registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) u32 __iomem *err_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /* Protected sources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) unsigned long *protected;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #ifdef CONFIG_MPIC_WEIRD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /* Pointer to HW info array */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) u32 *hw_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #ifdef CONFIG_PCI_MSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) struct msi_bitmap msi_bitmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #ifdef CONFIG_MPIC_BROKEN_REGREAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) u32 isu_reg0_shadow[MPIC_MAX_IRQ_SOURCES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /* link */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) struct mpic *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct mpic_irq_save *save_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) extern struct bus_type mpic_subsys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * MPIC flags (passed to mpic_alloc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) * The top 4 bits contain an MPIC bhw id that is used to index the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * register offsets and some masks when CONFIG_MPIC_WEIRD is set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * Note setting any ID (leaving those bits to 0) means standard MPIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * This is a secondary ("chained") controller; it only uses the CPU0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * registers. Primary controllers have IPIs and affinity control.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define MPIC_SECONDARY 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /* Set this for a big-endian MPIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define MPIC_BIG_ENDIAN 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /* Broken U3 MPIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define MPIC_U3_HT_IRQS 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /* Broken IPI registers (autodetected) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define MPIC_BROKEN_IPI 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /* Spurious vector requires EOI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define MPIC_SPV_EOI 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /* No passthrough disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define MPIC_NO_PTHROU_DIS 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /* DCR based MPIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define MPIC_USES_DCR 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /* MPIC has 11-bit vector fields (or larger) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define MPIC_LARGE_VECTORS 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /* Enable delivery of prio 15 interrupts as MCK instead of EE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define MPIC_ENABLE_MCK 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /* Disable bias among target selection, spread interrupts evenly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define MPIC_NO_BIAS 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /* Destination only supports a single CPU at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define MPIC_SINGLE_DEST_CPU 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /* Enable CoreInt delivery of interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define MPIC_ENABLE_COREINT 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /* Do not reset the MPIC during initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define MPIC_NO_RESET 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* Freescale MPIC (compatible includes "fsl,mpic") */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define MPIC_FSL 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /* Freescale MPIC supports EIMR (error interrupt mask register).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) * This flag is set for MPIC version >= 4.1 (version determined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) * from the BRR1 register).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define MPIC_FSL_HAS_EIMR 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /* MPIC HW modification ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define MPIC_REGSET_MASK 0xf0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define MPIC_REGSET(val) (((val) & 0xf ) << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define MPIC_GET_REGSET(flags) (((flags) >> 28) & 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define MPIC_REGSET_STANDARD MPIC_REGSET(0) /* Original MPIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define MPIC_REGSET_TSI108 MPIC_REGSET(1) /* Tsi108/109 PIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) /* Get the version of primary MPIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #ifdef CONFIG_MPIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) extern u32 fsl_mpic_primary_get_version(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static inline u32 fsl_mpic_primary_get_version(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /* Allocate the controller structure and setup the linux irq descs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * for the range if interrupts passed in. No HW initialization is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * actually performed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * @phys_addr: physial base address of the MPIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * @flags: flags, see constants above
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * @isu_size: number of interrupts in an ISU. Use 0 to use a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) * standard ISU-less setup (aka powermac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) * @irq_offset: first irq number to assign to this mpic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) * @irq_count: number of irqs to use with this mpic IRQ sources. Pass 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * to match the number of sources
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) * @ipi_offset: first irq number to assign to this mpic IPI sources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * used only on primary mpic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * @senses: array of sense values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * @senses_num: number of entries in the array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) * Note about the sense array. If none is passed, all interrupts are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) * setup to be level negative unless MPIC_U3_HT_IRQS is set in which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) * case they are edge positive (and the array is ignored anyway).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) * The values in the array start at the first source of the MPIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) * that is senses[0] correspond to linux irq "irq_offset".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) extern struct mpic *mpic_alloc(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) phys_addr_t phys_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) unsigned int flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) unsigned int isu_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) unsigned int irq_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) const char *name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /* Assign ISUs, to call before mpic_init()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) * @mpic: controller structure as returned by mpic_alloc()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) * @isu_num: ISU number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) * @phys_addr: physical address of the ISU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) extern void mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) phys_addr_t phys_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /* Initialize the controller. After this has been called, none of the above
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) * should be called again for this mpic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) extern void mpic_init(struct mpic *mpic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) * All of the following functions must only be used after the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) * ISUs have been assigned and the controller fully initialized
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) * with mpic_init()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /* Change the priority of an interrupt. Default is 8 for irqs and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) * 10 for IPIs. You can call this on both IPIs and IRQ numbers, but the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) * IPI number is then the offset'ed (linux irq number mapped to the IPI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) extern void mpic_irq_set_priority(unsigned int irq, unsigned int pri);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /* Setup a non-boot CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) extern void mpic_setup_this_cpu(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) /* Clean up for kexec (or cpu offline or ...) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) extern void mpic_teardown_this_cpu(int secondary);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) /* Get the current cpu priority for this cpu (0..15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) extern int mpic_cpu_get_priority(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /* Set the current cpu priority for this cpu */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) extern void mpic_cpu_set_priority(int prio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /* Request IPIs on primary mpic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) extern void mpic_request_ipis(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /* Send a message (IPI) to a given target (cpu number or MSG_*) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) void smp_mpic_message_pass(int target, int msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) /* Unmask a specific virq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) extern void mpic_unmask_irq(struct irq_data *d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) /* Mask a specific virq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) extern void mpic_mask_irq(struct irq_data *d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) /* EOI a specific virq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) extern void mpic_end_irq(struct irq_data *d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) /* Fetch interrupt from a given mpic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) extern unsigned int mpic_get_one_irq(struct mpic *mpic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) /* This one gets from the primary mpic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) extern unsigned int mpic_get_irq(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /* This one gets from the primary mpic via CoreInt*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) extern unsigned int mpic_get_coreint_irq(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) /* Fetch Machine Check interrupt from primary mpic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) extern unsigned int mpic_get_mcirq(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #endif /* __KERNEL__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #endif /* _ASM_POWERPC_MPIC_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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