Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * Prototypes, etc. for the Freescale MPC52xx embedded cpu chips
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * May need to be cleaned as the port goes on ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2004-2005 Sylvain Munaut <tnt@246tNt.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (C) 2003 MontaVista, Software, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * This file is licensed under the terms of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * version 2. This program is licensed "as is" without any warranty of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #ifndef __ASM_POWERPC_MPC52xx_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define __ASM_POWERPC_MPC52xx_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <asm/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <asm/prom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <asm/mpc5xxx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #endif /* __ASSEMBLY__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/suspend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) /* Variants of the 5200(B) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define MPC5200_SVR		0x80110010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define MPC5200_SVR_MASK	0xfffffff0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define MPC5200B_SVR		0x80110020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define MPC5200B_SVR_MASK	0xfffffff0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) /* ======================================================================== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) /* Structures mapping of some unit register set                             */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) /* ======================================================================== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) /* Memory Mapping Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) struct mpc52xx_mmap_ctl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	u32 mbar;		/* MMAP_CTRL + 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	u32 cs0_start;		/* MMAP_CTRL + 0x04 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	u32 cs0_stop;		/* MMAP_CTRL + 0x08 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	u32 cs1_start;		/* MMAP_CTRL + 0x0c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	u32 cs1_stop;		/* MMAP_CTRL + 0x10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	u32 cs2_start;		/* MMAP_CTRL + 0x14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	u32 cs2_stop;		/* MMAP_CTRL + 0x18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	u32 cs3_start;		/* MMAP_CTRL + 0x1c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	u32 cs3_stop;		/* MMAP_CTRL + 0x20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	u32 cs4_start;		/* MMAP_CTRL + 0x24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	u32 cs4_stop;		/* MMAP_CTRL + 0x28 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	u32 cs5_start;		/* MMAP_CTRL + 0x2c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	u32 cs5_stop;		/* MMAP_CTRL + 0x30 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	u32 sdram0;		/* MMAP_CTRL + 0x34 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	u32 sdram1;		/* MMAP_CTRL + 0X38 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	u32 reserved[4];	/* MMAP_CTRL + 0x3c .. 0x48 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	u32 boot_start;		/* MMAP_CTRL + 0x4c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	u32 boot_stop;		/* MMAP_CTRL + 0x50 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	u32 ipbi_ws_ctrl;	/* MMAP_CTRL + 0x54 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	u32 cs6_start;		/* MMAP_CTRL + 0x58 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	u32 cs6_stop;		/* MMAP_CTRL + 0x5c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	u32 cs7_start;		/* MMAP_CTRL + 0x60 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	u32 cs7_stop;		/* MMAP_CTRL + 0x64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) /* SDRAM control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) struct mpc52xx_sdram {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	u32 mode;		/* SDRAM + 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	u32 ctrl;		/* SDRAM + 0x04 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	u32 config1;		/* SDRAM + 0x08 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	u32 config2;		/* SDRAM + 0x0c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) /* SDMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) struct mpc52xx_sdma {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	u32 taskBar;		/* SDMA + 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	u32 currentPointer;	/* SDMA + 0x04 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	u32 endPointer;		/* SDMA + 0x08 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	u32 variablePointer;	/* SDMA + 0x0c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	u8 IntVect1;		/* SDMA + 0x10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	u8 IntVect2;		/* SDMA + 0x11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	u16 PtdCntrl;		/* SDMA + 0x12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	u32 IntPend;		/* SDMA + 0x14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	u32 IntMask;		/* SDMA + 0x18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	u16 tcr[16];		/* SDMA + 0x1c .. 0x3a */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	u8 ipr[32];		/* SDMA + 0x3c .. 0x5b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	u32 cReqSelect;		/* SDMA + 0x5c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	u32 task_size0;		/* SDMA + 0x60 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	u32 task_size1;		/* SDMA + 0x64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	u32 MDEDebug;		/* SDMA + 0x68 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	u32 ADSDebug;		/* SDMA + 0x6c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	u32 Value1;		/* SDMA + 0x70 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	u32 Value2;		/* SDMA + 0x74 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	u32 Control;		/* SDMA + 0x78 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	u32 Status;		/* SDMA + 0x7c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	u32 PTDDebug;		/* SDMA + 0x80 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* GPT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct mpc52xx_gpt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	u32 mode;		/* GPTx + 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	u32 count;		/* GPTx + 0x04 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	u32 pwm;		/* GPTx + 0x08 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	u32 status;		/* GPTx + 0X0c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* GPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct mpc52xx_gpio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	u32 port_config;	/* GPIO + 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	u32 simple_gpioe;	/* GPIO + 0x04 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	u32 simple_ode;		/* GPIO + 0x08 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	u32 simple_ddr;		/* GPIO + 0x0c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	u32 simple_dvo;		/* GPIO + 0x10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	u32 simple_ival;	/* GPIO + 0x14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	u8 outo_gpioe;		/* GPIO + 0x18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	u8 reserved1[3];	/* GPIO + 0x19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	u8 outo_dvo;		/* GPIO + 0x1c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	u8 reserved2[3];	/* GPIO + 0x1d */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	u8 sint_gpioe;		/* GPIO + 0x20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	u8 reserved3[3];	/* GPIO + 0x21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	u8 sint_ode;		/* GPIO + 0x24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	u8 reserved4[3];	/* GPIO + 0x25 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	u8 sint_ddr;		/* GPIO + 0x28 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	u8 reserved5[3];	/* GPIO + 0x29 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	u8 sint_dvo;		/* GPIO + 0x2c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	u8 reserved6[3];	/* GPIO + 0x2d */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	u8 sint_inten;		/* GPIO + 0x30 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	u8 reserved7[3];	/* GPIO + 0x31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	u16 sint_itype;		/* GPIO + 0x34 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	u16 reserved8;		/* GPIO + 0x36 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	u8 gpio_control;	/* GPIO + 0x38 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	u8 reserved9[3];	/* GPIO + 0x39 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	u8 sint_istat;		/* GPIO + 0x3c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	u8 sint_ival;		/* GPIO + 0x3d */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	u8 bus_errs;		/* GPIO + 0x3e */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	u8 reserved10;		/* GPIO + 0x3f */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define MPC52xx_GPIO_PSC_CONFIG_UART_WITHOUT_CD	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define MPC52xx_GPIO_PSC_CONFIG_UART_WITH_CD	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define MPC52xx_GPIO_PCI_DIS			(1<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* GPIO with WakeUp*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct mpc52xx_gpio_wkup {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	u8 wkup_gpioe;		/* GPIO_WKUP + 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	u8 reserved1[3];	/* GPIO_WKUP + 0x03 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	u8 wkup_ode;		/* GPIO_WKUP + 0x04 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	u8 reserved2[3];	/* GPIO_WKUP + 0x05 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	u8 wkup_ddr;		/* GPIO_WKUP + 0x08 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	u8 reserved3[3];	/* GPIO_WKUP + 0x09 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	u8 wkup_dvo;		/* GPIO_WKUP + 0x0C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	u8 reserved4[3];	/* GPIO_WKUP + 0x0D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	u8 wkup_inten;		/* GPIO_WKUP + 0x10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	u8 reserved5[3];	/* GPIO_WKUP + 0x11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	u8 wkup_iinten;		/* GPIO_WKUP + 0x14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	u8 reserved6[3];	/* GPIO_WKUP + 0x15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	u16 wkup_itype;		/* GPIO_WKUP + 0x18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	u8 reserved7[2];	/* GPIO_WKUP + 0x1A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	u8 wkup_maste;		/* GPIO_WKUP + 0x1C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	u8 reserved8[3];	/* GPIO_WKUP + 0x1D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	u8 wkup_ival;		/* GPIO_WKUP + 0x20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	u8 reserved9[3];	/* GPIO_WKUP + 0x21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	u8 wkup_istat;		/* GPIO_WKUP + 0x24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	u8 reserved10[3];	/* GPIO_WKUP + 0x25 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* XLB Bus control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct mpc52xx_xlb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	u8 reserved[0x40];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	u32 config;		/* XLB + 0x40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	u32 version;		/* XLB + 0x44 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	u32 status;		/* XLB + 0x48 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	u32 int_enable;		/* XLB + 0x4c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	u32 addr_capture;	/* XLB + 0x50 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	u32 bus_sig_capture;	/* XLB + 0x54 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	u32 addr_timeout;	/* XLB + 0x58 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	u32 data_timeout;	/* XLB + 0x5c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	u32 bus_act_timeout;	/* XLB + 0x60 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	u32 master_pri_enable;	/* XLB + 0x64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	u32 master_priority;	/* XLB + 0x68 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	u32 base_address;	/* XLB + 0x6c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	u32 snoop_window;	/* XLB + 0x70 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define MPC52xx_XLB_CFG_PLDIS		(1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define MPC52xx_XLB_CFG_SNOOP		(1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* Clock Distribution control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct mpc52xx_cdm {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	u32 jtag_id;		/* CDM + 0x00  reg0 read only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	u32 rstcfg;		/* CDM + 0x04  reg1 read only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	u32 breadcrumb;		/* CDM + 0x08  reg2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	u8 mem_clk_sel;		/* CDM + 0x0c  reg3 byte0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	u8 xlb_clk_sel;		/* CDM + 0x0d  reg3 byte1 read only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	u8 ipb_clk_sel;		/* CDM + 0x0e  reg3 byte2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	u8 pci_clk_sel;		/* CDM + 0x0f  reg3 byte3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	u8 ext_48mhz_en;	/* CDM + 0x10  reg4 byte0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	u8 fd_enable;		/* CDM + 0x11  reg4 byte1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	u16 fd_counters;	/* CDM + 0x12  reg4 byte2,3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	u32 clk_enables;	/* CDM + 0x14  reg5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	u8 osc_disable;		/* CDM + 0x18  reg6 byte0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	u8 reserved0[3];	/* CDM + 0x19  reg6 byte1,2,3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	u8 ccs_sleep_enable;	/* CDM + 0x1c  reg7 byte0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	u8 osc_sleep_enable;	/* CDM + 0x1d  reg7 byte1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	u8 reserved1;		/* CDM + 0x1e  reg7 byte2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	u8 ccs_qreq_test;	/* CDM + 0x1f  reg7 byte3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	u8 soft_reset;		/* CDM + 0x20  u8 byte0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	u8 no_ckstp;		/* CDM + 0x21  u8 byte0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	u8 reserved2[2];	/* CDM + 0x22  u8 byte1,2,3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	u8 pll_lock;		/* CDM + 0x24  reg9 byte0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	u8 pll_looselock;	/* CDM + 0x25  reg9 byte1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	u8 pll_sm_lockwin;	/* CDM + 0x26  reg9 byte2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	u8 reserved3;		/* CDM + 0x27  reg9 byte3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	u16 reserved4;		/* CDM + 0x28  reg10 byte0,1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	u16 mclken_div_psc1;	/* CDM + 0x2a  reg10 byte2,3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	u16 reserved5;		/* CDM + 0x2c  reg11 byte0,1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	u16 mclken_div_psc2;	/* CDM + 0x2e  reg11 byte2,3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	u16 reserved6;		/* CDM + 0x30  reg12 byte0,1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	u16 mclken_div_psc3;	/* CDM + 0x32  reg12 byte2,3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	u16 reserved7;		/* CDM + 0x34  reg13 byte0,1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	u16 mclken_div_psc6;	/* CDM + 0x36  reg13 byte2,3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* Interrupt controller Register set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct mpc52xx_intr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	u32 per_mask;		/* INTR + 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	u32 per_pri1;		/* INTR + 0x04 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	u32 per_pri2;		/* INTR + 0x08 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	u32 per_pri3;		/* INTR + 0x0c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	u32 ctrl;		/* INTR + 0x10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	u32 main_mask;		/* INTR + 0x14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	u32 main_pri1;		/* INTR + 0x18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	u32 main_pri2;		/* INTR + 0x1c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	u32 reserved1;		/* INTR + 0x20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	u32 enc_status;		/* INTR + 0x24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	u32 crit_status;	/* INTR + 0x28 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	u32 main_status;	/* INTR + 0x2c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	u32 per_status;		/* INTR + 0x30 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	u32 reserved2;		/* INTR + 0x34 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	u32 per_error;		/* INTR + 0x38 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #endif /* __ASSEMBLY__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* ========================================================================= */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* Prototypes for MPC52xx sysdev                                             */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* ========================================================================= */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* mpc52xx_common.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) extern void mpc5200_setup_xlb_arbiter(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) extern void mpc52xx_declare_of_platform_devices(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) extern int mpc5200_psc_ac97_gpio_reset(int psc_number);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) extern void mpc52xx_map_common_devices(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) extern int mpc52xx_set_psc_clkdiv(int psc_id, int clkdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) extern unsigned int mpc52xx_get_xtal_freq(struct device_node *node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) extern void __noreturn mpc52xx_restart(char *cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* mpc52xx_gpt.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) struct mpc52xx_gpt_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) extern struct mpc52xx_gpt_priv *mpc52xx_gpt_from_irq(int irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) extern int mpc52xx_gpt_start_timer(struct mpc52xx_gpt_priv *gpt, u64 period,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)                             int continuous);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) extern u64 mpc52xx_gpt_timer_period(struct mpc52xx_gpt_priv *gpt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) extern int mpc52xx_gpt_stop_timer(struct mpc52xx_gpt_priv *gpt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* mpc52xx_lpbfifo.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define MPC52XX_LPBFIFO_FLAG_READ		(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define MPC52XX_LPBFIFO_FLAG_WRITE		(1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define MPC52XX_LPBFIFO_FLAG_NO_INCREMENT	(1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define MPC52XX_LPBFIFO_FLAG_NO_DMA		(1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define MPC52XX_LPBFIFO_FLAG_POLL_DMA		(1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) struct mpc52xx_lpbfifo_request {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	/* localplus bus address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	unsigned int cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	size_t offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	/* Memory address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	void *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	phys_addr_t data_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	/* Details of transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	size_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	size_t pos;	/* current position of transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	int flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	int defer_xfer_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	/* What to do when finished */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	void (*callback)(struct mpc52xx_lpbfifo_request *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	void *priv;		/* Driver private data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	/* statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	int irq_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	int irq_ticks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	u8 last_byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	int buffer_not_done_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) extern int mpc52xx_lpbfifo_submit(struct mpc52xx_lpbfifo_request *req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) extern void mpc52xx_lpbfifo_abort(struct mpc52xx_lpbfifo_request *req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) extern void mpc52xx_lpbfifo_poll(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) extern int mpc52xx_lpbfifo_start_xfer(struct mpc52xx_lpbfifo_request *req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* mpc52xx_pic.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) extern void mpc52xx_init_irq(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) extern unsigned int mpc52xx_get_irq(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /* mpc52xx_pci.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) extern int __init mpc52xx_add_bridge(struct device_node *node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) extern void __init mpc52xx_setup_pci(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static inline void mpc52xx_setup_pci(void) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #endif /* __ASSEMBLY__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) struct mpc52xx_suspend {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	void (*board_suspend_prepare)(void __iomem *mbar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	void (*board_resume_finish)(void __iomem *mbar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) extern struct mpc52xx_suspend mpc52xx_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) extern int __init mpc52xx_pm_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) extern int mpc52xx_set_wakeup_gpio(u8 pin, u8 level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /* lite5200 calls mpc5200 suspend functions, so here they are */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) extern int mpc52xx_pm_prepare(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) extern int mpc52xx_pm_enter(suspend_state_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) extern void mpc52xx_pm_finish(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) extern char saved_sram[0x4000]; /* reuse buffer from mpc52xx suspend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #ifdef CONFIG_PPC_LITE5200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) int __init lite5200_pm_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #endif /* CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #endif /* __ASM_POWERPC_MPC52xx_H__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)