^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * MPC5121 Prototypes and definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef __ASM_POWERPC_MPC5121_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define __ASM_POWERPC_MPC5121_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) /* MPC512x Reset module registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) struct mpc512x_reset_module {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) u32 rcwlr; /* Reset Configuration Word Low Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) u32 rcwhr; /* Reset Configuration Word High Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) u32 reserved1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) u32 reserved2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) u32 rsr; /* Reset Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) u32 rmr; /* Reset Mode Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) u32 rpr; /* Reset Protection Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) u32 rcr; /* Reset Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) u32 rcer; /* Reset Control Enable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * Clock Control Module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct mpc512x_ccm {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) u32 spmr; /* System PLL Mode Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) u32 sccr1; /* System Clock Control Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) u32 sccr2; /* System Clock Control Register 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) u32 scfr1; /* System Clock Frequency Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) u32 scfr2; /* System Clock Frequency Register 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u32 scfr2s; /* System Clock Frequency Shadow Register 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) u32 bcr; /* Bread Crumb Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) u32 psc_ccr[12]; /* PSC Clock Control Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) u32 spccr; /* SPDIF Clock Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) u32 cccr; /* CFM Clock Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) u32 dccr; /* DIU Clock Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) u32 mscan_ccr[4]; /* MSCAN Clock Control Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u32 out_ccr[4]; /* OUT CLK Configure Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) u32 rsv0[2]; /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) u32 scfr3; /* System Clock Frequency Register 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u32 rsv1[3]; /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u32 spll_lock_cnt; /* System PLL Lock Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u8 res[0x6c]; /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * LPC Module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct mpc512x_lpc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) u32 cs_cfg[8]; /* CS config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) u32 cs_ctrl; /* CS Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) u32 cs_status; /* CS Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u32 burst_ctrl; /* CS Burst Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u32 deadcycle_ctrl; /* CS Deadcycle Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u32 holdcycle_ctrl; /* CS Holdcycle Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u32 alt; /* Address Latch Timing Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) int mpc512x_cs_config(unsigned int cs, u32 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * SCLPC Module (LPB FIFO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct mpc512x_lpbfifo {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u32 pkt_size; /* SCLPC Packet Size Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u32 start_addr; /* SCLPC Start Address Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u32 ctrl; /* SCLPC Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u32 enable; /* SCLPC Enable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) u32 reserved1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u32 status; /* SCLPC Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u32 bytes_done; /* SCLPC Bytes Done Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u32 emb_sc; /* EMB Share Counter Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u32 emb_pc; /* EMB Pause Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u32 reserved2[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u32 data_word; /* LPC RX/TX FIFO Data Word Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u32 fifo_status; /* LPC RX/TX FIFO Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u32 fifo_ctrl; /* LPC RX/TX FIFO Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u32 fifo_alarm; /* LPC RX/TX FIFO Alarm Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MPC512X_SCLPC_START (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define MPC512X_SCLPC_CS(x) (((x) & 0x7) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define MPC512X_SCLPC_FLUSH (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define MPC512X_SCLPC_READ (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define MPC512X_SCLPC_DAI (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define MPC512X_SCLPC_BPT(x) ((x) & 0x3f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define MPC512X_SCLPC_RESET (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define MPC512X_SCLPC_FIFO_RESET (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define MPC512X_SCLPC_ABORT_INT_ENABLE (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define MPC512X_SCLPC_NORM_INT_ENABLE (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define MPC512X_SCLPC_ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define MPC512X_SCLPC_SUCCESS (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define MPC512X_SCLPC_FIFO_CTRL(x) (((x) & 0x7) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define MPC512X_SCLPC_FIFO_ALARM(x) ((x) & 0x3ff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) enum lpb_dev_portsize {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) LPB_DEV_PORTSIZE_UNDEFINED = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) LPB_DEV_PORTSIZE_1_BYTE = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) LPB_DEV_PORTSIZE_2_BYTES = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) LPB_DEV_PORTSIZE_4_BYTES = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) LPB_DEV_PORTSIZE_8_BYTES = 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) enum mpc512x_lpbfifo_req_dir {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) MPC512X_LPBFIFO_REQ_DIR_READ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) MPC512X_LPBFIFO_REQ_DIR_WRITE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct mpc512x_lpbfifo_request {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) phys_addr_t dev_phys_addr; /* physical address of some device on LPB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) void *ram_virt_addr; /* virtual address of some region in RAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u32 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) enum lpb_dev_portsize portsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) enum mpc512x_lpbfifo_req_dir dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) void (*callback)(struct mpc512x_lpbfifo_request *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) int mpc512x_lpbfifo_submit(struct mpc512x_lpbfifo_request *req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #endif /* __ASM_POWERPC_MPC5121_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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