^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * PS3 hvcall interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2006 Sony Computer Entertainment Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright 2006 Sony Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright 2003, 2004 (c) MontaVista Software, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #if !defined(_ASM_POWERPC_LV1CALL_H)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define _ASM_POWERPC_LV1CALL_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #if !defined(__ASSEMBLY__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* lv1 call declaration macros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define LV1_1_IN_ARG_DECL u64 in_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define LV1_2_IN_ARG_DECL LV1_1_IN_ARG_DECL, u64 in_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define LV1_3_IN_ARG_DECL LV1_2_IN_ARG_DECL, u64 in_3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define LV1_4_IN_ARG_DECL LV1_3_IN_ARG_DECL, u64 in_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define LV1_5_IN_ARG_DECL LV1_4_IN_ARG_DECL, u64 in_5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define LV1_6_IN_ARG_DECL LV1_5_IN_ARG_DECL, u64 in_6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define LV1_7_IN_ARG_DECL LV1_6_IN_ARG_DECL, u64 in_7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define LV1_8_IN_ARG_DECL LV1_7_IN_ARG_DECL, u64 in_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define LV1_1_OUT_ARG_DECL u64 *out_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define LV1_2_OUT_ARG_DECL LV1_1_OUT_ARG_DECL, u64 *out_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define LV1_3_OUT_ARG_DECL LV1_2_OUT_ARG_DECL, u64 *out_3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define LV1_4_OUT_ARG_DECL LV1_3_OUT_ARG_DECL, u64 *out_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define LV1_5_OUT_ARG_DECL LV1_4_OUT_ARG_DECL, u64 *out_5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define LV1_6_OUT_ARG_DECL LV1_5_OUT_ARG_DECL, u64 *out_6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define LV1_7_OUT_ARG_DECL LV1_6_OUT_ARG_DECL, u64 *out_7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define LV1_0_IN_0_OUT_ARG_DECL void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define LV1_1_IN_0_OUT_ARG_DECL LV1_1_IN_ARG_DECL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define LV1_2_IN_0_OUT_ARG_DECL LV1_2_IN_ARG_DECL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define LV1_3_IN_0_OUT_ARG_DECL LV1_3_IN_ARG_DECL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define LV1_4_IN_0_OUT_ARG_DECL LV1_4_IN_ARG_DECL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define LV1_5_IN_0_OUT_ARG_DECL LV1_5_IN_ARG_DECL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define LV1_6_IN_0_OUT_ARG_DECL LV1_6_IN_ARG_DECL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define LV1_7_IN_0_OUT_ARG_DECL LV1_7_IN_ARG_DECL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define LV1_0_IN_1_OUT_ARG_DECL LV1_1_OUT_ARG_DECL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define LV1_1_IN_1_OUT_ARG_DECL LV1_1_IN_ARG_DECL, LV1_1_OUT_ARG_DECL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define LV1_2_IN_1_OUT_ARG_DECL LV1_2_IN_ARG_DECL, LV1_1_OUT_ARG_DECL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define LV1_3_IN_1_OUT_ARG_DECL LV1_3_IN_ARG_DECL, LV1_1_OUT_ARG_DECL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define LV1_4_IN_1_OUT_ARG_DECL LV1_4_IN_ARG_DECL, LV1_1_OUT_ARG_DECL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define LV1_5_IN_1_OUT_ARG_DECL LV1_5_IN_ARG_DECL, LV1_1_OUT_ARG_DECL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define LV1_6_IN_1_OUT_ARG_DECL LV1_6_IN_ARG_DECL, LV1_1_OUT_ARG_DECL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define LV1_7_IN_1_OUT_ARG_DECL LV1_7_IN_ARG_DECL, LV1_1_OUT_ARG_DECL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define LV1_8_IN_1_OUT_ARG_DECL LV1_8_IN_ARG_DECL, LV1_1_OUT_ARG_DECL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define LV1_0_IN_2_OUT_ARG_DECL LV1_2_OUT_ARG_DECL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define LV1_1_IN_2_OUT_ARG_DECL LV1_1_IN_ARG_DECL, LV1_2_OUT_ARG_DECL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define LV1_2_IN_2_OUT_ARG_DECL LV1_2_IN_ARG_DECL, LV1_2_OUT_ARG_DECL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define LV1_3_IN_2_OUT_ARG_DECL LV1_3_IN_ARG_DECL, LV1_2_OUT_ARG_DECL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define LV1_4_IN_2_OUT_ARG_DECL LV1_4_IN_ARG_DECL, LV1_2_OUT_ARG_DECL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define LV1_5_IN_2_OUT_ARG_DECL LV1_5_IN_ARG_DECL, LV1_2_OUT_ARG_DECL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define LV1_6_IN_2_OUT_ARG_DECL LV1_6_IN_ARG_DECL, LV1_2_OUT_ARG_DECL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define LV1_7_IN_2_OUT_ARG_DECL LV1_7_IN_ARG_DECL, LV1_2_OUT_ARG_DECL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define LV1_0_IN_3_OUT_ARG_DECL LV1_3_OUT_ARG_DECL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define LV1_1_IN_3_OUT_ARG_DECL LV1_1_IN_ARG_DECL, LV1_3_OUT_ARG_DECL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define LV1_2_IN_3_OUT_ARG_DECL LV1_2_IN_ARG_DECL, LV1_3_OUT_ARG_DECL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define LV1_3_IN_3_OUT_ARG_DECL LV1_3_IN_ARG_DECL, LV1_3_OUT_ARG_DECL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define LV1_4_IN_3_OUT_ARG_DECL LV1_4_IN_ARG_DECL, LV1_3_OUT_ARG_DECL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define LV1_5_IN_3_OUT_ARG_DECL LV1_5_IN_ARG_DECL, LV1_3_OUT_ARG_DECL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define LV1_6_IN_3_OUT_ARG_DECL LV1_6_IN_ARG_DECL, LV1_3_OUT_ARG_DECL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define LV1_7_IN_3_OUT_ARG_DECL LV1_7_IN_ARG_DECL, LV1_3_OUT_ARG_DECL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define LV1_0_IN_4_OUT_ARG_DECL LV1_4_OUT_ARG_DECL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define LV1_1_IN_4_OUT_ARG_DECL LV1_1_IN_ARG_DECL, LV1_4_OUT_ARG_DECL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define LV1_2_IN_4_OUT_ARG_DECL LV1_2_IN_ARG_DECL, LV1_4_OUT_ARG_DECL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define LV1_3_IN_4_OUT_ARG_DECL LV1_3_IN_ARG_DECL, LV1_4_OUT_ARG_DECL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define LV1_4_IN_4_OUT_ARG_DECL LV1_4_IN_ARG_DECL, LV1_4_OUT_ARG_DECL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define LV1_5_IN_4_OUT_ARG_DECL LV1_5_IN_ARG_DECL, LV1_4_OUT_ARG_DECL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define LV1_6_IN_4_OUT_ARG_DECL LV1_6_IN_ARG_DECL, LV1_4_OUT_ARG_DECL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define LV1_7_IN_4_OUT_ARG_DECL LV1_7_IN_ARG_DECL, LV1_4_OUT_ARG_DECL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define LV1_0_IN_5_OUT_ARG_DECL LV1_5_OUT_ARG_DECL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define LV1_1_IN_5_OUT_ARG_DECL LV1_1_IN_ARG_DECL, LV1_5_OUT_ARG_DECL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define LV1_2_IN_5_OUT_ARG_DECL LV1_2_IN_ARG_DECL, LV1_5_OUT_ARG_DECL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define LV1_3_IN_5_OUT_ARG_DECL LV1_3_IN_ARG_DECL, LV1_5_OUT_ARG_DECL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define LV1_4_IN_5_OUT_ARG_DECL LV1_4_IN_ARG_DECL, LV1_5_OUT_ARG_DECL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define LV1_5_IN_5_OUT_ARG_DECL LV1_5_IN_ARG_DECL, LV1_5_OUT_ARG_DECL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define LV1_6_IN_5_OUT_ARG_DECL LV1_6_IN_ARG_DECL, LV1_5_OUT_ARG_DECL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define LV1_7_IN_5_OUT_ARG_DECL LV1_7_IN_ARG_DECL, LV1_5_OUT_ARG_DECL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define LV1_0_IN_6_OUT_ARG_DECL LV1_6_OUT_ARG_DECL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define LV1_1_IN_6_OUT_ARG_DECL LV1_1_IN_ARG_DECL, LV1_6_OUT_ARG_DECL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define LV1_2_IN_6_OUT_ARG_DECL LV1_2_IN_ARG_DECL, LV1_6_OUT_ARG_DECL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define LV1_3_IN_6_OUT_ARG_DECL LV1_3_IN_ARG_DECL, LV1_6_OUT_ARG_DECL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define LV1_4_IN_6_OUT_ARG_DECL LV1_4_IN_ARG_DECL, LV1_6_OUT_ARG_DECL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define LV1_5_IN_6_OUT_ARG_DECL LV1_5_IN_ARG_DECL, LV1_6_OUT_ARG_DECL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define LV1_6_IN_6_OUT_ARG_DECL LV1_6_IN_ARG_DECL, LV1_6_OUT_ARG_DECL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define LV1_7_IN_6_OUT_ARG_DECL LV1_7_IN_ARG_DECL, LV1_6_OUT_ARG_DECL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define LV1_0_IN_7_OUT_ARG_DECL LV1_7_OUT_ARG_DECL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define LV1_1_IN_7_OUT_ARG_DECL LV1_1_IN_ARG_DECL, LV1_7_OUT_ARG_DECL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define LV1_2_IN_7_OUT_ARG_DECL LV1_2_IN_ARG_DECL, LV1_7_OUT_ARG_DECL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define LV1_3_IN_7_OUT_ARG_DECL LV1_3_IN_ARG_DECL, LV1_7_OUT_ARG_DECL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define LV1_4_IN_7_OUT_ARG_DECL LV1_4_IN_ARG_DECL, LV1_7_OUT_ARG_DECL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define LV1_5_IN_7_OUT_ARG_DECL LV1_5_IN_ARG_DECL, LV1_7_OUT_ARG_DECL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define LV1_6_IN_7_OUT_ARG_DECL LV1_6_IN_ARG_DECL, LV1_7_OUT_ARG_DECL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define LV1_7_IN_7_OUT_ARG_DECL LV1_7_IN_ARG_DECL, LV1_7_OUT_ARG_DECL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define LV1_1_IN_ARGS in_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define LV1_2_IN_ARGS LV1_1_IN_ARGS, in_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define LV1_3_IN_ARGS LV1_2_IN_ARGS, in_3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define LV1_4_IN_ARGS LV1_3_IN_ARGS, in_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define LV1_5_IN_ARGS LV1_4_IN_ARGS, in_5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define LV1_6_IN_ARGS LV1_5_IN_ARGS, in_6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define LV1_7_IN_ARGS LV1_6_IN_ARGS, in_7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define LV1_8_IN_ARGS LV1_7_IN_ARGS, in_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define LV1_1_OUT_ARGS out_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define LV1_2_OUT_ARGS LV1_1_OUT_ARGS, out_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define LV1_3_OUT_ARGS LV1_2_OUT_ARGS, out_3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define LV1_4_OUT_ARGS LV1_3_OUT_ARGS, out_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define LV1_5_OUT_ARGS LV1_4_OUT_ARGS, out_5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define LV1_6_OUT_ARGS LV1_5_OUT_ARGS, out_6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define LV1_7_OUT_ARGS LV1_6_OUT_ARGS, out_7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define LV1_0_IN_0_OUT_ARGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define LV1_1_IN_0_OUT_ARGS LV1_1_IN_ARGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define LV1_2_IN_0_OUT_ARGS LV1_2_IN_ARGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define LV1_3_IN_0_OUT_ARGS LV1_3_IN_ARGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define LV1_4_IN_0_OUT_ARGS LV1_4_IN_ARGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define LV1_5_IN_0_OUT_ARGS LV1_5_IN_ARGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define LV1_6_IN_0_OUT_ARGS LV1_6_IN_ARGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define LV1_7_IN_0_OUT_ARGS LV1_7_IN_ARGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define LV1_0_IN_1_OUT_ARGS LV1_1_OUT_ARGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define LV1_1_IN_1_OUT_ARGS LV1_1_IN_ARGS, LV1_1_OUT_ARGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define LV1_2_IN_1_OUT_ARGS LV1_2_IN_ARGS, LV1_1_OUT_ARGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define LV1_3_IN_1_OUT_ARGS LV1_3_IN_ARGS, LV1_1_OUT_ARGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define LV1_4_IN_1_OUT_ARGS LV1_4_IN_ARGS, LV1_1_OUT_ARGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define LV1_5_IN_1_OUT_ARGS LV1_5_IN_ARGS, LV1_1_OUT_ARGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define LV1_6_IN_1_OUT_ARGS LV1_6_IN_ARGS, LV1_1_OUT_ARGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define LV1_7_IN_1_OUT_ARGS LV1_7_IN_ARGS, LV1_1_OUT_ARGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define LV1_8_IN_1_OUT_ARGS LV1_8_IN_ARGS, LV1_1_OUT_ARGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define LV1_0_IN_2_OUT_ARGS LV1_2_OUT_ARGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define LV1_1_IN_2_OUT_ARGS LV1_1_IN_ARGS, LV1_2_OUT_ARGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define LV1_2_IN_2_OUT_ARGS LV1_2_IN_ARGS, LV1_2_OUT_ARGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define LV1_3_IN_2_OUT_ARGS LV1_3_IN_ARGS, LV1_2_OUT_ARGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define LV1_4_IN_2_OUT_ARGS LV1_4_IN_ARGS, LV1_2_OUT_ARGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define LV1_5_IN_2_OUT_ARGS LV1_5_IN_ARGS, LV1_2_OUT_ARGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define LV1_6_IN_2_OUT_ARGS LV1_6_IN_ARGS, LV1_2_OUT_ARGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define LV1_7_IN_2_OUT_ARGS LV1_7_IN_ARGS, LV1_2_OUT_ARGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define LV1_0_IN_3_OUT_ARGS LV1_3_OUT_ARGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define LV1_1_IN_3_OUT_ARGS LV1_1_IN_ARGS, LV1_3_OUT_ARGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define LV1_2_IN_3_OUT_ARGS LV1_2_IN_ARGS, LV1_3_OUT_ARGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define LV1_3_IN_3_OUT_ARGS LV1_3_IN_ARGS, LV1_3_OUT_ARGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define LV1_4_IN_3_OUT_ARGS LV1_4_IN_ARGS, LV1_3_OUT_ARGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define LV1_5_IN_3_OUT_ARGS LV1_5_IN_ARGS, LV1_3_OUT_ARGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define LV1_6_IN_3_OUT_ARGS LV1_6_IN_ARGS, LV1_3_OUT_ARGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define LV1_7_IN_3_OUT_ARGS LV1_7_IN_ARGS, LV1_3_OUT_ARGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define LV1_0_IN_4_OUT_ARGS LV1_4_OUT_ARGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define LV1_1_IN_4_OUT_ARGS LV1_1_IN_ARGS, LV1_4_OUT_ARGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define LV1_2_IN_4_OUT_ARGS LV1_2_IN_ARGS, LV1_4_OUT_ARGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define LV1_3_IN_4_OUT_ARGS LV1_3_IN_ARGS, LV1_4_OUT_ARGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define LV1_4_IN_4_OUT_ARGS LV1_4_IN_ARGS, LV1_4_OUT_ARGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define LV1_5_IN_4_OUT_ARGS LV1_5_IN_ARGS, LV1_4_OUT_ARGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define LV1_6_IN_4_OUT_ARGS LV1_6_IN_ARGS, LV1_4_OUT_ARGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define LV1_7_IN_4_OUT_ARGS LV1_7_IN_ARGS, LV1_4_OUT_ARGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define LV1_0_IN_5_OUT_ARGS LV1_5_OUT_ARGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define LV1_1_IN_5_OUT_ARGS LV1_1_IN_ARGS, LV1_5_OUT_ARGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define LV1_2_IN_5_OUT_ARGS LV1_2_IN_ARGS, LV1_5_OUT_ARGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define LV1_3_IN_5_OUT_ARGS LV1_3_IN_ARGS, LV1_5_OUT_ARGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define LV1_4_IN_5_OUT_ARGS LV1_4_IN_ARGS, LV1_5_OUT_ARGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define LV1_5_IN_5_OUT_ARGS LV1_5_IN_ARGS, LV1_5_OUT_ARGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define LV1_6_IN_5_OUT_ARGS LV1_6_IN_ARGS, LV1_5_OUT_ARGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define LV1_7_IN_5_OUT_ARGS LV1_7_IN_ARGS, LV1_5_OUT_ARGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define LV1_0_IN_6_OUT_ARGS LV1_6_OUT_ARGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define LV1_1_IN_6_OUT_ARGS LV1_1_IN_ARGS, LV1_6_OUT_ARGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define LV1_2_IN_6_OUT_ARGS LV1_2_IN_ARGS, LV1_6_OUT_ARGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define LV1_3_IN_6_OUT_ARGS LV1_3_IN_ARGS, LV1_6_OUT_ARGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define LV1_4_IN_6_OUT_ARGS LV1_4_IN_ARGS, LV1_6_OUT_ARGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define LV1_5_IN_6_OUT_ARGS LV1_5_IN_ARGS, LV1_6_OUT_ARGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define LV1_6_IN_6_OUT_ARGS LV1_6_IN_ARGS, LV1_6_OUT_ARGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define LV1_7_IN_6_OUT_ARGS LV1_7_IN_ARGS, LV1_6_OUT_ARGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define LV1_0_IN_7_OUT_ARGS LV1_7_OUT_ARGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define LV1_1_IN_7_OUT_ARGS LV1_1_IN_ARGS, LV1_7_OUT_ARGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define LV1_2_IN_7_OUT_ARGS LV1_2_IN_ARGS, LV1_7_OUT_ARGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define LV1_3_IN_7_OUT_ARGS LV1_3_IN_ARGS, LV1_7_OUT_ARGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define LV1_4_IN_7_OUT_ARGS LV1_4_IN_ARGS, LV1_7_OUT_ARGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define LV1_5_IN_7_OUT_ARGS LV1_5_IN_ARGS, LV1_7_OUT_ARGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define LV1_6_IN_7_OUT_ARGS LV1_6_IN_ARGS, LV1_7_OUT_ARGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define LV1_7_IN_7_OUT_ARGS LV1_7_IN_ARGS, LV1_7_OUT_ARGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * This LV1_CALL() macro is for use by callers. It expands into an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * inline call wrapper and an underscored HV call declaration. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * wrapper can be used to instrument the lv1 call interface. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * file lv1call.S defines its own LV1_CALL() macro to expand into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * the actual underscored call definition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #if !defined(LV1_CALL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define LV1_CALL(name, in, out, num) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) extern s64 _lv1_##name(LV1_##in##_IN_##out##_OUT_ARG_DECL); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static inline int lv1_##name(LV1_##in##_IN_##out##_OUT_ARG_DECL) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {return _lv1_##name(LV1_##in##_IN_##out##_OUT_ARGS);}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #endif /* !defined(__ASSEMBLY__) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* lv1 call table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) LV1_CALL(allocate_memory, 4, 2, 0 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) LV1_CALL(write_htab_entry, 4, 0, 1 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) LV1_CALL(construct_virtual_address_space, 3, 2, 2 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) LV1_CALL(invalidate_htab_entries, 5, 0, 3 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) LV1_CALL(get_virtual_address_space_id_of_ppe, 0, 1, 4 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) LV1_CALL(query_logical_partition_address_region_info, 1, 5, 6 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) LV1_CALL(select_virtual_address_space, 1, 0, 7 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) LV1_CALL(pause, 1, 0, 9 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) LV1_CALL(destruct_virtual_address_space, 1, 0, 10 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) LV1_CALL(configure_irq_state_bitmap, 3, 0, 11 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) LV1_CALL(connect_irq_plug_ext, 5, 0, 12 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) LV1_CALL(release_memory, 1, 0, 13 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) LV1_CALL(put_iopte, 5, 0, 15 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) LV1_CALL(disconnect_irq_plug_ext, 3, 0, 17 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) LV1_CALL(construct_event_receive_port, 0, 1, 18 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) LV1_CALL(destruct_event_receive_port, 1, 0, 19 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) LV1_CALL(send_event_locally, 1, 0, 24 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) LV1_CALL(end_of_interrupt, 1, 0, 27 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) LV1_CALL(connect_irq_plug, 2, 0, 28 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) LV1_CALL(disconnect_irq_plug, 1, 0, 29 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) LV1_CALL(end_of_interrupt_ext, 3, 0, 30 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) LV1_CALL(did_update_interrupt_mask, 2, 0, 31 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) LV1_CALL(shutdown_logical_partition, 1, 0, 44 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) LV1_CALL(destruct_logical_spe, 1, 0, 54 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) LV1_CALL(construct_logical_spe, 7, 6, 57 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) LV1_CALL(set_spe_interrupt_mask, 3, 0, 61 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) LV1_CALL(set_spe_transition_notifier, 3, 0, 64 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) LV1_CALL(disable_logical_spe, 2, 0, 65 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) LV1_CALL(clear_spe_interrupt_status, 4, 0, 66 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) LV1_CALL(get_spe_interrupt_status, 2, 1, 67 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) LV1_CALL(get_logical_ppe_id, 0, 1, 69 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) LV1_CALL(set_interrupt_mask, 5, 0, 73 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) LV1_CALL(get_logical_partition_id, 0, 1, 74 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) LV1_CALL(configure_execution_time_variable, 1, 0, 77 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) LV1_CALL(get_spe_irq_outlet, 2, 1, 78 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) LV1_CALL(set_spe_privilege_state_area_1_register, 3, 0, 79 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) LV1_CALL(create_repository_node, 6, 0, 90 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) LV1_CALL(read_repository_node, 5, 2, 91 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) LV1_CALL(write_repository_node, 6, 0, 92 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) LV1_CALL(delete_repository_node, 4, 0, 93 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) LV1_CALL(read_htab_entries, 2, 5, 95 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) LV1_CALL(set_dabr, 2, 0, 96 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) LV1_CALL(get_total_execution_time, 2, 1, 103 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) LV1_CALL(allocate_io_segment, 3, 1, 116 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) LV1_CALL(release_io_segment, 2, 0, 117 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) LV1_CALL(construct_io_irq_outlet, 1, 1, 120 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) LV1_CALL(destruct_io_irq_outlet, 1, 0, 121 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) LV1_CALL(map_htab, 1, 1, 122 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) LV1_CALL(unmap_htab, 1, 0, 123 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) LV1_CALL(get_version_info, 0, 2, 127 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) LV1_CALL(insert_htab_entry, 6, 3, 158 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) LV1_CALL(read_virtual_uart, 3, 1, 162 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) LV1_CALL(write_virtual_uart, 3, 1, 163 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) LV1_CALL(set_virtual_uart_param, 3, 0, 164 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) LV1_CALL(get_virtual_uart_param, 2, 1, 165 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) LV1_CALL(configure_virtual_uart_irq, 1, 1, 166 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) LV1_CALL(open_device, 3, 0, 170 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) LV1_CALL(close_device, 2, 0, 171 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) LV1_CALL(map_device_mmio_region, 5, 1, 172 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) LV1_CALL(unmap_device_mmio_region, 3, 0, 173 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) LV1_CALL(allocate_device_dma_region, 5, 1, 174 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) LV1_CALL(free_device_dma_region, 3, 0, 175 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) LV1_CALL(map_device_dma_region, 6, 0, 176 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) LV1_CALL(unmap_device_dma_region, 4, 0, 177 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) LV1_CALL(net_add_multicast_address, 4, 0, 185 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) LV1_CALL(net_remove_multicast_address, 4, 0, 186 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) LV1_CALL(net_start_tx_dma, 4, 0, 187 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) LV1_CALL(net_stop_tx_dma, 2, 0, 188 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) LV1_CALL(net_start_rx_dma, 4, 0, 189 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) LV1_CALL(net_stop_rx_dma, 2, 0, 190 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) LV1_CALL(net_set_interrupt_status_indicator, 4, 0, 191 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) LV1_CALL(net_set_interrupt_mask, 4, 0, 193 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) LV1_CALL(net_control, 6, 2, 194 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) LV1_CALL(connect_interrupt_event_receive_port, 4, 0, 197 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) LV1_CALL(disconnect_interrupt_event_receive_port, 4, 0, 198 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) LV1_CALL(get_spe_all_interrupt_statuses, 1, 1, 199 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) LV1_CALL(deconfigure_virtual_uart_irq, 0, 0, 202 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) LV1_CALL(enable_logical_spe, 2, 0, 207 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) LV1_CALL(gpu_open, 1, 0, 210 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) LV1_CALL(gpu_close, 0, 0, 211 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) LV1_CALL(gpu_device_map, 1, 2, 212 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) LV1_CALL(gpu_device_unmap, 1, 0, 213 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) LV1_CALL(gpu_memory_allocate, 5, 2, 214 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) LV1_CALL(gpu_memory_free, 1, 0, 216 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) LV1_CALL(gpu_context_allocate, 2, 5, 217 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) LV1_CALL(gpu_context_free, 1, 0, 218 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) LV1_CALL(gpu_context_iomap, 5, 0, 221 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) LV1_CALL(gpu_context_attribute, 6, 0, 225 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) LV1_CALL(gpu_context_intr, 1, 1, 227 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) LV1_CALL(gpu_attribute, 3, 0, 228 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) LV1_CALL(get_rtc, 0, 2, 232 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) LV1_CALL(set_ppe_periodic_tracer_frequency, 1, 0, 240 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) LV1_CALL(start_ppe_periodic_tracer, 5, 0, 241 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) LV1_CALL(stop_ppe_periodic_tracer, 1, 1, 242 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) LV1_CALL(storage_read, 6, 1, 245 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) LV1_CALL(storage_write, 6, 1, 246 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) LV1_CALL(storage_send_device_command, 6, 1, 248 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) LV1_CALL(storage_get_async_status, 1, 2, 249 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) LV1_CALL(storage_check_async_status, 2, 1, 254 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) LV1_CALL(panic, 1, 0, 255 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) LV1_CALL(construct_lpm, 6, 3, 140 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) LV1_CALL(destruct_lpm, 1, 0, 141 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) LV1_CALL(start_lpm, 1, 0, 142 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) LV1_CALL(stop_lpm, 1, 1, 143 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) LV1_CALL(copy_lpm_trace_buffer, 3, 1, 144 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) LV1_CALL(add_lpm_event_bookmark, 5, 0, 145 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) LV1_CALL(delete_lpm_event_bookmark, 3, 0, 146 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) LV1_CALL(set_lpm_interrupt_mask, 3, 1, 147 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) LV1_CALL(get_lpm_interrupt_status, 1, 1, 148 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) LV1_CALL(set_lpm_general_control, 5, 2, 149 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) LV1_CALL(set_lpm_interval, 3, 1, 150 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) LV1_CALL(set_lpm_trigger_control, 3, 1, 151 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) LV1_CALL(set_lpm_counter_control, 4, 1, 152 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) LV1_CALL(set_lpm_group_control, 3, 1, 153 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) LV1_CALL(set_lpm_debug_bus_control, 3, 1, 154 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) LV1_CALL(set_lpm_counter, 5, 2, 155 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) LV1_CALL(set_lpm_signal, 7, 0, 156 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) LV1_CALL(set_lpm_spr_trigger, 2, 0, 157 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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