Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) #ifndef _ASM_POWERPC_KEYLARGO_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) #define _ASM_POWERPC_KEYLARGO_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) #ifdef __KERNEL__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * keylargo.h: definitions for using the "KeyLargo" I/O controller chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) /* "Pangea" chipset has keylargo device-id 0x25 while core99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * has device-id 0x22. The rev. of the pangea one is 0, so we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * fake an artificial rev. in keylargo_rev by oring 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define KL_PANGEA_REV		0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) /* offset from base for feature control registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define KEYLARGO_MBCR		0x34	/* KL Only, Media bay control/status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define KEYLARGO_FCR0		0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define KEYLARGO_FCR1		0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define KEYLARGO_FCR2		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define KEYLARGO_FCR3		0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define KEYLARGO_FCR4		0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define KEYLARGO_FCR5		0x4c	/* Pangea only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) /* K2 additional FCRs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define K2_FCR6			0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define K2_FCR7			0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define K2_FCR8			0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define K2_FCR9			0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define K2_FCR10		0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) /* GPIO registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define KEYLARGO_GPIO_LEVELS0		0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define KEYLARGO_GPIO_LEVELS1		0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define KEYLARGO_GPIO_EXTINT_0		0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define KEYLARGO_GPIO_EXTINT_CNT	18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define KEYLARGO_GPIO_0			0x6A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define KEYLARGO_GPIO_CNT		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define KEYLARGO_GPIO_EXTINT_DUAL_EDGE	0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define KEYLARGO_GPIO_OUTPUT_ENABLE	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define KEYLARGO_GPIO_OUTOUT_DATA	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define KEYLARGO_GPIO_INPUT_DATA	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) /* K2 does only extint GPIOs and does 51 of them */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define K2_GPIO_EXTINT_0		0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define K2_GPIO_EXTINT_CNT		51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) /* Specific GPIO regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define KL_GPIO_MODEM_RESET		(KEYLARGO_GPIO_0+0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define KL_GPIO_MODEM_POWER		(KEYLARGO_GPIO_0+0x02) /* Pangea */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define KL_GPIO_SOUND_POWER		(KEYLARGO_GPIO_0+0x05)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) /* Hrm... this one is only to be used on Pismo. It seems to also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56)  * control the timebase enable on other machines. Still to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57)  * experimented... --BenH.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define KL_GPIO_FW_CABLE_POWER		(KEYLARGO_GPIO_0+0x09)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define KL_GPIO_TB_ENABLE		(KEYLARGO_GPIO_0+0x09)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define KL_GPIO_ETH_PHY_RESET		(KEYLARGO_GPIO_0+0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define KL_GPIO_EXTINT_CPU1		(KEYLARGO_GPIO_0+0x0a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define KL_GPIO_EXTINT_CPU1_ASSERT	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define KL_GPIO_EXTINT_CPU1_RELEASE	0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define KL_GPIO_RESET_CPU0		(KEYLARGO_GPIO_EXTINT_0+0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define KL_GPIO_RESET_CPU1		(KEYLARGO_GPIO_EXTINT_0+0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define KL_GPIO_RESET_CPU2		(KEYLARGO_GPIO_EXTINT_0+0x0f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define KL_GPIO_RESET_CPU3		(KEYLARGO_GPIO_EXTINT_0+0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define KL_GPIO_PMU_MESSAGE_IRQ		(KEYLARGO_GPIO_EXTINT_0+0x09)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define KL_GPIO_PMU_MESSAGE_BIT		KEYLARGO_GPIO_INPUT_DATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define KL_GPIO_MEDIABAY_IRQ		(KEYLARGO_GPIO_EXTINT_0+0x0e)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define KL_GPIO_AIRPORT_0		(KEYLARGO_GPIO_EXTINT_0+0x0a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define KL_GPIO_AIRPORT_1		(KEYLARGO_GPIO_EXTINT_0+0x0d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define KL_GPIO_AIRPORT_2		(KEYLARGO_GPIO_0+0x0d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define KL_GPIO_AIRPORT_3		(KEYLARGO_GPIO_0+0x0e)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define KL_GPIO_AIRPORT_4		(KEYLARGO_GPIO_0+0x0f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85)  * Bits in feature control register. Those bits different for K2 are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86)  * listed separately
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define KL_MBCR_MB0_PCI_ENABLE		0x00000800	/* exist ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define KL_MBCR_MB0_IDE_ENABLE		0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define KL_MBCR_MB0_FLOPPY_ENABLE	0x00002000	/* exist ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define KL_MBCR_MB0_SOUND_ENABLE	0x00004000	/* hrm... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define KL_MBCR_MB0_DEV_MASK		0x00007800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define KL_MBCR_MB0_DEV_POWER		0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define KL_MBCR_MB0_DEV_RESET		0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define KL_MBCR_MB0_ENABLE		0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define KL_MBCR_MB1_PCI_ENABLE		0x08000000	/* exist ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define KL_MBCR_MB1_IDE_ENABLE		0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define KL_MBCR_MB1_FLOPPY_ENABLE	0x20000000	/* exist ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define KL_MBCR_MB1_SOUND_ENABLE	0x40000000	/* hrm... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define KL_MBCR_MB1_DEV_MASK		0x78000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define KL_MBCR_MB1_DEV_POWER		0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define KL_MBCR_MB1_DEV_RESET		0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define KL_MBCR_MB1_ENABLE		0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define KL0_SCC_B_INTF_ENABLE		0x00000001	/* (KL Only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define KL0_SCC_A_INTF_ENABLE		0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define KL0_SCC_SLOWPCLK		0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define KL0_SCC_RESET			0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define KL0_SCCA_ENABLE			0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define KL0_SCCB_ENABLE			0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define KL0_SCC_CELL_ENABLE		0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define KL0_IRDA_HIGH_BAND		0x00000100	/* (KL Only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define KL0_IRDA_SOURCE2_SEL		0x00000200	/* (KL Only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define KL0_IRDA_SOURCE1_SEL		0x00000400	/* (KL Only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define KL0_PG_USB0_PMI_ENABLE		0x00000400	/* (Pangea/Intrepid Only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define KL0_IRDA_RESET			0x00000800	/* (KL Only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define KL0_PG_USB0_REF_SUSPEND_SEL	0x00000800	/* (Pangea/Intrepid Only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define KL0_IRDA_DEFAULT1		0x00001000	/* (KL Only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define KL0_PG_USB0_REF_SUSPEND		0x00001000	/* (Pangea/Intrepid Only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define KL0_IRDA_DEFAULT0		0x00002000	/* (KL Only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define KL0_PG_USB0_PAD_SUSPEND		0x00002000	/* (Pangea/Intrepid Only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define KL0_IRDA_FAST_CONNECT		0x00004000	/* (KL Only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define KL0_PG_USB1_PMI_ENABLE		0x00004000	/* (Pangea/Intrepid Only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define KL0_IRDA_ENABLE			0x00008000	/* (KL Only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define KL0_PG_USB1_REF_SUSPEND_SEL	0x00008000	/* (Pangea/Intrepid Only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define KL0_IRDA_CLK32_ENABLE		0x00010000	/* (KL Only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define KL0_PG_USB1_REF_SUSPEND		0x00010000	/* (Pangea/Intrepid Only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define KL0_IRDA_CLK19_ENABLE		0x00020000	/* (KL Only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define KL0_PG_USB1_PAD_SUSPEND		0x00020000	/* (Pangea/Intrepid Only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define KL0_USB0_PAD_SUSPEND0		0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define KL0_USB0_PAD_SUSPEND1		0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define KL0_USB0_CELL_ENABLE		0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define KL0_USB1_PAD_SUSPEND0		0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define KL0_USB1_PAD_SUSPEND1		0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define KL0_USB1_CELL_ENABLE		0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define KL0_USB_REF_SUSPEND		0x10000000	/* (KL Only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define KL0_SERIAL_ENABLE		(KL0_SCC_B_INTF_ENABLE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 					KL0_SCC_SLOWPCLK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 					KL0_SCC_CELL_ENABLE | KL0_SCCA_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define KL1_USB2_PMI_ENABLE		0x00000001	/* Intrepid only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define KL1_AUDIO_SEL_22MCLK		0x00000002	/* KL/Pangea only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define KL1_USB2_REF_SUSPEND_SEL	0x00000002	/* Intrepid only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define KL1_USB2_REF_SUSPEND		0x00000004	/* Intrepid only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define KL1_AUDIO_CLK_ENABLE_BIT	0x00000008	/* KL/Pangea only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define KL1_USB2_PAD_SUSPEND_SEL	0x00000008	/* Intrepid only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define KL1_USB2_PAD_SUSPEND0		0x00000010	/* Intrepid only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define KL1_AUDIO_CLK_OUT_ENABLE	0x00000020	/* KL/Pangea only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define KL1_USB2_PAD_SUSPEND1		0x00000020	/* Intrepid only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define KL1_AUDIO_CELL_ENABLE		0x00000040	/* KL/Pangea only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define KL1_USB2_CELL_ENABLE		0x00000040	/* Intrepid only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define KL1_AUDIO_CHOOSE		0x00000080	/* KL/Pangea only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define KL1_I2S0_CHOOSE			0x00000200	/* KL Only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define KL1_I2S0_CELL_ENABLE		0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define KL1_I2S0_CLK_ENABLE_BIT		0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define KL1_I2S0_ENABLE			0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define KL1_I2S1_CELL_ENABLE		0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define KL1_I2S1_CLK_ENABLE_BIT		0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define KL1_I2S1_ENABLE			0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define KL1_EIDE0_ENABLE		0x00800000	/* KL/Intrepid Only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define KL1_EIDE0_RESET_N		0x01000000	/* KL/Intrepid Only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define KL1_EIDE1_ENABLE		0x04000000	/* KL Only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define KL1_EIDE1_RESET_N		0x08000000	/* KL Only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define KL1_UIDE_ENABLE			0x20000000	/* KL/Pangea Only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define KL1_UIDE_RESET_N		0x40000000	/* KL/Pangea Only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define KL2_IOBUS_ENABLE		0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define KL2_SLEEP_STATE_BIT		0x00000100	/* KL Only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define KL2_PG_STOP_ALL_CLOCKS		0x00000100	/* Pangea Only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define KL2_MPIC_ENABLE			0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define KL2_CARDSLOT_RESET		0x00040000	/* Pangea/Intrepid Only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define KL2_ALT_DATA_OUT		0x02000000	/* KL Only ??? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define KL2_MEM_IS_BIG			0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define KL2_CARDSEL_16			0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define KL3_SHUTDOWN_PLL_TOTAL		0x00000001	/* KL/Pangea only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define KL3_SHUTDOWN_PLLKW6		0x00000002	/* KL/Pangea only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define KL3_IT_SHUTDOWN_PLL3		0x00000002	/* Intrepid only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define KL3_SHUTDOWN_PLLKW4		0x00000004	/* KL/Pangea only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define KL3_IT_SHUTDOWN_PLL2		0x00000004	/* Intrepid only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define KL3_SHUTDOWN_PLLKW35		0x00000008	/* KL/Pangea only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define KL3_IT_SHUTDOWN_PLL1		0x00000008	/* Intrepid only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define KL3_SHUTDOWN_PLLKW12		0x00000010	/* KL Only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define KL3_IT_ENABLE_PLL3_SHUTDOWN	0x00000010	/* Intrepid only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define KL3_PLL_RESET			0x00000020	/* KL/Pangea only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define KL3_IT_ENABLE_PLL2_SHUTDOWN	0x00000020	/* Intrepid only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define KL3_IT_ENABLE_PLL1_SHUTDOWN	0x00000010	/* Intrepid only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define KL3_SHUTDOWN_PLL2X		0x00000080	/* KL Only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define KL3_CLK66_ENABLE		0x00000100	/* KL Only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define KL3_CLK49_ENABLE		0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define KL3_CLK45_ENABLE		0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define KL3_CLK31_ENABLE		0x00000800	/* KL/Pangea only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define KL3_TIMER_CLK18_ENABLE		0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define KL3_I2S1_CLK18_ENABLE		0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define KL3_I2S0_CLK18_ENABLE		0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define KL3_VIA_CLK16_ENABLE		0x00008000	/* KL/Pangea only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define KL3_IT_VIA_CLK32_ENABLE		0x00008000	/* Intrepid only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define KL3_STOPPING33_ENABLED		0x00080000	/* KL Only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define KL3_PG_PLL_ENABLE_TEST		0x00080000	/* Pangea Only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* Intrepid USB bus 2, port 0,1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define KL3_IT_PORT_WAKEUP_ENABLE(p)		(0x00080000 << ((p)<<3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define KL3_IT_PORT_RESUME_WAKE_EN(p)		(0x00040000 << ((p)<<3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define KL3_IT_PORT_CONNECT_WAKE_EN(p)		(0x00020000 << ((p)<<3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define KL3_IT_PORT_DISCONNECT_WAKE_EN(p)	(0x00010000 << ((p)<<3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define KL3_IT_PORT_RESUME_STAT(p)		(0x00300000 << ((p)<<3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define KL3_IT_PORT_CONNECT_STAT(p)		(0x00200000 << ((p)<<3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define KL3_IT_PORT_DISCONNECT_STAT(p)		(0x00100000 << ((p)<<3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* Port 0,1 : bus 0, port 2,3 : bus 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define KL4_PORT_WAKEUP_ENABLE(p)	(0x00000008 << ((p)<<3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define KL4_PORT_RESUME_WAKE_EN(p)	(0x00000004 << ((p)<<3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define KL4_PORT_CONNECT_WAKE_EN(p)	(0x00000002 << ((p)<<3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define KL4_PORT_DISCONNECT_WAKE_EN(p)	(0x00000001 << ((p)<<3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define KL4_PORT_RESUME_STAT(p)		(0x00000040 << ((p)<<3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define KL4_PORT_CONNECT_STAT(p)	(0x00000020 << ((p)<<3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define KL4_PORT_DISCONNECT_STAT(p)	(0x00000010 << ((p)<<3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* Pangea and Intrepid only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define KL5_VIA_USE_CLK31		0000000001	/* Pangea Only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define KL5_SCC_USE_CLK31		0x00000002	/* Pangea Only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define KL5_PWM_CLK32_EN		0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define KL5_CLK3_68_EN			0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define KL5_CLK32_EN			0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* K2 definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define K2_FCR0_USB0_SWRESET		0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define K2_FCR0_USB1_SWRESET		0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define K2_FCR0_RING_PME_DISABLE	0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define K2_FCR1_PCI1_BUS_RESET_N	0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define K2_FCR1_PCI1_SLEEP_RESET_EN	0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define K2_FCR1_I2S0_CELL_ENABLE	0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define K2_FCR1_I2S0_RESET		0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define K2_FCR1_I2S0_CLK_ENABLE_BIT	0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define K2_FCR1_I2S0_ENABLE    		0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define K2_FCR1_PCI1_CLK_ENABLE		0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define K2_FCR1_FW_CLK_ENABLE		0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define K2_FCR1_FW_RESET_N		0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define K2_FCR1_I2S1_CELL_ENABLE	0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define K2_FCR1_I2S1_CLK_ENABLE_BIT	0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define K2_FCR1_I2S1_ENABLE		0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define K2_FCR1_GMAC_CLK_ENABLE		0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define K2_FCR1_GMAC_POWER_DOWN		0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define K2_FCR1_GMAC_RESET_N		0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define K2_FCR1_SATA_CLK_ENABLE		0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define K2_FCR1_SATA_POWER_DOWN		0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define K2_FCR1_SATA_RESET_N		0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define K2_FCR1_UATA_CLK_ENABLE		0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define K2_FCR1_UATA_RESET_N		0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define K2_FCR1_UATA_CHOOSE_CLK66	0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* Shasta definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define SH_FCR1_I2S2_CELL_ENABLE	0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define SH_FCR1_I2S2_CLK_ENABLE_BIT	0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define SH_FCR1_I2S2_ENABLE		0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define SH_FCR3_I2S2_CLK18_ENABLE	0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #endif /* __KERNEL__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #endif /* _ASM_POWERPC_KEYLARGO_H */