Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Rewrite, cleanup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #ifndef _ASM_IOMMU_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define _ASM_IOMMU_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #ifdef __KERNEL__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/compiler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/dma-map-ops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <asm/machdep.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <asm/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <asm/pci-bridge.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <asm/asm-const.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define IOMMU_PAGE_SHIFT_4K      12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define IOMMU_PAGE_SIZE_4K       (ASM_CONST(1) << IOMMU_PAGE_SHIFT_4K)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define IOMMU_PAGE_MASK_4K       (~((1 << IOMMU_PAGE_SHIFT_4K) - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define IOMMU_PAGE_ALIGN_4K(addr) ALIGN(addr, IOMMU_PAGE_SIZE_4K)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define IOMMU_PAGE_SIZE(tblptr) (ASM_CONST(1) << (tblptr)->it_page_shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define IOMMU_PAGE_MASK(tblptr) (~((1 << (tblptr)->it_page_shift) - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define IOMMU_PAGE_ALIGN(addr, tblptr) ALIGN(addr, IOMMU_PAGE_SIZE(tblptr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) /* Boot time flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) extern int iommu_is_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) extern int iommu_force_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) struct iommu_table_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	 * When called with direction==DMA_NONE, it is equal to clear().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	 * uaddr is a linear map address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	int (*set)(struct iommu_table *tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 			long index, long npages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 			unsigned long uaddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 			enum dma_data_direction direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 			unsigned long attrs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #ifdef CONFIG_IOMMU_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	 * Exchanges existing TCE with new TCE plus direction bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	 * returns old TCE and DMA direction mask.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	 * @tce is a physical address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	int (*xchg_no_kill)(struct iommu_table *tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 			long index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 			unsigned long *hpa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 			enum dma_data_direction *direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 			bool realmode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	void (*tce_kill)(struct iommu_table *tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 			unsigned long index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 			unsigned long pages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 			bool realmode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	__be64 *(*useraddrptr)(struct iommu_table *tbl, long index, bool alloc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	void (*clear)(struct iommu_table *tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 			long index, long npages);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	/* get() returns a physical address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	unsigned long (*get)(struct iommu_table *tbl, long index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	void (*flush)(struct iommu_table *tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	void (*free)(struct iommu_table *tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) /* These are used by VIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) extern struct iommu_table_ops iommu_table_lpar_multi_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) extern struct iommu_table_ops iommu_table_pseries_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77)  * IOMAP_MAX_ORDER defines the largest contiguous block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78)  * of dma space we can get.  IOMAP_MAX_ORDER = 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79)  * allows up to 2**12 pages (4096 * 4096) = 16 MB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define IOMAP_MAX_ORDER		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define IOMMU_POOL_HASHBITS	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define IOMMU_NR_POOLS		(1 << IOMMU_POOL_HASHBITS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) struct iommu_pool {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	unsigned long start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	unsigned long end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	unsigned long hint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) } ____cacheline_aligned_in_smp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) struct iommu_table {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	unsigned long  it_busno;     /* Bus number this table belongs to */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	unsigned long  it_size;      /* Size of iommu table in entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	unsigned long  it_indirect_levels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	unsigned long  it_level_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	unsigned long  it_allocated_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	unsigned long  it_offset;    /* Offset into global table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	unsigned long  it_base;      /* mapped address of tce table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	unsigned long  it_index;     /* which iommu table this is */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	unsigned long  it_type;      /* type: PCI or Virtual Bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	unsigned long  it_blocksize; /* Entries in each block (cacheline) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	unsigned long  poolsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	unsigned long  nr_pools;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	struct iommu_pool large_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	struct iommu_pool pools[IOMMU_NR_POOLS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	unsigned long *it_map;       /* A simple allocation bitmap for now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	unsigned long  it_page_shift;/* table iommu page size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	struct list_head it_group_list;/* List of iommu_table_group_link */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	__be64 *it_userspace; /* userspace view of the table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	struct iommu_table_ops *it_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	struct kref    it_kref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	int it_nid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	unsigned long it_reserved_start; /* Start of not-DMA-able (MMIO) area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	unsigned long it_reserved_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define IOMMU_TABLE_USERSPACE_ENTRY_RO(tbl, entry) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		((tbl)->it_ops->useraddrptr((tbl), (entry), false))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define IOMMU_TABLE_USERSPACE_ENTRY(tbl, entry) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		((tbl)->it_ops->useraddrptr((tbl), (entry), true))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* Pure 2^n version of get_order */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static inline __attribute_const__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) int get_iommu_order(unsigned long size, struct iommu_table *tbl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	return __ilog2((size - 1) >> tbl->it_page_shift) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct scatterlist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #ifdef CONFIG_PPC64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static inline void set_iommu_table_base(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 					struct iommu_table *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	dev->archdata.iommu_table_base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static inline void *get_iommu_table_base(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	return dev->archdata.iommu_table_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) extern int dma_iommu_dma_supported(struct device *dev, u64 mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) extern struct iommu_table *iommu_tce_table_get(struct iommu_table *tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) extern int iommu_tce_table_put(struct iommu_table *tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* Initializes an iommu_table based in values set in the passed-in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)  * structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) extern struct iommu_table *iommu_init_table(struct iommu_table *tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		int nid, unsigned long res_start, unsigned long res_end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define IOMMU_TABLE_GROUP_MAX_TABLES	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct iommu_table_group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct iommu_table_group_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	unsigned long (*get_table_size)(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 			__u32 page_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 			__u64 window_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 			__u32 levels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	long (*create_table)(struct iommu_table_group *table_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 			int num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 			__u32 page_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 			__u64 window_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 			__u32 levels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 			struct iommu_table **ptbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	long (*set_window)(struct iommu_table_group *table_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 			int num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 			struct iommu_table *tblnew);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	long (*unset_window)(struct iommu_table_group *table_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 			int num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	/* Switch ownership from platform code to external user (e.g. VFIO) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	void (*take_ownership)(struct iommu_table_group *table_group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	/* Switch ownership from external user (e.g. VFIO) back to core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	void (*release_ownership)(struct iommu_table_group *table_group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct iommu_table_group_link {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	struct list_head next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	struct rcu_head rcu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	struct iommu_table_group *table_group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct iommu_table_group {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	/* IOMMU properties */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	__u32 tce32_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	__u32 tce32_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	__u64 pgsizes; /* Bitmap of supported page sizes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	__u32 max_dynamic_windows_supported;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	__u32 max_levels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	struct iommu_group *group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	struct iommu_table *tables[IOMMU_TABLE_GROUP_MAX_TABLES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	struct iommu_table_group_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #ifdef CONFIG_IOMMU_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) extern void iommu_register_group(struct iommu_table_group *table_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 				 int pci_domain_number, unsigned long pe_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) extern int iommu_add_device(struct iommu_table_group *table_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) extern void iommu_del_device(struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) extern long iommu_tce_xchg(struct mm_struct *mm, struct iommu_table *tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		unsigned long entry, unsigned long *hpa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		enum dma_data_direction *direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) extern long iommu_tce_xchg_no_kill(struct mm_struct *mm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		struct iommu_table *tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		unsigned long entry, unsigned long *hpa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		enum dma_data_direction *direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) extern void iommu_tce_kill(struct iommu_table *tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		unsigned long entry, unsigned long pages);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static inline void iommu_register_group(struct iommu_table_group *table_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 					int pci_domain_number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 					unsigned long pe_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static inline int iommu_add_device(struct iommu_table_group *table_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static inline void iommu_del_device(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #endif /* !CONFIG_IOMMU_API */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) u64 dma_iommu_get_required_mask(struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static inline void *get_iommu_table_base(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static inline int dma_iommu_dma_supported(struct device *dev, u64 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #endif /* CONFIG_PPC64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) extern int ppc_iommu_map_sg(struct device *dev, struct iommu_table *tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 			    struct scatterlist *sglist, int nelems,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 			    unsigned long mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 			    enum dma_data_direction direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 			    unsigned long attrs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) extern void ppc_iommu_unmap_sg(struct iommu_table *tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 			       struct scatterlist *sglist,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 			       int nelems,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 			       enum dma_data_direction direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 			       unsigned long attrs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) extern void *iommu_alloc_coherent(struct device *dev, struct iommu_table *tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 				  size_t size, dma_addr_t *dma_handle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 				  unsigned long mask, gfp_t flag, int node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) extern void iommu_free_coherent(struct iommu_table *tbl, size_t size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 				void *vaddr, dma_addr_t dma_handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) extern dma_addr_t iommu_map_page(struct device *dev, struct iommu_table *tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 				 struct page *page, unsigned long offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 				 size_t size, unsigned long mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 				 enum dma_data_direction direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 				 unsigned long attrs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) extern void iommu_unmap_page(struct iommu_table *tbl, dma_addr_t dma_handle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 			     size_t size, enum dma_data_direction direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 			     unsigned long attrs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) extern void iommu_init_early_pSeries(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) extern void iommu_init_early_dart(struct pci_controller_ops *controller_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) extern void iommu_init_early_pasemi(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #if defined(CONFIG_PPC64) && defined(CONFIG_PM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static inline void iommu_save(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	if (ppc_md.iommu_save)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		ppc_md.iommu_save();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static inline void iommu_restore(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	if (ppc_md.iommu_restore)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		ppc_md.iommu_restore();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /* The API to support IOMMU operations for VFIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) extern int iommu_tce_check_ioba(unsigned long page_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		unsigned long offset, unsigned long size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		unsigned long ioba, unsigned long npages);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) extern int iommu_tce_check_gpa(unsigned long page_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		unsigned long gpa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define iommu_tce_clear_param_check(tbl, ioba, tce_value, npages) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		(iommu_tce_check_ioba((tbl)->it_page_shift,       \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 				(tbl)->it_offset, (tbl)->it_size, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 				(ioba), (npages)) || (tce_value))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define iommu_tce_put_param_check(tbl, ioba, gpa)                 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		(iommu_tce_check_ioba((tbl)->it_page_shift,       \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 				(tbl)->it_offset, (tbl)->it_size, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 				(ioba), 1) ||                     \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		iommu_tce_check_gpa((tbl)->it_page_shift, (gpa)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) extern void iommu_flush_tce(struct iommu_table *tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) extern int iommu_take_ownership(struct iommu_table *tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) extern void iommu_release_ownership(struct iommu_table *tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) extern enum dma_data_direction iommu_tce_direction(unsigned long tce);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) extern unsigned long iommu_direction_to_tce_perm(enum dma_data_direction dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #ifdef CONFIG_PPC_CELL_NATIVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) extern bool iommu_fixed_is_weak;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define iommu_fixed_is_weak false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) extern const struct dma_map_ops dma_iommu_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #endif /* __KERNEL__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #endif /* _ASM_IOMMU_H */