^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef _ASM_POWERPC_IO_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define _ASM_POWERPC_IO_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #ifdef __KERNEL__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #define ARCH_HAS_IOREMAP_WC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifdef CONFIG_PPC32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define ARCH_HAS_IOREMAP_WT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /* Check of existence of legacy devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) extern int check_legacy_ioport(unsigned long base_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define I8042_DATA_REG 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define FDC_BASE 0x3f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #if defined(CONFIG_PPC64) && defined(CONFIG_PCI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) extern struct pci_dev *isa_bridge_pcidev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * has legacy ISA devices ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define arch_has_dev_port() (isa_bridge_pcidev != NULL || isa_io_special)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/compiler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <asm/byteorder.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <asm/synch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <asm/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <asm/mmiowb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <asm/mmu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <asm/ppc_asm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SIO_CONFIG_RA 0x398
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SIO_CONFIG_RD 0x399
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SLOW_DOWN_IO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* 32 bits uses slightly different variables for the various IO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * bases. Most of this file only uses _IO_BASE though which we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * define properly based on the platform
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #ifndef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define _IO_BASE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define _ISA_MEM_BASE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PCI_DRAM_OFFSET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #elif defined(CONFIG_PPC32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define _IO_BASE isa_io_base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define _ISA_MEM_BASE isa_mem_base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PCI_DRAM_OFFSET pci_dram_offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define _IO_BASE pci_io_base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define _ISA_MEM_BASE isa_mem_base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PCI_DRAM_OFFSET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) extern unsigned long isa_io_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) extern unsigned long pci_io_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) extern unsigned long pci_dram_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) extern resource_size_t isa_mem_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* Boolean set by platform if PIO accesses are suppored while _IO_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * is not set or addresses cannot be translated to MMIO. This is typically
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * set when the platform supports "special" PIO accesses via a non memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * mapped mechanism, and allows things like the early udbg UART code to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) extern bool isa_io_special;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #ifdef CONFIG_PPC32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #error CONFIG_PPC_INDIRECT_{PIO,MMIO} are not yet supported on 32 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * Low level MMIO accessors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * This provides the non-bus specific accessors to MMIO. Those are PowerPC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * specific and thus shouldn't be used in generic code. The accessors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * provided here are:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * in_8, in_le16, in_be16, in_le32, in_be32, in_le64, in_be64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * out_8, out_le16, out_be16, out_le32, out_be32, out_le64, out_be64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * _insb, _insw_ns, _insl_ns, _outsb, _outsw_ns, _outsl_ns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * Those operate directly on a kernel virtual address. Note that the prototype
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * for the out_* accessors has the arguments in opposite order from the usual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * linux PCI accessors. Unlike those, they take the address first and the value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * next.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * Note: I might drop the _ns suffix on the stream operations soon as it is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * simply normal for stream operations to not swap in the first place.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define DEF_MMIO_IN_X(name, size, insn) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static inline u##size name(const volatile u##size __iomem *addr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u##size ret; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) __asm__ __volatile__("sync;"#insn" %0,%y1;twi 0,%0,0;isync" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) : "=r" (ret) : "Z" (*addr) : "memory"); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return ret; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define DEF_MMIO_OUT_X(name, size, insn) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static inline void name(volatile u##size __iomem *addr, u##size val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) __asm__ __volatile__("sync;"#insn" %1,%y0" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) : "=Z" (*addr) : "r" (val) : "memory"); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) mmiowb_set_pending(); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define DEF_MMIO_IN_D(name, size, insn) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static inline u##size name(const volatile u##size __iomem *addr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u##size ret; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) __asm__ __volatile__("sync;"#insn"%U1%X1 %0,%1;twi 0,%0,0;isync"\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) : "=r" (ret) : "m" (*addr) : "memory"); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return ret; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define DEF_MMIO_OUT_D(name, size, insn) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static inline void name(volatile u##size __iomem *addr, u##size val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) __asm__ __volatile__("sync;"#insn"%U0%X0 %1,%0" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) : "=m" (*addr) : "r" (val) : "memory"); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) mmiowb_set_pending(); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) DEF_MMIO_IN_D(in_8, 8, lbz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) DEF_MMIO_OUT_D(out_8, 8, stb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #ifdef __BIG_ENDIAN__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) DEF_MMIO_IN_D(in_be16, 16, lhz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) DEF_MMIO_IN_D(in_be32, 32, lwz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) DEF_MMIO_IN_X(in_le16, 16, lhbrx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) DEF_MMIO_IN_X(in_le32, 32, lwbrx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) DEF_MMIO_OUT_D(out_be16, 16, sth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) DEF_MMIO_OUT_D(out_be32, 32, stw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) DEF_MMIO_OUT_X(out_le16, 16, sthbrx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) DEF_MMIO_OUT_X(out_le32, 32, stwbrx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) DEF_MMIO_IN_X(in_be16, 16, lhbrx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) DEF_MMIO_IN_X(in_be32, 32, lwbrx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) DEF_MMIO_IN_D(in_le16, 16, lhz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) DEF_MMIO_IN_D(in_le32, 32, lwz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) DEF_MMIO_OUT_X(out_be16, 16, sthbrx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) DEF_MMIO_OUT_X(out_be32, 32, stwbrx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) DEF_MMIO_OUT_D(out_le16, 16, sth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) DEF_MMIO_OUT_D(out_le32, 32, stw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #endif /* __BIG_ENDIAN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #ifdef __powerpc64__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #ifdef __BIG_ENDIAN__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) DEF_MMIO_OUT_D(out_be64, 64, std);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) DEF_MMIO_IN_D(in_be64, 64, ld);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* There is no asm instructions for 64 bits reverse loads and stores */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static inline u64 in_le64(const volatile u64 __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return swab64(in_be64(addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static inline void out_le64(volatile u64 __iomem *addr, u64 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) out_be64(addr, swab64(val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) DEF_MMIO_OUT_D(out_le64, 64, std);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) DEF_MMIO_IN_D(in_le64, 64, ld);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* There is no asm instructions for 64 bits reverse loads and stores */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static inline u64 in_be64(const volatile u64 __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return swab64(in_le64(addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static inline void out_be64(volatile u64 __iomem *addr, u64 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) out_le64(addr, swab64(val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #endif /* __powerpc64__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * Low level IO stream instructions are defined out of line for now
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) extern void _insb(const volatile u8 __iomem *addr, void *buf, long count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) extern void _outsb(volatile u8 __iomem *addr,const void *buf,long count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) extern void _insw_ns(const volatile u16 __iomem *addr, void *buf, long count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) extern void _outsw_ns(volatile u16 __iomem *addr, const void *buf, long count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) extern void _insl_ns(const volatile u32 __iomem *addr, void *buf, long count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) extern void _outsl_ns(volatile u32 __iomem *addr, const void *buf, long count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* The _ns naming is historical and will be removed. For now, just #define
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * the non _ns equivalent names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define _insw _insw_ns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define _insl _insl_ns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define _outsw _outsw_ns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define _outsl _outsl_ns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * memset_io, memcpy_toio, memcpy_fromio base implementations are out of line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) extern void _memset_io(volatile void __iomem *addr, int c, unsigned long n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) extern void _memcpy_fromio(void *dest, const volatile void __iomem *src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) unsigned long n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) extern void _memcpy_toio(volatile void __iomem *dest, const void *src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) unsigned long n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * PCI and standard ISA accessors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * Those are globally defined linux accessors for devices on PCI or ISA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * busses. They follow the Linux defined semantics. The current implementation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * for PowerPC is as close as possible to the x86 version of these, and thus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * provides fairly heavy weight barriers for the non-raw versions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * In addition, they support a hook mechanism when CONFIG_PPC_INDIRECT_MMIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * or CONFIG_PPC_INDIRECT_PIO are set allowing the platform to provide its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * own implementation of some or all of the accessors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * Include the EEH definitions when EEH is enabled only so they don't get
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * in the way when building for 32 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #ifdef CONFIG_EEH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #include <asm/eeh.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* Shortcut to the MMIO argument pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define PCI_IO_ADDR volatile void __iomem *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* Indirect IO address tokens:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * When CONFIG_PPC_INDIRECT_MMIO is set, the platform can provide hooks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * on all MMIOs. (Note that this is all 64 bits only for now)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * To help platforms who may need to differentiate MMIO addresses in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * their hooks, a bitfield is reserved for use by the platform near the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * top of MMIO addresses (not PIO, those have to cope the hard way).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * The highest address in the kernel virtual space are:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * d0003fffffffffff # with Hash MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * c00fffffffffffff # with Radix MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * The top 4 bits are reserved as the region ID on hash, leaving us 8 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * that can be used for the field.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * The direct IO mapping operations will then mask off those bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * before doing the actual access, though that only happen when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * CONFIG_PPC_INDIRECT_MMIO is set, thus be careful when you use that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * mechanism
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * For PIO, there is a separate CONFIG_PPC_INDIRECT_PIO which makes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * all PIO functions call through a hook.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #ifdef CONFIG_PPC_INDIRECT_MMIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define PCI_IO_IND_TOKEN_SHIFT 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define PCI_IO_IND_TOKEN_MASK (0xfful << PCI_IO_IND_TOKEN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define PCI_FIX_ADDR(addr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) ((PCI_IO_ADDR)(((unsigned long)(addr)) & ~PCI_IO_IND_TOKEN_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define PCI_GET_ADDR_TOKEN(addr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) (((unsigned long)(addr) & PCI_IO_IND_TOKEN_MASK) >> \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) PCI_IO_IND_TOKEN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define PCI_SET_ADDR_TOKEN(addr, token) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) unsigned long __a = (unsigned long)(addr); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) __a &= ~PCI_IO_IND_TOKEN_MASK; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) __a |= ((unsigned long)(token)) << PCI_IO_IND_TOKEN_SHIFT; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) (addr) = (void __iomem *)__a; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define PCI_FIX_ADDR(addr) (addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * Non ordered and non-swapping "raw" accessors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static inline unsigned char __raw_readb(const volatile void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return *(volatile unsigned char __force *)PCI_FIX_ADDR(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static inline unsigned short __raw_readw(const volatile void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) return *(volatile unsigned short __force *)PCI_FIX_ADDR(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static inline unsigned int __raw_readl(const volatile void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return *(volatile unsigned int __force *)PCI_FIX_ADDR(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static inline void __raw_writeb(unsigned char v, volatile void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) *(volatile unsigned char __force *)PCI_FIX_ADDR(addr) = v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static inline void __raw_writew(unsigned short v, volatile void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) *(volatile unsigned short __force *)PCI_FIX_ADDR(addr) = v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static inline void __raw_writel(unsigned int v, volatile void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) *(volatile unsigned int __force *)PCI_FIX_ADDR(addr) = v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #ifdef __powerpc64__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static inline unsigned long __raw_readq(const volatile void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return *(volatile unsigned long __force *)PCI_FIX_ADDR(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static inline void __raw_writeq(unsigned long v, volatile void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) *(volatile unsigned long __force *)PCI_FIX_ADDR(addr) = v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static inline void __raw_writeq_be(unsigned long v, volatile void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) __raw_writeq((__force unsigned long)cpu_to_be64(v), addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * Real mode versions of the above. Those instructions are only supposed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) * to be used in hypervisor real mode as per the architecture spec.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static inline void __raw_rm_writeb(u8 val, volatile void __iomem *paddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) __asm__ __volatile__(".machine push; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .machine power6; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) stbcix %0,0,%1; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .machine pop;"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) : : "r" (val), "r" (paddr) : "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static inline void __raw_rm_writew(u16 val, volatile void __iomem *paddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) __asm__ __volatile__(".machine push; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .machine power6; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) sthcix %0,0,%1; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .machine pop;"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) : : "r" (val), "r" (paddr) : "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static inline void __raw_rm_writel(u32 val, volatile void __iomem *paddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) __asm__ __volatile__(".machine push; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .machine power6; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) stwcix %0,0,%1; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .machine pop;"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) : : "r" (val), "r" (paddr) : "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static inline void __raw_rm_writeq(u64 val, volatile void __iomem *paddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) __asm__ __volatile__(".machine push; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .machine power6; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) stdcix %0,0,%1; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .machine pop;"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) : : "r" (val), "r" (paddr) : "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static inline void __raw_rm_writeq_be(u64 val, volatile void __iomem *paddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) __raw_rm_writeq((__force u64)cpu_to_be64(val), paddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static inline u8 __raw_rm_readb(volatile void __iomem *paddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) u8 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) __asm__ __volatile__(".machine push; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .machine power6; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) lbzcix %0,0, %1; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .machine pop;"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) : "=r" (ret) : "r" (paddr) : "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static inline u16 __raw_rm_readw(volatile void __iomem *paddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) u16 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) __asm__ __volatile__(".machine push; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .machine power6; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) lhzcix %0,0, %1; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .machine pop;"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) : "=r" (ret) : "r" (paddr) : "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static inline u32 __raw_rm_readl(volatile void __iomem *paddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) u32 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) __asm__ __volatile__(".machine push; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .machine power6; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) lwzcix %0,0, %1; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .machine pop;"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) : "=r" (ret) : "r" (paddr) : "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static inline u64 __raw_rm_readq(volatile void __iomem *paddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) u64 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) __asm__ __volatile__(".machine push; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .machine power6; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) ldcix %0,0, %1; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .machine pop;"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) : "=r" (ret) : "r" (paddr) : "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #endif /* __powerpc64__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * PCI PIO and MMIO accessors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) * On 32 bits, PIO operations have a recovery mechanism in case they trigger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) * machine checks (which they occasionally do when probing non existing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) * IO ports on some platforms, like PowerMac and 8xx).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) * I always found it to be of dubious reliability and I am tempted to get
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * rid of it one of these days. So if you think it's important to keep it,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * please voice up asap. We never had it for 64 bits and I do not intend
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) * to port it over
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #ifdef CONFIG_PPC32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define __do_in_asm(name, op) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static inline unsigned int name(unsigned int port) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) unsigned int x; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) __asm__ __volatile__( \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) "sync\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) "0:" op " %0,0,%1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) "1: twi 0,%0,0\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) "2: isync\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) "3: nop\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) "4:\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) ".section .fixup,\"ax\"\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) "5: li %0,-1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) " b 4b\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) ".previous\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) EX_TABLE(0b, 5b) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) EX_TABLE(1b, 5b) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) EX_TABLE(2b, 5b) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) EX_TABLE(3b, 5b) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) : "=&r" (x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) : "r" (port + _IO_BASE) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) : "memory"); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) return x; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define __do_out_asm(name, op) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) static inline void name(unsigned int val, unsigned int port) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) __asm__ __volatile__( \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) "sync\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) "0:" op " %0,0,%1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) "1: sync\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) "2:\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) EX_TABLE(0b, 2b) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) EX_TABLE(1b, 2b) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) : : "r" (val), "r" (port + _IO_BASE) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) : "memory"); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) __do_in_asm(_rec_inb, "lbzx")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) __do_in_asm(_rec_inw, "lhbrx")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) __do_in_asm(_rec_inl, "lwbrx")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) __do_out_asm(_rec_outb, "stbx")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) __do_out_asm(_rec_outw, "sthbrx")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) __do_out_asm(_rec_outl, "stwbrx")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #endif /* CONFIG_PPC32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /* The "__do_*" operations below provide the actual "base" implementation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) * for each of the defined accessors. Some of them use the out_* functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) * directly, some of them still use EEH, though we might change that in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) * future. Those macros below provide the necessary argument swapping and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) * handling of the IO base for PIO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) * They are themselves used by the macros that define the actual accessors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) * and can be used by the hooks if any.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) * Note that PIO operations are always defined in terms of their corresonding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * MMIO operations. That allows platforms like iSeries who want to modify the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) * behaviour of both to only hook on the MMIO version and get both. It's also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) * possible to hook directly at the toplevel PIO operation if they have to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) * be handled differently
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define __do_writeb(val, addr) out_8(PCI_FIX_ADDR(addr), val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define __do_writew(val, addr) out_le16(PCI_FIX_ADDR(addr), val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define __do_writel(val, addr) out_le32(PCI_FIX_ADDR(addr), val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define __do_writeq(val, addr) out_le64(PCI_FIX_ADDR(addr), val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define __do_writew_be(val, addr) out_be16(PCI_FIX_ADDR(addr), val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define __do_writel_be(val, addr) out_be32(PCI_FIX_ADDR(addr), val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define __do_writeq_be(val, addr) out_be64(PCI_FIX_ADDR(addr), val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #ifdef CONFIG_EEH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define __do_readb(addr) eeh_readb(PCI_FIX_ADDR(addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define __do_readw(addr) eeh_readw(PCI_FIX_ADDR(addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define __do_readl(addr) eeh_readl(PCI_FIX_ADDR(addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define __do_readq(addr) eeh_readq(PCI_FIX_ADDR(addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define __do_readw_be(addr) eeh_readw_be(PCI_FIX_ADDR(addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define __do_readl_be(addr) eeh_readl_be(PCI_FIX_ADDR(addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define __do_readq_be(addr) eeh_readq_be(PCI_FIX_ADDR(addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #else /* CONFIG_EEH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define __do_readb(addr) in_8(PCI_FIX_ADDR(addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define __do_readw(addr) in_le16(PCI_FIX_ADDR(addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define __do_readl(addr) in_le32(PCI_FIX_ADDR(addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define __do_readq(addr) in_le64(PCI_FIX_ADDR(addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define __do_readw_be(addr) in_be16(PCI_FIX_ADDR(addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define __do_readl_be(addr) in_be32(PCI_FIX_ADDR(addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define __do_readq_be(addr) in_be64(PCI_FIX_ADDR(addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #endif /* !defined(CONFIG_EEH) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #ifdef CONFIG_PPC32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define __do_outb(val, port) _rec_outb(val, port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define __do_outw(val, port) _rec_outw(val, port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define __do_outl(val, port) _rec_outl(val, port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define __do_inb(port) _rec_inb(port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define __do_inw(port) _rec_inw(port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define __do_inl(port) _rec_inl(port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #else /* CONFIG_PPC32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define __do_outb(val, port) writeb(val,(PCI_IO_ADDR)_IO_BASE+port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define __do_outw(val, port) writew(val,(PCI_IO_ADDR)_IO_BASE+port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define __do_outl(val, port) writel(val,(PCI_IO_ADDR)_IO_BASE+port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define __do_inb(port) readb((PCI_IO_ADDR)_IO_BASE + port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define __do_inw(port) readw((PCI_IO_ADDR)_IO_BASE + port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define __do_inl(port) readl((PCI_IO_ADDR)_IO_BASE + port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #endif /* !CONFIG_PPC32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #ifdef CONFIG_EEH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define __do_readsb(a, b, n) eeh_readsb(PCI_FIX_ADDR(a), (b), (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define __do_readsw(a, b, n) eeh_readsw(PCI_FIX_ADDR(a), (b), (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define __do_readsl(a, b, n) eeh_readsl(PCI_FIX_ADDR(a), (b), (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #else /* CONFIG_EEH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define __do_readsb(a, b, n) _insb(PCI_FIX_ADDR(a), (b), (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define __do_readsw(a, b, n) _insw(PCI_FIX_ADDR(a), (b), (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define __do_readsl(a, b, n) _insl(PCI_FIX_ADDR(a), (b), (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #endif /* !CONFIG_EEH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define __do_writesb(a, b, n) _outsb(PCI_FIX_ADDR(a),(b),(n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define __do_writesw(a, b, n) _outsw(PCI_FIX_ADDR(a),(b),(n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define __do_writesl(a, b, n) _outsl(PCI_FIX_ADDR(a),(b),(n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define __do_insb(p, b, n) readsb((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define __do_insw(p, b, n) readsw((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define __do_insl(p, b, n) readsl((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define __do_outsb(p, b, n) writesb((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define __do_outsw(p, b, n) writesw((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define __do_outsl(p, b, n) writesl((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #define __do_memset_io(addr, c, n) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) _memset_io(PCI_FIX_ADDR(addr), c, n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define __do_memcpy_toio(dst, src, n) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) _memcpy_toio(PCI_FIX_ADDR(dst), src, n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #ifdef CONFIG_EEH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define __do_memcpy_fromio(dst, src, n) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) eeh_memcpy_fromio(dst, PCI_FIX_ADDR(src), n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #else /* CONFIG_EEH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define __do_memcpy_fromio(dst, src, n) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) _memcpy_fromio(dst,PCI_FIX_ADDR(src),n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #endif /* !CONFIG_EEH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #ifdef CONFIG_PPC_INDIRECT_PIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define DEF_PCI_HOOK_pio(x) x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define DEF_PCI_HOOK_pio(x) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #ifdef CONFIG_PPC_INDIRECT_MMIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #define DEF_PCI_HOOK_mem(x) x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define DEF_PCI_HOOK_mem(x) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) /* Structure containing all the hooks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) extern struct ppc_pci_io {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #define DEF_PCI_AC_RET(name, ret, at, al, space, aa) ret (*name) at;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #define DEF_PCI_AC_NORET(name, at, al, space, aa) void (*name) at;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #include <asm/io-defs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #undef DEF_PCI_AC_RET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #undef DEF_PCI_AC_NORET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) } ppc_pci_io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) /* The inline wrappers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #define DEF_PCI_AC_RET(name, ret, at, al, space, aa) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) static inline ret name at \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) return ppc_pci_io.name al; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) return __do_##name al; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #define DEF_PCI_AC_NORET(name, at, al, space, aa) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) static inline void name at \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) ppc_pci_io.name al; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) else \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) __do_##name al; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) #include <asm/io-defs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) #undef DEF_PCI_AC_RET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #undef DEF_PCI_AC_NORET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) /* Some drivers check for the presence of readq & writeq with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) * a #ifdef, so we make them happy here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) #ifdef __powerpc64__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) #define readq readq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) #define writeq writeq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) * Convert a physical pointer to a virtual kernel pointer for /dev/mem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) * access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) #define xlate_dev_mem_ptr(p) __va(p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) * Convert a virtual cached pointer to an uncached pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) #define xlate_dev_kmem_ptr(p) p
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) * We don't do relaxed operations yet, at least not with this semantic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) #define readb_relaxed(addr) readb(addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) #define readw_relaxed(addr) readw(addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) #define readl_relaxed(addr) readl(addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) #define readq_relaxed(addr) readq(addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) #define writeb_relaxed(v, addr) writeb(v, addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) #define writew_relaxed(v, addr) writew(v, addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) #define writel_relaxed(v, addr) writel(v, addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) #define writeq_relaxed(v, addr) writeq(v, addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) #include <asm-generic/iomap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) static inline void iosync(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) __asm__ __volatile__ ("sync" : : : "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) /* Enforce in-order execution of data I/O.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) * No distinction between read/write on PPC; use eieio for all three.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) * Those are fairly week though. They don't provide a barrier between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) * MMIO and cacheable storage nor do they provide a barrier vs. locks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) * they only provide barriers between 2 __raw MMIO operations and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) * possibly break write combining.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) #define iobarrier_rw() eieio()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) #define iobarrier_r() eieio()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) #define iobarrier_w() eieio()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) * output pause versions need a delay at least for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) * w83c105 ide controller in a p610.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) #define inb_p(port) inb(port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) #define outb_p(val, port) (udelay(1), outb((val), (port)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) #define inw_p(port) inw(port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) #define outw_p(val, port) (udelay(1), outw((val), (port)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) #define inl_p(port) inl(port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) #define outl_p(val, port) (udelay(1), outl((val), (port)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) #define IO_SPACE_LIMIT ~(0UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) * ioremap - map bus memory into CPU space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) * @address: bus address of the memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) * @size: size of the resource to map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) * ioremap performs a platform specific sequence of operations to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) * make bus memory CPU accessible via the readb/readw/readl/writeb/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) * writew/writel functions and the other mmio helpers. The returned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) * address is not guaranteed to be usable directly as a virtual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) * address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) * We provide a few variations of it:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) * * ioremap is the standard one and provides non-cacheable guarded mappings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) * and can be hooked by the platform via ppc_md
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) * * ioremap_prot allows to specify the page flags as an argument and can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) * also be hooked by the platform via ppc_md.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) * * ioremap_wc enables write combining
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) * * ioremap_wt enables write through
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) * * ioremap_coherent maps coherent cached memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) * * iounmap undoes such a mapping and can be hooked
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) * * __ioremap_caller is the same as above but takes an explicit caller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) * reference rather than using __builtin_return_address(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) extern void __iomem *ioremap(phys_addr_t address, unsigned long size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) extern void __iomem *ioremap_prot(phys_addr_t address, unsigned long size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) unsigned long flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) extern void __iomem *ioremap_wc(phys_addr_t address, unsigned long size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) void __iomem *ioremap_wt(phys_addr_t address, unsigned long size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) void __iomem *ioremap_coherent(phys_addr_t address, unsigned long size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) #define ioremap_uc(addr, size) ioremap((addr), (size))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) #define ioremap_cache(addr, size) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) ioremap_prot((addr), (size), pgprot_val(PAGE_KERNEL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) extern void iounmap(volatile void __iomem *addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) void __iomem *ioremap_phb(phys_addr_t paddr, unsigned long size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) int early_ioremap_range(unsigned long ea, phys_addr_t pa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) unsigned long size, pgprot_t prot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) void __iomem *do_ioremap(phys_addr_t pa, phys_addr_t offset, unsigned long size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) pgprot_t prot, void *caller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) extern void __iomem *__ioremap_caller(phys_addr_t, unsigned long size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) pgprot_t prot, void *caller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) * When CONFIG_PPC_INDIRECT_PIO is set, we use the generic iomap implementation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) * which needs some additional definitions here. They basically allow PIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) * space overall to be 1GB. This will work as long as we never try to use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) * iomap to map MMIO below 1GB which should be fine on ppc64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) #define HAVE_ARCH_PIO_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) #define PIO_OFFSET 0x00000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) #define PIO_MASK (FULL_IO_SIZE - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) #define PIO_RESERVED (FULL_IO_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) #define mmio_read16be(addr) readw_be(addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) #define mmio_read32be(addr) readl_be(addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) #define mmio_read64be(addr) readq_be(addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) #define mmio_write16be(val, addr) writew_be(val, addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) #define mmio_write32be(val, addr) writel_be(val, addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) #define mmio_write64be(val, addr) writeq_be(val, addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) #define mmio_insb(addr, dst, count) readsb(addr, dst, count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) #define mmio_insw(addr, dst, count) readsw(addr, dst, count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) #define mmio_insl(addr, dst, count) readsl(addr, dst, count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) #define mmio_outsb(addr, src, count) writesb(addr, src, count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) #define mmio_outsw(addr, src, count) writesw(addr, src, count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) #define mmio_outsl(addr, src, count) writesl(addr, src, count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) * virt_to_phys - map virtual addresses to physical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) * @address: address to remap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) * The returned physical address is the physical (CPU) mapping for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) * the memory address given. It is only valid to use this function on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) * addresses directly mapped or allocated via kmalloc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) * This function does not give bus mappings for DMA transfers. In
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) * almost all conceivable cases a device driver should not be using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) * this function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) static inline unsigned long virt_to_phys(volatile void * address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) WARN_ON(IS_ENABLED(CONFIG_DEBUG_VIRTUAL) && !virt_addr_valid(address));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) return __pa((unsigned long)address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) * phys_to_virt - map physical address to virtual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) * @address: address to remap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) * The returned virtual address is a current CPU mapping for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) * the memory address given. It is only valid to use this function on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) * addresses that have a kernel mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) * This function does not handle bus mappings for DMA transfers. In
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) * almost all conceivable cases a device driver should not be using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) * this function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) static inline void * phys_to_virt(unsigned long address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) return (void *)__va(address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) * Change "struct page" to physical address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) static inline phys_addr_t page_to_phys(struct page *page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) unsigned long pfn = page_to_pfn(page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) WARN_ON(IS_ENABLED(CONFIG_DEBUG_VIRTUAL) && !pfn_valid(pfn));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) return PFN_PHYS(pfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) * 32 bits still uses virt_to_bus() for it's implementation of DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) * mappings se we have to keep it defined here. We also have some old
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) * drivers (shame shame shame) that use bus_to_virt() and haven't been
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) * fixed yet so I need to define it here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) #ifdef CONFIG_PPC32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) static inline unsigned long virt_to_bus(volatile void * address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) if (address == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) return __pa(address) + PCI_DRAM_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) static inline void * bus_to_virt(unsigned long address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) if (address == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) return __va(address - PCI_DRAM_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) #define page_to_bus(page) (page_to_phys(page) + PCI_DRAM_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) #endif /* CONFIG_PPC32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) /* access ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) #define setbits32(_addr, _v) out_be32((_addr), in_be32(_addr) | (_v))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) #define clrbits32(_addr, _v) out_be32((_addr), in_be32(_addr) & ~(_v))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) #define setbits16(_addr, _v) out_be16((_addr), in_be16(_addr) | (_v))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) #define clrbits16(_addr, _v) out_be16((_addr), in_be16(_addr) & ~(_v))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) #define setbits8(_addr, _v) out_8((_addr), in_8(_addr) | (_v))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) #define clrbits8(_addr, _v) out_8((_addr), in_8(_addr) & ~(_v))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) /* Clear and set bits in one shot. These macros can be used to clear and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) * set multiple bits in a register using a single read-modify-write. These
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) * macros can also be used to set a multiple-bit bit pattern using a mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) * by specifying the mask in the 'clear' parameter and the new bit pattern
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) * in the 'set' parameter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) #define clrsetbits(type, addr, clear, set) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) #ifdef __powerpc64__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) #define clrsetbits_be64(addr, clear, set) clrsetbits(be64, addr, clear, set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) #define clrsetbits_le64(addr, clear, set) clrsetbits(le64, addr, clear, set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) #define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) #define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) #define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) #define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) #endif /* __KERNEL__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) #endif /* _ASM_POWERPC_IO_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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