^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ICSWX api
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2015 IBM Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This provides the Initiate Coprocessor Store Word Indexed (ICSWX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * instruction. This instruction is used to communicate with PowerPC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * coprocessors. This also provides definitions of the structures used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * to communicate with the coprocessor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * The RFC02130: Coprocessor Architecture document is the reference for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * everything in this file unless otherwise noted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #ifndef _ARCH_POWERPC_INCLUDE_ASM_ICSWX_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define _ARCH_POWERPC_INCLUDE_ASM_ICSWX_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/ppc-opcode.h> /* for PPC_ICSWX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* Chapter 6.5.8 Coprocessor-Completion Block (CCB) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CCB_VALUE (0x3fffffffffffffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CCB_ADDRESS (0xfffffffffffffff8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CCB_CM (0x0000000000000007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CCB_CM0 (0x0000000000000004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CCB_CM12 (0x0000000000000003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CCB_CM0_ALL_COMPLETIONS (0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CCB_CM0_LAST_IN_CHAIN (0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CCB_CM12_STORE (0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CCB_CM12_INTERRUPT (0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CCB_SIZE (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CCB_ALIGN CCB_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct coprocessor_completion_block {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) __be64 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) __be64 address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) } __packed __aligned(CCB_ALIGN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* Chapter 6.5.7 Coprocessor-Status Block (CSB) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CSB_V (0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CSB_F (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CSB_CH (0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CSB_CE_INCOMPLETE (0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CSB_CE_TERMINATION (0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CSB_CE_TPBC (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CSB_CC_SUCCESS (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CSB_CC_INVALID_ALIGN (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CSB_CC_OPERAND_OVERLAP (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CSB_CC_DATA_LENGTH (3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CSB_CC_TRANSLATION (5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CSB_CC_PROTECTION (6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CSB_CC_RD_EXTERNAL (7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CSB_CC_INVALID_OPERAND (8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CSB_CC_PRIVILEGE (9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CSB_CC_INTERNAL (10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CSB_CC_WR_EXTERNAL (12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CSB_CC_NOSPC (13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CSB_CC_EXCESSIVE_DDE (14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CSB_CC_WR_TRANSLATION (15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CSB_CC_WR_PROTECTION (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CSB_CC_UNKNOWN_CODE (17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CSB_CC_ABORT (18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CSB_CC_EXCEED_BYTE_COUNT (19) /* P9 or later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define CSB_CC_TRANSPORT (20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CSB_CC_INVALID_CRB (21) /* P9 or later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define CSB_CC_INVALID_DDE (30) /* P9 or later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define CSB_CC_SEGMENTED_DDL (31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define CSB_CC_PROGRESS_POINT (32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define CSB_CC_DDE_OVERFLOW (33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define CSB_CC_SESSION (34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define CSB_CC_PROVISION (36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define CSB_CC_CHAIN (37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define CSB_CC_SEQUENCE (38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define CSB_CC_HW (39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* P9 DD2 NX Workbook 3.2 (Table 4-36): Address translation fault */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define CSB_CC_FAULT_ADDRESS (250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define CSB_SIZE (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define CSB_ALIGN CSB_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct coprocessor_status_block {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u8 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u8 cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u8 cc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u8 ce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) __be32 count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) __be64 address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) } __packed __aligned(CSB_ALIGN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* Chapter 6.5.10 Data-Descriptor List (DDL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * each list contains one or more Data-Descriptor Entries (DDE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define DDE_P (0x8000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define DDE_SIZE (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define DDE_ALIGN DDE_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct data_descriptor_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) __be16 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u8 count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u8 index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) __be32 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) __be64 address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) } __packed __aligned(DDE_ALIGN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* 4.3.2 NX-stamped Fault CRB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define NX_STAMP_ALIGN (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct nx_fault_stamp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) __be64 fault_storage_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) __be16 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) __u8 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) __u8 fault_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) __be32 pswid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) } __packed __aligned(NX_STAMP_ALIGN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* Chapter 6.5.2 Coprocessor-Request Block (CRB) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define CRB_SIZE (0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define CRB_ALIGN (0x100) /* Errata: requires 256 alignment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* Coprocessor Status Block field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * ADDRESS address of CSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * C CCB is valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * AT 0 = addrs are virtual, 1 = addrs are phys
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * M enable perf monitor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define CRB_CSB_ADDRESS (0xfffffffffffffff0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define CRB_CSB_C (0x0000000000000008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define CRB_CSB_AT (0x0000000000000002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define CRB_CSB_M (0x0000000000000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct coprocessor_request_block {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) __be32 ccw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) __be32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) __be64 csb_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct data_descriptor_entry source;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct data_descriptor_entry target;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct coprocessor_completion_block ccb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct nx_fault_stamp nx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) u8 reserved[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) } stamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) u8 reserved[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct coprocessor_status_block csb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) } __aligned(128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* RFC02167 Initiate Coprocessor Instructions document
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * Chapter 8.2.1.1.1 RS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * Chapter 8.2.3 Coprocessor Directive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * Chapter 8.2.4 Execution
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * The CCW must be converted to BE before passing to icswx()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define CCW_PS (0xff000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define CCW_CT (0x00ff0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define CCW_CD (0x0000ffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define CCW_CL (0x0000c000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* RFC02167 Initiate Coprocessor Instructions document
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * Chapter 8.2.1 Initiate Coprocessor Store Word Indexed (ICSWX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * Chapter 8.2.4.1 Condition Register 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define ICSWX_INITIATED (0x8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define ICSWX_BUSY (0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define ICSWX_REJECTED (0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define ICSWX_XERS0 (0x1) /* undefined or set from XERSO. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static inline int icswx(__be32 ccw, struct coprocessor_request_block *crb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) __be64 ccw_reg = ccw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) u32 cr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* NB: the same structures are used by VAS-NX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) BUILD_BUG_ON(sizeof(*crb) != 128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) __asm__ __volatile__(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) PPC_ICSWX(%1,0,%2) "\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) "mfcr %0\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) : "=r" (cr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) : "r" (ccw_reg), "r" (crb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) : "cr0", "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return (int)((cr >> 28) & 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #endif /* _ARCH_POWERPC_INCLUDE_ASM_ICSWX_H_ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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