^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * include/asm-ppc/hydra.h -- Mac I/O `Hydra' definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 1997 Geert Uytterhoeven
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This file is based on the following documentation:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Macintosh Technology in the Common Hardware Reference Platform
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Apple Computer, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * © Copyright 1995 Apple Computer, Inc. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * It's available online from https://www.cpu.lu/~mlan/ftp/MacTech.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * You can obtain paper copies of this book from computer bookstores or by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * writing Morgan Kaufmann Publishers, Inc., 340 Pine Street, Sixth Floor, San
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Francisco, CA 94104. Reference ISBN 1-55860-393-X.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * License. See the file COPYING in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #ifndef _ASMPPC_HYDRA_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define _ASMPPC_HYDRA_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #ifdef __KERNEL__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct Hydra {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* DBDMA Controller Register Space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) char Pad1[0x30];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u_int CachePD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) u_int IDs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) u_int Feature_Control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) char Pad2[0x7fc4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* DBDMA Channel Register Space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) char SCSI_DMA[0x100];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) char Pad3[0x300];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) char SCCA_Tx_DMA[0x100];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) char SCCA_Rx_DMA[0x100];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) char SCCB_Tx_DMA[0x100];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) char SCCB_Rx_DMA[0x100];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) char Pad4[0x7800];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* Device Register Space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) char SCSI[0x1000];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) char ADB[0x1000];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) char SCC_Legacy[0x1000];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) char SCC[0x1000];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) char Pad9[0x2000];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) char VIA[0x2000];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) char Pad10[0x28000];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) char OpenPIC[0x40000];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) extern volatile struct Hydra __iomem *Hydra;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * Feature Control Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define HYDRA_FC_SCC_CELL_EN 0x00000001 /* Enable SCC Clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define HYDRA_FC_SCSI_CELL_EN 0x00000002 /* Enable SCSI Clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define HYDRA_FC_SCCA_ENABLE 0x00000004 /* Enable SCC A Lines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define HYDRA_FC_SCCB_ENABLE 0x00000008 /* Enable SCC B Lines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define HYDRA_FC_ARB_BYPASS 0x00000010 /* Bypass Internal Arbiter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define HYDRA_FC_RESET_SCC 0x00000020 /* Reset SCC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define HYDRA_FC_MPIC_ENABLE 0x00000040 /* Enable OpenPIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define HYDRA_FC_SLOW_SCC_PCLK 0x00000080 /* 1=15.6672, 0=25 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define HYDRA_FC_MPIC_IS_MASTER 0x00000100 /* OpenPIC Master Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * OpenPIC Interrupt Sources
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define HYDRA_INT_SIO 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define HYDRA_INT_SCSI_DMA 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define HYDRA_INT_SCCA_TX_DMA 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define HYDRA_INT_SCCA_RX_DMA 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define HYDRA_INT_SCCB_TX_DMA 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define HYDRA_INT_SCCB_RX_DMA 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define HYDRA_INT_SCSI 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define HYDRA_INT_SCCA 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define HYDRA_INT_SCCB 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define HYDRA_INT_VIA 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define HYDRA_INT_ADB 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define HYDRA_INT_ADB_NMI 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define HYDRA_INT_EXT1 12 /* PCI IRQW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define HYDRA_INT_EXT2 13 /* PCI IRQX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define HYDRA_INT_EXT3 14 /* PCI IRQY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define HYDRA_INT_EXT4 15 /* PCI IRQZ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define HYDRA_INT_EXT5 16 /* IDE Primary/Secondary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define HYDRA_INT_EXT6 17 /* IDE Secondary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define HYDRA_INT_EXT7 18 /* Power Off Request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define HYDRA_INT_SPARE 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) extern int hydra_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #endif /* __KERNEL__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #endif /* _ASMPPC_HYDRA_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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