^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef _ASM_POWERPC_HEATHROW_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define _ASM_POWERPC_HEATHROW_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #ifdef __KERNEL__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * heathrow.h: definitions for using the "Heathrow" I/O controller chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Grabbed from Open Firmware definitions on a PowerBook G3 Series
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) 1997 Paul Mackerras.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /* Front light color on Yikes/B&W G3. 32 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define HEATHROW_FRONT_LIGHT 0x32 /* (set to 0 or 0xffffffff) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* Brightness/contrast (gossamer iMac ?). 8 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define HEATHROW_BRIGHTNESS_CNTL 0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define HEATHROW_CONTRAST_CNTL 0x33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* offset from ohare base for feature control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define HEATHROW_MBCR 0x34 /* Media bay control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define HEATHROW_FCR 0x38 /* Feature control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define HEATHROW_AUX_CNTL_REG 0x3c /* Aux control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * Bits in feature control register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * Bits postfixed with a _N are in inverse logic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define HRW_SCC_TRANS_EN_N 0x00000001 /* Also controls modem power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define HRW_BAY_POWER_N 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define HRW_BAY_PCI_ENABLE 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define HRW_BAY_IDE_ENABLE 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define HRW_BAY_FLOPPY_ENABLE 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define HRW_IDE0_ENABLE 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define HRW_IDE0_RESET_N 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define HRW_BAY_DEV_MASK 0x0000001c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define HRW_BAY_RESET_N 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define HRW_IOBUS_ENABLE 0x00000100 /* Internal IDE ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define HRW_SCC_ENABLE 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define HRW_MESH_ENABLE 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define HRW_SWIM_ENABLE 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define HRW_SOUND_POWER_N 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define HRW_SOUND_CLK_ENABLE 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define HRW_SCCA_IO 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define HRW_SCCB_IO 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define HRW_PORT_OR_DESK_VIA_N 0x00010000 /* This one is 0 on PowerBook */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define HRW_PWM_MON_ID_N 0x00020000 /* ??? (0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define HRW_HOOK_MB_CNT_N 0x00040000 /* ??? (0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define HRW_SWIM_CLONE_FLOPPY 0x00080000 /* ??? (0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define HRW_AUD_RUN22 0x00100000 /* ??? (1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define HRW_SCSI_LINK_MODE 0x00200000 /* Read ??? (1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define HRW_ARB_BYPASS 0x00400000 /* Disable internal PCI arbitrer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define HRW_IDE1_RESET_N 0x00800000 /* Media bay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define HRW_SLOW_SCC_PCLK 0x01000000 /* ??? (0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define HRW_RESET_SCC 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define HRW_MFDC_CELL_ENABLE 0x04000000 /* ??? (0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define HRW_USE_MFDC 0x08000000 /* ??? (0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define HRW_BMAC_IO_ENABLE 0x60000000 /* two bits, not documented in OF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define HRW_BMAC_RESET 0x80000000 /* not documented in OF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* We OR those features at boot on desktop G3s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define HRW_DEFAULTS (HRW_SCCA_IO | HRW_SCCB_IO | HRW_SCC_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* Looks like Heathrow has some sort of GPIOs as well... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define HRW_GPIO_MODEM_RESET 0x6d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #endif /* __KERNEL__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #endif /* _ASM_POWERPC_HEATHROW_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags