^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef _ASM_POWERPC_FUTEX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define _ASM_POWERPC_FUTEX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #ifdef __KERNEL__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/futex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <asm/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <asm/synch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) __asm__ __volatile ( \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) PPC_ATOMIC_ENTRY_BARRIER \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) "1: lwarx %0,0,%2\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) insn \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) "2: stwcx. %1,0,%2\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) "bne- 1b\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) PPC_ATOMIC_EXIT_BARRIER \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) "li %1,0\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) "3: .section .fixup,\"ax\"\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) "4: li %1,%3\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) "b 3b\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) ".previous\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) EX_TABLE(1b, 4b) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) EX_TABLE(2b, 4b) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) : "=&r" (oldval), "=&r" (ret) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) : "b" (uaddr), "i" (-EFAULT), "r" (oparg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) : "cr0", "memory")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static inline int arch_futex_atomic_op_inuser(int op, int oparg, int *oval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) u32 __user *uaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) int oldval = 0, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) if (!access_ok(uaddr, sizeof(u32)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) allow_read_write_user(uaddr, uaddr, sizeof(*uaddr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) switch (op) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) case FUTEX_OP_SET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) __futex_atomic_op("mr %1,%4\n", ret, oldval, uaddr, oparg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) case FUTEX_OP_ADD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) __futex_atomic_op("add %1,%0,%4\n", ret, oldval, uaddr, oparg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) case FUTEX_OP_OR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) __futex_atomic_op("or %1,%0,%4\n", ret, oldval, uaddr, oparg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) case FUTEX_OP_ANDN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) __futex_atomic_op("andc %1,%0,%4\n", ret, oldval, uaddr, oparg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) case FUTEX_OP_XOR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) __futex_atomic_op("xor %1,%0,%4\n", ret, oldval, uaddr, oparg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) ret = -ENOSYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) *oval = oldval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) prevent_read_write_user(uaddr, uaddr, sizeof(*uaddr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u32 oldval, u32 newval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u32 prev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) if (!access_ok(uaddr, sizeof(u32)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) allow_read_write_user(uaddr, uaddr, sizeof(*uaddr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) __asm__ __volatile__ (
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) PPC_ATOMIC_ENTRY_BARRIER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) "1: lwarx %1,0,%3 # futex_atomic_cmpxchg_inatomic\n\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) cmpw 0,%1,%4\n\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) bne- 3f\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) "2: stwcx. %5,0,%3\n\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) bne- 1b\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) PPC_ATOMIC_EXIT_BARRIER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) "3: .section .fixup,\"ax\"\n\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) 4: li %0,%6\n\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) b 3b\n\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .previous\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) EX_TABLE(1b, 4b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) EX_TABLE(2b, 4b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) : "+r" (ret), "=&r" (prev), "+m" (*uaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) : "r" (uaddr), "r" (oldval), "r" (newval), "i" (-EFAULT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) : "cc", "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) *uval = prev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) prevent_read_write_user(uaddr, uaddr, sizeof(*uaddr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #endif /* __KERNEL__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #endif /* _ASM_POWERPC_FUTEX_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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