^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Definitions for use by exception code on Book3-E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2008 Ben. Herrenschmidt (benh@kernel.crashing.org), IBM Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef _ASM_POWERPC_EXCEPTION_64E_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define _ASM_POWERPC_EXCEPTION_64E_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * SPRGs usage an other considerations...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Since TLB miss and other standard exceptions can be interrupted by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * critical exceptions which can themselves be interrupted by machine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * checks, and since the two later can themselves cause a TLB miss when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * hitting the linear mapping for the kernel stacks, we need to be a bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * creative on how we use SPRGs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * The base idea is that we have one SRPG reserved for critical and one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * for machine check interrupts. Those are used to save a GPR that can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * then be used to get the PACA, and store as much context as we need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * to save in there. That includes saving the SPRGs used by the TLB miss
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * handler for linear mapping misses and the associated SRR0/1 due to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * the above re-entrancy issue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * So here's the current usage pattern. It's done regardless of which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * SPRGs are user-readable though, thus we might have to change some of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * this later. In order to do that more easily, we use special constants
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * for naming them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * WARNING: Some of these SPRGs are user readable. We need to do something
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * about it as some point by making sure they can't be used to leak kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * critical data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PACA_EXGDBELL PACA_EXGEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* We are out of SPRGs so we save some things in the PACA. The normal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * exception frame is smaller than the CRIT or MC one though
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define EX_R1 (0 * 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define EX_CR (1 * 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define EX_R10 (2 * 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define EX_R11 (3 * 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define EX_R14 (4 * 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define EX_R15 (5 * 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * The TLB miss exception uses different slots.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * The bolted variant uses only the first six fields,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * which in combination with pgd and kernel_pgd fits in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * one 64-byte cache line.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define EX_TLB_R10 ( 0 * 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define EX_TLB_R11 ( 1 * 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define EX_TLB_R14 ( 2 * 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define EX_TLB_R15 ( 3 * 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define EX_TLB_R16 ( 4 * 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define EX_TLB_CR ( 5 * 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define EX_TLB_R12 ( 6 * 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define EX_TLB_R13 ( 7 * 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define EX_TLB_DEAR ( 8 * 8) /* Level 0 and 2 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define EX_TLB_ESR ( 9 * 8) /* Level 0 and 2 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define EX_TLB_SRR0 (10 * 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define EX_TLB_SRR1 (11 * 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define EX_TLB_R7 (12 * 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define EX_TLB_SIZE (13 * 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define START_EXCEPTION(label) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .globl exc_##label##_book3e; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) exc_##label##_book3e:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* TLB miss exception prolog
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * This prolog handles re-entrancy (up to 3 levels supported in the PACA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * though we currently don't test for overflow). It provides you with a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * re-entrancy safe working space of r10...r16 and CR with r12 being used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * as the exception area pointer in the PACA for that level of re-entrancy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * and r13 containing the PACA pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * SRR0 and SRR1 are saved, but DEAR and ESR are not, since they don't apply
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * as-is for instruction exceptions. It's up to the actual exception code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * to save them as well if required.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define TLB_MISS_PROLOG \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) mtspr SPRN_SPRG_TLB_SCRATCH,r12; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) mfspr r12,SPRN_SPRG_TLB_EXFRAME; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) std r10,EX_TLB_R10(r12); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) mfcr r10; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) std r11,EX_TLB_R11(r12); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) mfspr r11,SPRN_SPRG_TLB_SCRATCH; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) std r13,EX_TLB_R13(r12); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) mfspr r13,SPRN_SPRG_PACA; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) std r14,EX_TLB_R14(r12); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) addi r14,r12,EX_TLB_SIZE; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) std r15,EX_TLB_R15(r12); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) mfspr r15,SPRN_SRR1; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) std r16,EX_TLB_R16(r12); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) mfspr r16,SPRN_SRR0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) std r10,EX_TLB_CR(r12); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) std r11,EX_TLB_R12(r12); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) mtspr SPRN_SPRG_TLB_EXFRAME,r14; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) std r15,EX_TLB_SRR1(r12); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) std r16,EX_TLB_SRR0(r12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* And these are the matching epilogs that restores things
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * There are 3 epilogs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * - SUCCESS : Unwinds one level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * - ERROR : restore from level 0 and reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * - ERROR_SPECIAL : restore from current level and reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * Normal errors use ERROR, that is, they restore the initial fault context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * and trigger a fault. However, there is a special case for linear mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * errors. Those should basically never happen, but if they do happen, we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * want the error to point out the context that did that linear mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * fault, not the initial level 0 (basically, we got a bogus PGF or something
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * like that). For userland errors on the linear mapping, there is no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * difference since those are always level 0 anyway
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define TLB_MISS_RESTORE(freg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) ld r14,EX_TLB_CR(r12); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) ld r10,EX_TLB_R10(r12); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) ld r15,EX_TLB_SRR0(r12); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) ld r16,EX_TLB_SRR1(r12); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) mtspr SPRN_SPRG_TLB_EXFRAME,freg; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) ld r11,EX_TLB_R11(r12); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) mtcr r14; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) ld r13,EX_TLB_R13(r12); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) ld r14,EX_TLB_R14(r12); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) mtspr SPRN_SRR0,r15; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) ld r15,EX_TLB_R15(r12); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) mtspr SPRN_SRR1,r16; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) ld r16,EX_TLB_R16(r12); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) ld r12,EX_TLB_R12(r12); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define TLB_MISS_EPILOG_SUCCESS \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) TLB_MISS_RESTORE(r12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define TLB_MISS_EPILOG_ERROR \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) addi r12,r13,PACA_EXTLB; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) TLB_MISS_RESTORE(r12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define TLB_MISS_EPILOG_ERROR_SPECIAL \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) addi r11,r13,PACA_EXTLB; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) TLB_MISS_RESTORE(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define SET_IVOR(vector_number, vector_offset) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) LOAD_REG_ADDR(r3,interrupt_base_book3e);\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) ori r3,r3,vector_offset@l; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) mtspr SPRN_IVOR##vector_number,r3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * powerpc relies on return from interrupt/syscall being context synchronising
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * (which rfi is) to support ARCH_HAS_MEMBARRIER_SYNC_CORE without additional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * synchronisation instructions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define RFI_TO_KERNEL \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) rfi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define RFI_TO_USER \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) rfi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #endif /* _ASM_POWERPC_EXCEPTION_64E_H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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