^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2001 Dave Engebretsen & Todd Inglett IBM Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2001-2012 IBM Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef _POWERPC_EEH_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define _POWERPC_EEH_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifdef __KERNEL__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/atomic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <uapi/asm/eeh.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) struct pci_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) struct pci_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct pci_dn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #ifdef CONFIG_EEH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* EEH subsystem flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define EEH_ENABLED 0x01 /* EEH enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define EEH_FORCE_DISABLED 0x02 /* EEH disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define EEH_PROBE_MODE_DEV 0x04 /* From PCI device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define EEH_PROBE_MODE_DEVTREE 0x08 /* From device tree */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define EEH_ENABLE_IO_FOR_LOG 0x20 /* Enable IO for log */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define EEH_EARLY_DUMP_LOG 0x40 /* Dump log immediately */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * Delay for PE reset, all in ms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * PCI specification has reset hold time of 100 milliseconds.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * We have 250 milliseconds here. The PCI bus settlement time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * is specified as 1.5 seconds and we have 1.8 seconds.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define EEH_PE_RST_HOLD_TIME 250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define EEH_PE_RST_SETTLE_TIME 1800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * The struct is used to trace PE related EEH functionality.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * In theory, there will have one instance of the struct to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * be created against particular PE. In nature, PEs correlate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * to each other. the struct has to reflect that hierarchy in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * order to easily pick up those affected PEs when one particular
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * PE has EEH errors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * Also, one particular PE might be composed of PCI device, PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * bus and its subordinate components. The struct also need ship
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * the information. Further more, one particular PE is only meaingful
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * in the corresponding PHB. Therefore, the root PEs should be created
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * against existing PHBs in on-to-one fashion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define EEH_PE_INVALID (1 << 0) /* Invalid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define EEH_PE_PHB (1 << 1) /* PHB PE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define EEH_PE_DEVICE (1 << 2) /* Device PE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define EEH_PE_BUS (1 << 3) /* Bus PE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define EEH_PE_VF (1 << 4) /* VF PE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define EEH_PE_ISOLATED (1 << 0) /* Isolated PE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define EEH_PE_RECOVERING (1 << 1) /* Recovering PE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define EEH_PE_CFG_BLOCKED (1 << 2) /* Block config access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define EEH_PE_RESET (1 << 3) /* PE reset in progress */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define EEH_PE_KEEP (1 << 8) /* Keep PE on hotplug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define EEH_PE_CFG_RESTRICTED (1 << 9) /* Block config on error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define EEH_PE_REMOVED (1 << 10) /* Removed permanently */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define EEH_PE_PRI_BUS (1 << 11) /* Cached primary bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct eeh_pe {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) int type; /* PE type: PHB/Bus/Device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) int state; /* PE EEH dependent mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) int addr; /* PE configuration address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct pci_controller *phb; /* Associated PHB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct pci_bus *bus; /* Top PCI bus for bus PE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) int check_count; /* Times of ignored error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) int freeze_count; /* Times of froze up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) time64_t tstamp; /* Time on first-time freeze */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) int false_positives; /* Times of reported #ff's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) atomic_t pass_dev_cnt; /* Count of passed through devs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct eeh_pe *parent; /* Parent PE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) void *data; /* PE auxillary data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct list_head child_list; /* List of PEs below this PE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct list_head child; /* Memb. child_list/eeh_phb_pe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct list_head edevs; /* List of eeh_dev in this PE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #ifdef CONFIG_STACKTRACE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * Saved stack trace. When we find a PE freeze in eeh_dev_check_failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * the stack trace is saved here so we can print it in the recovery
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * thread if it turns out to due to a real problem rather than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * a hot-remove.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * A max of 64 entries might be overkill, but it also might not be.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) unsigned long stack_trace[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) int trace_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #endif /* CONFIG_STACKTRACE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define eeh_pe_for_each_dev(pe, edev, tmp) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) list_for_each_entry_safe(edev, tmp, &pe->edevs, entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define eeh_for_each_pe(root, pe) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) for (pe = root; pe; pe = eeh_pe_next(pe, root))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static inline bool eeh_pe_passed(struct eeh_pe *pe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return pe ? !!atomic_read(&pe->pass_dev_cnt) : false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * The struct is used to trace EEH state for the associated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * PCI device node or PCI device. In future, it might
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * represent PE as well so that the EEH device to form
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * another tree except the currently existing tree of PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * buses and PCI devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define EEH_DEV_BRIDGE (1 << 0) /* PCI bridge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define EEH_DEV_ROOT_PORT (1 << 1) /* PCIe root port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define EEH_DEV_DS_PORT (1 << 2) /* Downstream port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define EEH_DEV_IRQ_DISABLED (1 << 3) /* Interrupt disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define EEH_DEV_DISCONNECTED (1 << 4) /* Removing from PE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define EEH_DEV_NO_HANDLER (1 << 8) /* No error handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define EEH_DEV_SYSFS (1 << 9) /* Sysfs created */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define EEH_DEV_REMOVED (1 << 10) /* Removed permanently */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct eeh_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) int mode; /* EEH mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) int bdfn; /* bdfn of device (for cfg ops) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct pci_controller *controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) int pe_config_addr; /* PE config address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) u32 config_space[16]; /* Saved PCI config space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) int pcix_cap; /* Saved PCIx capability */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) int pcie_cap; /* Saved PCIe capability */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) int aer_cap; /* Saved AER capability */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) int af_cap; /* Saved AF capability */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct eeh_pe *pe; /* Associated PE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct list_head entry; /* Membership in eeh_pe.edevs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct list_head rmv_entry; /* Membership in rmv_list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct pci_dn *pdn; /* Associated PCI device node */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct pci_dev *pdev; /* Associated PCI device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) bool in_error; /* Error flag for edev */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* VF specific properties */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct pci_dev *physfn; /* Associated SRIOV PF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) int vf_index; /* Index of this VF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* "fmt" must be a simple literal string */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define EEH_EDEV_PRINT(level, edev, fmt, ...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) pr_##level("PCI %04x:%02x:%02x.%x#%04x: EEH: " fmt, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) (edev)->controller->global_number, PCI_BUSNO((edev)->bdfn), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) PCI_SLOT((edev)->bdfn), PCI_FUNC((edev)->bdfn), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) ((edev)->pe ? (edev)->pe_config_addr : 0xffff), ##__VA_ARGS__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define eeh_edev_dbg(edev, fmt, ...) EEH_EDEV_PRINT(debug, (edev), fmt, ##__VA_ARGS__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define eeh_edev_info(edev, fmt, ...) EEH_EDEV_PRINT(info, (edev), fmt, ##__VA_ARGS__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define eeh_edev_warn(edev, fmt, ...) EEH_EDEV_PRINT(warn, (edev), fmt, ##__VA_ARGS__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define eeh_edev_err(edev, fmt, ...) EEH_EDEV_PRINT(err, (edev), fmt, ##__VA_ARGS__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static inline struct pci_dn *eeh_dev_to_pdn(struct eeh_dev *edev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return edev ? edev->pdn : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static inline struct pci_dev *eeh_dev_to_pci_dev(struct eeh_dev *edev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return edev ? edev->pdev : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static inline struct eeh_pe *eeh_dev_to_pe(struct eeh_dev* edev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return edev ? edev->pe : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* Return values from eeh_ops::next_error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) EEH_NEXT_ERR_NONE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) EEH_NEXT_ERR_INF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) EEH_NEXT_ERR_FROZEN_PE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) EEH_NEXT_ERR_FENCED_PHB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) EEH_NEXT_ERR_DEAD_PHB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) EEH_NEXT_ERR_DEAD_IOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * The struct is used to trace the registered EEH operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * callback functions. Actually, those operation callback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * functions are heavily platform dependent. That means the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * platform should register its own EEH operation callback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * functions before any EEH further operations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define EEH_OPT_DISABLE 0 /* EEH disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define EEH_OPT_ENABLE 1 /* EEH enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define EEH_OPT_THAW_MMIO 2 /* MMIO enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define EEH_OPT_THAW_DMA 3 /* DMA enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define EEH_OPT_FREEZE_PE 4 /* Freeze PE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define EEH_STATE_UNAVAILABLE (1 << 0) /* State unavailable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define EEH_STATE_NOT_SUPPORT (1 << 1) /* EEH not supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define EEH_STATE_RESET_ACTIVE (1 << 2) /* Active reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define EEH_STATE_MMIO_ACTIVE (1 << 3) /* Active MMIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define EEH_STATE_DMA_ACTIVE (1 << 4) /* Active DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define EEH_STATE_MMIO_ENABLED (1 << 5) /* MMIO enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define EEH_STATE_DMA_ENABLED (1 << 6) /* DMA enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define EEH_RESET_DEACTIVATE 0 /* Deactivate the PE reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define EEH_RESET_HOT 1 /* Hot reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define EEH_RESET_FUNDAMENTAL 3 /* Fundamental reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define EEH_LOG_TEMP 1 /* EEH temporary error log */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define EEH_LOG_PERM 2 /* EEH permanent error log */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct eeh_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct eeh_dev *(*probe)(struct pci_dev *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) int (*set_option)(struct eeh_pe *pe, int option);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) int (*get_state)(struct eeh_pe *pe, int *delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) int (*reset)(struct eeh_pe *pe, int option);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) int (*get_log)(struct eeh_pe *pe, int severity, char *drv_log, unsigned long len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) int (*configure_bridge)(struct eeh_pe *pe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) int (*err_inject)(struct eeh_pe *pe, int type, int func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) unsigned long addr, unsigned long mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) int (*read_config)(struct eeh_dev *edev, int where, int size, u32 *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) int (*write_config)(struct eeh_dev *edev, int where, int size, u32 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) int (*next_error)(struct eeh_pe **pe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) int (*restore_config)(struct eeh_dev *edev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) int (*notify_resume)(struct eeh_dev *edev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) extern int eeh_subsystem_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) extern u32 eeh_max_freezes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) extern bool eeh_debugfs_no_recover;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) extern struct eeh_ops *eeh_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) extern raw_spinlock_t confirm_error_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static inline void eeh_add_flag(int flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) eeh_subsystem_flags |= flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static inline void eeh_clear_flag(int flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) eeh_subsystem_flags &= ~flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static inline bool eeh_has_flag(int flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return !!(eeh_subsystem_flags & flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static inline bool eeh_enabled(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return eeh_has_flag(EEH_ENABLED) && !eeh_has_flag(EEH_FORCE_DISABLED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static inline void eeh_serialize_lock(unsigned long *flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) raw_spin_lock_irqsave(&confirm_error_lock, *flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static inline void eeh_serialize_unlock(unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) raw_spin_unlock_irqrestore(&confirm_error_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static inline bool eeh_state_active(int state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return (state & (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) == (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) typedef void (*eeh_edev_traverse_func)(struct eeh_dev *edev, void *flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) typedef void *(*eeh_pe_traverse_func)(struct eeh_pe *pe, void *flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) void eeh_set_pe_aux_size(int size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) int eeh_phb_pe_create(struct pci_controller *phb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) int eeh_wait_state(struct eeh_pe *pe, int max_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct eeh_pe *eeh_phb_pe_get(struct pci_controller *phb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) struct eeh_pe *eeh_pe_next(struct eeh_pe *pe, struct eeh_pe *root);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) struct eeh_pe *eeh_pe_get(struct pci_controller *phb, int pe_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) int eeh_pe_tree_insert(struct eeh_dev *edev, struct eeh_pe *new_pe_parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) int eeh_pe_tree_remove(struct eeh_dev *edev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) void eeh_pe_update_time_stamp(struct eeh_pe *pe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) void *eeh_pe_traverse(struct eeh_pe *root,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) eeh_pe_traverse_func fn, void *flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) void eeh_pe_dev_traverse(struct eeh_pe *root,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) eeh_edev_traverse_func fn, void *flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) void eeh_pe_restore_bars(struct eeh_pe *pe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) const char *eeh_pe_loc_get(struct eeh_pe *pe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) struct pci_bus *eeh_pe_bus_get(struct eeh_pe *pe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) void eeh_show_enabled(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) int __init eeh_init(struct eeh_ops *ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) int eeh_check_failure(const volatile void __iomem *token);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) int eeh_dev_check_failure(struct eeh_dev *edev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) void eeh_addr_cache_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) void eeh_probe_device(struct pci_dev *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) void eeh_remove_device(struct pci_dev *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) int eeh_unfreeze_pe(struct eeh_pe *pe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) int eeh_pe_reset_and_recover(struct eeh_pe *pe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) int eeh_dev_open(struct pci_dev *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) void eeh_dev_release(struct pci_dev *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct eeh_pe *eeh_iommu_group_to_pe(struct iommu_group *group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) int eeh_pe_set_option(struct eeh_pe *pe, int option);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) int eeh_pe_get_state(struct eeh_pe *pe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) int eeh_pe_reset(struct eeh_pe *pe, int option, bool include_passed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) int eeh_pe_configure(struct eeh_pe *pe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) int eeh_pe_inject_err(struct eeh_pe *pe, int type, int func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) unsigned long addr, unsigned long mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * EEH_POSSIBLE_ERROR() -- test for possible MMIO failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * If this macro yields TRUE, the caller relays to eeh_check_failure()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * which does further tests out of line.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define EEH_POSSIBLE_ERROR(val, type) ((val) == (type)~0 && eeh_enabled())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * Reads from a device which has been isolated by EEH will return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * all 1s. This macro gives an all-1s value of the given size (in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) * bytes: 1, 2, or 4) for comparing with the result of a read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define EEH_IO_ERROR_VALUE(size) (~0U >> ((4 - (size)) * 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #else /* !CONFIG_EEH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static inline bool eeh_enabled(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static inline void eeh_show_enabled(void) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static inline void eeh_dev_phb_init_dynamic(struct pci_controller *phb) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static inline int eeh_check_failure(const volatile void __iomem *token)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define eeh_dev_check_failure(x) (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static inline void eeh_addr_cache_init(void) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static inline void eeh_probe_device(struct pci_dev *dev) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static inline void eeh_remove_device(struct pci_dev *dev) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define EEH_POSSIBLE_ERROR(val, type) (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define EEH_IO_ERROR_VALUE(size) (-1UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static inline int eeh_phb_pe_create(struct pci_controller *phb) { return 0; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #endif /* CONFIG_EEH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #if defined(CONFIG_PPC_PSERIES) && defined(CONFIG_EEH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) void pseries_eeh_init_edev(struct pci_dn *pdn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) void pseries_eeh_init_edev_recursive(struct pci_dn *pdn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static inline void pseries_eeh_add_device_early(struct pci_dn *pdn) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static inline void pseries_eeh_add_device_tree_early(struct pci_dn *pdn) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #ifdef CONFIG_PPC64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * MMIO read/write operations with EEH support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static inline u8 eeh_readb(const volatile void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) u8 val = in_8(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (EEH_POSSIBLE_ERROR(val, u8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) eeh_check_failure(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static inline u16 eeh_readw(const volatile void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) u16 val = in_le16(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (EEH_POSSIBLE_ERROR(val, u16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) eeh_check_failure(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static inline u32 eeh_readl(const volatile void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) u32 val = in_le32(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (EEH_POSSIBLE_ERROR(val, u32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) eeh_check_failure(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static inline u64 eeh_readq(const volatile void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) u64 val = in_le64(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (EEH_POSSIBLE_ERROR(val, u64))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) eeh_check_failure(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static inline u16 eeh_readw_be(const volatile void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) u16 val = in_be16(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if (EEH_POSSIBLE_ERROR(val, u16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) eeh_check_failure(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static inline u32 eeh_readl_be(const volatile void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) u32 val = in_be32(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (EEH_POSSIBLE_ERROR(val, u32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) eeh_check_failure(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) static inline u64 eeh_readq_be(const volatile void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) u64 val = in_be64(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (EEH_POSSIBLE_ERROR(val, u64))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) eeh_check_failure(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static inline void eeh_memcpy_fromio(void *dest, const
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) volatile void __iomem *src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) unsigned long n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) _memcpy_fromio(dest, src, n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) /* Look for ffff's here at dest[n]. Assume that at least 4 bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * were copied. Check all four bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (n >= 4 && EEH_POSSIBLE_ERROR(*((u32 *)(dest + n - 4)), u32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) eeh_check_failure(src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /* in-string eeh macros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static inline void eeh_readsb(const volatile void __iomem *addr, void * buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) int ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) _insb(addr, buf, ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if (EEH_POSSIBLE_ERROR((*(((u8*)buf)+ns-1)), u8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) eeh_check_failure(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) static inline void eeh_readsw(const volatile void __iomem *addr, void * buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) int ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) _insw(addr, buf, ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (EEH_POSSIBLE_ERROR((*(((u16*)buf)+ns-1)), u16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) eeh_check_failure(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static inline void eeh_readsl(const volatile void __iomem *addr, void * buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) int nl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) _insl(addr, buf, nl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (EEH_POSSIBLE_ERROR((*(((u32*)buf)+nl-1)), u32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) eeh_check_failure(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) void eeh_cache_debugfs_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #endif /* CONFIG_PPC64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #endif /* __KERNEL__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #endif /* _POWERPC_EEH_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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