^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * drmem.h: Power specific logical memory block representation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2017 IBM Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef _ASM_POWERPC_LMB_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define _ASM_POWERPC_LMB_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) struct drmem_lmb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) u64 base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) u32 drc_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) u32 aa_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) struct drmem_lmb_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct drmem_lmb *lmbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) int n_lmbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) u64 lmb_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) extern struct drmem_lmb_info *drmem_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static inline struct drmem_lmb *drmem_lmb_next(struct drmem_lmb *lmb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) const struct drmem_lmb *start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * DLPAR code paths can take several milliseconds per element
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * when interacting with firmware. Ensure that we don't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * unfairly monopolize the CPU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) if (((++lmb - start) % 16) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) cond_resched();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) return lmb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define for_each_drmem_lmb_in_range(lmb, start, end) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) for ((lmb) = (start); (lmb) < (end); lmb = drmem_lmb_next(lmb, start))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define for_each_drmem_lmb(lmb) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) for_each_drmem_lmb_in_range((lmb), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) &drmem_info->lmbs[0], \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) &drmem_info->lmbs[drmem_info->n_lmbs])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * The of_drconf_cell_v1 struct defines the layout of the LMB data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * specified in the ibm,dynamic-memory device tree property.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * The property itself is a 32-bit value specifying the number of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * LMBs followed by an array of of_drconf_cell_v1 entries, one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * per LMB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct of_drconf_cell_v1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) __be64 base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) __be32 drc_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) __be32 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) __be32 aa_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) __be32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * Version 2 of the ibm,dynamic-memory property is defined as a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * 32-bit value specifying the number of LMB sets followed by an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * array of of_drconf_cell_v2 entries, one per LMB set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct of_drconf_cell_v2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u32 seq_lmbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u64 base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u32 drc_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u32 aa_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define DRCONF_MEM_ASSIGNED 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define DRCONF_MEM_AI_INVALID 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define DRCONF_MEM_RESERVED 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define DRCONF_MEM_HOTREMOVABLE 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static inline u64 drmem_lmb_size(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return drmem_info->lmb_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define DRMEM_LMB_RESERVED 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static inline void drmem_mark_lmb_reserved(struct drmem_lmb *lmb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) lmb->flags |= DRMEM_LMB_RESERVED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static inline void drmem_remove_lmb_reservation(struct drmem_lmb *lmb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) lmb->flags &= ~DRMEM_LMB_RESERVED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static inline bool drmem_lmb_reserved(struct drmem_lmb *lmb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return lmb->flags & DRMEM_LMB_RESERVED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u64 drmem_lmb_memory_max(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) int walk_drmem_lmbs(struct device_node *dn, void *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) int (*func)(struct drmem_lmb *, const __be32 **, void *));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) int drmem_update_dt(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #ifdef CONFIG_PPC_PSERIES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) int __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) walk_drmem_lmbs_early(unsigned long node, void *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) int (*func)(struct drmem_lmb *, const __be32 **, void *));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static inline void invalidate_lmb_associativity_index(struct drmem_lmb *lmb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) lmb->aa_index = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #endif /* _ASM_POWERPC_LMB_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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