Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * (c) Copyright 2006 Benjamin Herrenschmidt, IBM Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *                    <benh@kernel.crashing.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #ifndef _ASM_POWERPC_DCR_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #define _ASM_POWERPC_DCR_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #ifdef __KERNEL__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifdef CONFIG_PPC_DCR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #ifdef CONFIG_PPC_DCR_NATIVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/dcr-native.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #ifdef CONFIG_PPC_DCR_MMIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/dcr-mmio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* Indirection layer for providing both NATIVE and MMIO support. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #if defined(CONFIG_PPC_DCR_NATIVE) && defined(CONFIG_PPC_DCR_MMIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/dcr-generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DCR_MAP_OK(host)	dcr_map_ok_generic(host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define dcr_map(dev, dcr_n, dcr_c) dcr_map_generic(dev, dcr_n, dcr_c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define dcr_unmap(host, dcr_c) dcr_unmap_generic(host, dcr_c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define dcr_read(host, dcr_n) dcr_read_generic(host, dcr_n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define dcr_write(host, dcr_n, value) dcr_write_generic(host, dcr_n, value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #ifdef CONFIG_PPC_DCR_NATIVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) typedef dcr_host_native_t dcr_host_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DCR_MAP_OK(host)	dcr_map_ok_native(host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define dcr_map(dev, dcr_n, dcr_c) dcr_map_native(dev, dcr_n, dcr_c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define dcr_unmap(host, dcr_c) dcr_unmap_native(host, dcr_c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define dcr_read(host, dcr_n) dcr_read_native(host, dcr_n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define dcr_write(host, dcr_n, value) dcr_write_native(host, dcr_n, value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) typedef dcr_host_mmio_t dcr_host_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define DCR_MAP_OK(host)	dcr_map_ok_mmio(host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define dcr_map(dev, dcr_n, dcr_c) dcr_map_mmio(dev, dcr_n, dcr_c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define dcr_unmap(host, dcr_c) dcr_unmap_mmio(host, dcr_c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define dcr_read(host, dcr_n) dcr_read_mmio(host, dcr_n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define dcr_write(host, dcr_n, value) dcr_write_mmio(host, dcr_n, value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #endif /* defined(CONFIG_PPC_DCR_NATIVE) && defined(CONFIG_PPC_DCR_MMIO) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)  * additional helpers to read the DCR * base from the device-tree
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct device_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) extern unsigned int dcr_resource_start(const struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 				       unsigned int index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) extern unsigned int dcr_resource_len(const struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 				     unsigned int index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #endif /* CONFIG_PPC_DCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #endif /* __ASSEMBLY__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #endif /* __KERNEL__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #endif /* _ASM_POWERPC_DCR_H */