^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Common DCR / SDR / CPR register definitions used on various IBM/AMCC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * 4xx processors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright 2007 Benjamin Herrenschmidt, IBM Corp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * <benh@kernel.crashing.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Mostly lifted from asm-ppc/ibm4xx.h by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #ifndef __DCR_REGS_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define __DCR_REGS_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * Most DCRs used for controlling devices such as the MAL, DMA engine,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * etc... are obtained for the device tree.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * The definitions in this files are fixed DCRs and indirect DCRs that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * are commonly used outside of specific drivers or refer to core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * common registers that may occasionally have to be tweaked outside
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * of the driver main register set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* CPRs (440GX and 440SP/440SPe) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DCRN_CPR0_CONFIG_ADDR 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DCRN_CPR0_CONFIG_DATA 0xd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* SDRs (440GX and 440SP/440SPe) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DCRN_SDR0_CONFIG_ADDR 0xe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DCRN_SDR0_CONFIG_DATA 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SDR0_PFC0 0x4100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SDR0_PFC1 0x4101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SDR0_PFC1_EPS 0x1c00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SDR0_PFC1_EPS_SHIFT 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SDR0_PFC1_RMII 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SDR0_MFR 0x4300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SDR0_MFR_TAH0 0x80000000 /* TAHOE0 Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SDR0_MFR_TAH1 0x40000000 /* TAHOE1 Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SDR0_MFR_PCM 0x10000000 /* PPC440GP irq compat mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SDR0_MFR_ECS 0x08000000 /* EMAC int clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SDR0_MFR_T0TXFL 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SDR0_MFR_T0TXFH 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SDR0_MFR_T1TXFL 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SDR0_MFR_T1TXFH 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SDR0_MFR_E0TXFL 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SDR0_MFR_E0TXFH 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SDR0_MFR_E0RXFL 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SDR0_MFR_E0RXFH 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SDR0_MFR_E1TXFL 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SDR0_MFR_E1TXFH 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SDR0_MFR_E1RXFL 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SDR0_MFR_E1RXFH 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SDR0_MFR_E2TXFL 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SDR0_MFR_E2TXFH 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SDR0_MFR_E2RXFL 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SDR0_MFR_E2RXFH 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SDR0_MFR_E3TXFL 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SDR0_MFR_E3TXFH 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SDR0_MFR_E3RXFL 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SDR0_MFR_E3RXFH 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SDR0_UART0 0x0120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SDR0_UART1 0x0121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SDR0_UART2 0x0122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SDR0_UART3 0x0123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SDR0_CUST0 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* SDR for 405EZ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define DCRN_SDR_ICINTSTAT 0x4510
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define ICINTSTAT_ICRX 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define ICINTSTAT_ICTX0 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define ICINTSTAT_ICTX1 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define ICINTSTAT_ICTX 0x60000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* SDRs (460EX/460GT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SDR0_ETH_CFG 0x4103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SDR0_ETH_CFG_ECS 0x00000100 /* EMAC int clk source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * All those DCR register addresses are offsets from the base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * for the SRAM0 controller (e.g. 0x20 on 440GX). The base address is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * excluded here and configured in the device tree.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define DCRN_SRAM0_SB0CR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define DCRN_SRAM0_SB1CR 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define DCRN_SRAM0_SB2CR 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define DCRN_SRAM0_SB3CR 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SRAM_SBCR_BU_MASK 0x00000180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SRAM_SBCR_BS_64KB 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SRAM_SBCR_BU_RO 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SRAM_SBCR_BU_RW 0x00000180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define DCRN_SRAM0_BEAR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define DCRN_SRAM0_BESR0 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define DCRN_SRAM0_BESR1 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define DCRN_SRAM0_PMEG 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define DCRN_SRAM0_CID 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define DCRN_SRAM0_REVID 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define DCRN_SRAM0_DPC 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SRAM_DPC_ENABLE 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * All those DCR register addresses are offsets from the base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * for the SRAM0 controller (e.g. 0x30 on 440GX). The base address is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * excluded here and configured in the device tree.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define DCRN_L2C0_CFG 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define L2C_CFG_L2M 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define L2C_CFG_ICU 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define L2C_CFG_DCU 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define L2C_CFG_DCW_MASK 0x1e000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define L2C_CFG_TPC 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define L2C_CFG_CPC 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define L2C_CFG_FRAN 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define L2C_CFG_SS_MASK 0x00180000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define L2C_CFG_SS_256 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define L2C_CFG_CPIM 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define L2C_CFG_TPIM 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define L2C_CFG_LIM 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define L2C_CFG_PMUX_MASK 0x00007000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define L2C_CFG_PMUX_SNP 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define L2C_CFG_PMUX_IF 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define L2C_CFG_PMUX_DF 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define L2C_CFG_PMUX_DS 0x00003000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define L2C_CFG_PMIM 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define L2C_CFG_TPEI 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define L2C_CFG_CPEI 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define L2C_CFG_NAM 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define L2C_CFG_SMCM 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define L2C_CFG_NBRM 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define L2C_CFG_RDBW 0x00000008 /* only 460EX/GT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define DCRN_L2C0_CMD 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define L2C_CMD_CLR 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define L2C_CMD_DIAG 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define L2C_CMD_INV 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define L2C_CMD_CCP 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define L2C_CMD_CTE 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define L2C_CMD_STRC 0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define L2C_CMD_STPC 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define L2C_CMD_RPMC 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define L2C_CMD_HCC 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define DCRN_L2C0_ADDR 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define DCRN_L2C0_DATA 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define DCRN_L2C0_SR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define L2C_SR_CC 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define L2C_SR_CPE 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define L2C_SR_TPE 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define L2C_SR_LRU 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define L2C_SR_PCS 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define DCRN_L2C0_REVID 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define DCRN_L2C0_SNP0 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define DCRN_L2C0_SNP1 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define L2C_SNP_BA_MASK 0xffff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define L2C_SNP_SSR_MASK 0x0000f000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define L2C_SNP_SSR_32G 0x0000f000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define L2C_SNP_ESR 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * DCR register offsets for 440SP/440SPe I2O/DMA controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * The base address is configured in the device tree.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define DCRN_I2O0_IBAL 0x006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define DCRN_I2O0_IBAH 0x007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define I2O_REG_ENABLE 0x00000001 /* Enable I2O/DMA access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* 440SP/440SPe Software Reset DCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define DCRN_SDR0_SRST 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define DCRN_SDR0_SRST_I2ODMA (0x80000000 >> 15) /* Reset I2O/DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* 440SP/440SPe Memory Queue DCR offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define DCRN_MQ0_XORBA 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define DCRN_MQ0_CF2H 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define DCRN_MQ0_CFBHL 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define DCRN_MQ0_BAUH 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* HB/LL Paths Configuration Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define MQ0_CFBHL_TPLM 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define MQ0_CFBHL_HBCL 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define MQ0_CFBHL_POLY 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #endif /* __DCR_REGS_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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