^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Definitions for using the Apple Descriptor-Based DMA controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * in Power Macintosh computers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 1996 Paul Mackerras.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifdef __KERNEL__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef _ASM_DBDMA_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define _ASM_DBDMA_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * DBDMA control/status registers. All little-endian.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) struct dbdma_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) unsigned int control; /* lets you change bits in status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) unsigned int status; /* DMA and device status bits (see below) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) unsigned int cmdptr_hi; /* upper 32 bits of command address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) unsigned int cmdptr; /* (lower 32 bits of) command address (phys) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) unsigned int intr_sel; /* select interrupt condition bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) unsigned int br_sel; /* select branch condition bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) unsigned int wait_sel; /* select wait condition bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) unsigned int xfer_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) unsigned int data2ptr_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) unsigned int data2ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) unsigned int res1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) unsigned int address_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) unsigned int br_addr_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) unsigned int res2[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* Bits in control and status registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define RUN 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PAUSE 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define FLUSH 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define WAKE 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DEAD 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ACTIVE 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define BT 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DEVSTAT 0x00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * DBDMA command structure. These fields are all little-endian!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct dbdma_cmd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) __le16 req_count; /* requested byte transfer count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) __le16 command; /* command word (has bit-fields) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) __le32 phy_addr; /* physical data address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) __le32 cmd_dep; /* command-dependent field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) __le16 res_count; /* residual count after completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) __le16 xfer_status; /* transfer status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* DBDMA command values in command field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define OUTPUT_MORE 0 /* transfer memory data to stream */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define OUTPUT_LAST 0x1000 /* ditto followed by end marker */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define INPUT_MORE 0x2000 /* transfer stream data to memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define INPUT_LAST 0x3000 /* ditto, expect end marker */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define STORE_WORD 0x4000 /* write word (4 bytes) to device reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define LOAD_WORD 0x5000 /* read word (4 bytes) from device reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define DBDMA_NOP 0x6000 /* do nothing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define DBDMA_STOP 0x7000 /* suspend processing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* Key values in command field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define KEY_STREAM0 0 /* usual data stream */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define KEY_STREAM1 0x100 /* control/status stream */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define KEY_STREAM2 0x200 /* device-dependent stream */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define KEY_STREAM3 0x300 /* device-dependent stream */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define KEY_REGS 0x500 /* device register space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define KEY_SYSTEM 0x600 /* system memory-mapped space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define KEY_DEVICE 0x700 /* device memory-mapped space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* Interrupt control values in command field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define INTR_NEVER 0 /* don't interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define INTR_IFSET 0x10 /* intr if condition bit is 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define INTR_IFCLR 0x20 /* intr if condition bit is 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define INTR_ALWAYS 0x30 /* always interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* Branch control values in command field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define BR_NEVER 0 /* don't branch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define BR_IFSET 0x4 /* branch if condition bit is 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define BR_IFCLR 0x8 /* branch if condition bit is 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define BR_ALWAYS 0xc /* always branch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* Wait control values in command field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define WAIT_NEVER 0 /* don't wait */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define WAIT_IFSET 1 /* wait if condition bit is 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define WAIT_IFCLR 2 /* wait if condition bit is 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define WAIT_ALWAYS 3 /* always wait */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* Align an address for a DBDMA command structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define DBDMA_ALIGN(x) (((unsigned long)(x) + sizeof(struct dbdma_cmd) - 1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) & -sizeof(struct dbdma_cmd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* Useful macros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define DBDMA_DO_STOP(regs) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) out_le32(&((regs)->control), (RUN|FLUSH)<<16); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) while(in_le32(&((regs)->status)) & (ACTIVE|FLUSH)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) ; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define DBDMA_DO_RESET(regs) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) out_le32(&((regs)->control), (ACTIVE|DEAD|WAKE|FLUSH|PAUSE|RUN)<<16);\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) while(in_le32(&((regs)->status)) & (RUN)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) ; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #endif /* _ASM_DBDMA_H_ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #endif /* __KERNEL__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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