^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef __ASM_POWERPC_CPUTABLE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define __ASM_POWERPC_CPUTABLE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <uapi/asm/cputable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <asm/asm-const.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /* This structure can grow, it's real size is used by head.S code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * via the mkdefs mechanism.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) struct cpu_spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) typedef void (*cpu_restore_t)(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) enum powerpc_oprofile_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) PPC_OPROFILE_INVALID = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) PPC_OPROFILE_RS64 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) PPC_OPROFILE_POWER4 = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) PPC_OPROFILE_G4 = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) PPC_OPROFILE_FSL_EMB = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) PPC_OPROFILE_CELL = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) PPC_OPROFILE_PA6T = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) enum powerpc_pmc_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) PPC_PMC_DEFAULT = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) PPC_PMC_IBM = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) PPC_PMC_PA6T = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) PPC_PMC_G4 = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct pt_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) extern int machine_check_generic(struct pt_regs *regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) extern int machine_check_4xx(struct pt_regs *regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) extern int machine_check_440A(struct pt_regs *regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) extern int machine_check_e500mc(struct pt_regs *regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) extern int machine_check_e500(struct pt_regs *regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) extern int machine_check_e200(struct pt_regs *regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) extern int machine_check_47x(struct pt_regs *regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) int machine_check_8xx(struct pt_regs *regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) int machine_check_83xx(struct pt_regs *regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) extern void cpu_down_flush_e500v2(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) extern void cpu_down_flush_e500mc(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) extern void cpu_down_flush_e5500(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) extern void cpu_down_flush_e6500(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* NOTE WELL: Update identify_cpu() if fields are added or removed! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct cpu_spec {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* CPU is matched via (PVR & pvr_mask) == pvr_value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) unsigned int pvr_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) unsigned int pvr_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) char *cpu_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) unsigned long cpu_features; /* Kernel features */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) unsigned int cpu_user_features; /* Userland features */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) unsigned int cpu_user_features2; /* Userland features v2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) unsigned int mmu_features; /* MMU features */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* cache line sizes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) unsigned int icache_bsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) unsigned int dcache_bsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* flush caches inside the current cpu */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) void (*cpu_down_flush)(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* number of performance monitor counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) unsigned int num_pmcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) enum powerpc_pmc_type pmc_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* this is called to initialize various CPU bits like L1 cache,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * BHT, SPD, etc... from head.S before branching to identify_machine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) cpu_setup_t cpu_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* Used to restore cpu setup on secondary processors and at resume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) cpu_restore_t cpu_restore;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* Used by oprofile userspace to select the right counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) char *oprofile_cpu_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* Processor specific oprofile operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) enum powerpc_oprofile_type oprofile_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* Bit locations inside the mmcra change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) unsigned long oprofile_mmcra_sihv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) unsigned long oprofile_mmcra_sipr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* Bits to clear during an oprofile exception */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) unsigned long oprofile_mmcra_clear;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* Name of processor class, for the ELF AT_PLATFORM entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) char *platform;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* Processor specific machine check handling. Return negative
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * if the error is fatal, 1 if it was fully recovered and 0 to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * pass up (not CPU originated) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) int (*machine_check)(struct pt_regs *regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * Processor specific early machine check handler which is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * called in real mode to handle SLB and TLB errors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) long (*machine_check_early)(struct pt_regs *regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) extern struct cpu_spec *cur_cpu_spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) extern void set_cur_cpu_spec(struct cpu_spec *s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) extern void identify_cpu_name(unsigned int pvr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) extern void do_feature_fixups(unsigned long value, void *fixup_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) void *fixup_end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) extern const char *powerpc_base_platform;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #ifdef CONFIG_JUMP_LABEL_FEATURE_CHECKS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) extern void cpu_feature_keys_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static inline void cpu_feature_keys_init(void) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #endif /* __ASSEMBLY__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* CPU kernel features */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* Definitions for features that we have on both 32-bit and 64-bit chips */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define CPU_FTR_ALTIVEC ASM_CONST(0x00000002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define CPU_FTR_DBELL ASM_CONST(0x00000004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define CPU_FTR_CAN_NAP ASM_CONST(0x00000008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define CPU_FTR_DEBUG_LVL_EXC ASM_CONST(0x00000010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define CPU_FTR_NODSISRALIGN ASM_CONST(0x00000020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x00000040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define CPU_FTR_LWSYNC ASM_CONST(0x00000080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define CPU_FTR_NOEXECUTE ASM_CONST(0x00000100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define CPU_FTR_EMB_HV ASM_CONST(0x00000200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* Definitions for features that only exist on 32-bit chips */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #ifdef CONFIG_PPC32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define CPU_FTR_L2CR ASM_CONST(0x00002000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define CPU_FTR_SPEC7450 ASM_CONST(0x00004000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define CPU_FTR_TAU ASM_CONST(0x00008000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define CPU_FTR_CAN_DOZE ASM_CONST(0x00010000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define CPU_FTR_L3CR ASM_CONST(0x00040000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x00080000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x00100000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x00200000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define CPU_FTR_NO_DPM ASM_CONST(0x00400000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define CPU_FTR_476_DD2 ASM_CONST(0x00800000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define CPU_FTR_NEED_COHERENT ASM_CONST(0x01000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define CPU_FTR_NO_BTIC ASM_CONST(0x02000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define CPU_FTR_PPC_LE ASM_CONST(0x04000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define CPU_FTR_SPE ASM_CONST(0x10000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define CPU_FTR_NEED_PAIRED_STWCX ASM_CONST(0x20000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define CPU_FTR_INDEXED_DCR ASM_CONST(0x40000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #else /* CONFIG_PPC32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* Define these to 0 for the sake of tests in common code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define CPU_FTR_PPC_LE (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define CPU_FTR_SPE (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * Definitions for the 64-bit processor unique features;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * on 32-bit, make the names available but defined to be 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #ifdef __powerpc64__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define LONG_ASM_CONST(x) ASM_CONST(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define LONG_ASM_CONST(x) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define CPU_FTR_REAL_LE LONG_ASM_CONST(0x0000000000001000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define CPU_FTR_HVMODE LONG_ASM_CONST(0x0000000000002000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define CPU_FTR_ARCH_206 LONG_ASM_CONST(0x0000000000008000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define CPU_FTR_ARCH_207S LONG_ASM_CONST(0x0000000000010000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define CPU_FTR_ARCH_300 LONG_ASM_CONST(0x0000000000020000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000000000040000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define CPU_FTR_CTRL LONG_ASM_CONST(0x0000000000080000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define CPU_FTR_SMT LONG_ASM_CONST(0x0000000000100000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000000000200000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define CPU_FTR_PURR LONG_ASM_CONST(0x0000000000400000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000000000800000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define CPU_FTR_SPURR LONG_ASM_CONST(0x0000000001000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define CPU_FTR_DSCR LONG_ASM_CONST(0x0000000002000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define CPU_FTR_VSX LONG_ASM_CONST(0x0000000004000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define CPU_FTR_SAO LONG_ASM_CONST(0x0000000008000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define CPU_FTR_CP_USE_DCBTZ LONG_ASM_CONST(0x0000000010000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define CPU_FTR_UNALIGNED_LD_STD LONG_ASM_CONST(0x0000000020000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define CPU_FTR_ASYM_SMT LONG_ASM_CONST(0x0000000040000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define CPU_FTR_STCX_CHECKS_ADDRESS LONG_ASM_CONST(0x0000000080000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define CPU_FTR_POPCNTB LONG_ASM_CONST(0x0000000100000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define CPU_FTR_POPCNTD LONG_ASM_CONST(0x0000000200000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* LONG_ASM_CONST(0x0000000400000000) Free */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define CPU_FTR_VMX_COPY LONG_ASM_CONST(0x0000000800000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define CPU_FTR_TM LONG_ASM_CONST(0x0000001000000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define CPU_FTR_CFAR LONG_ASM_CONST(0x0000002000000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define CPU_FTR_HAS_PPR LONG_ASM_CONST(0x0000004000000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define CPU_FTR_DAWR LONG_ASM_CONST(0x0000008000000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define CPU_FTR_DABRX LONG_ASM_CONST(0x0000010000000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define CPU_FTR_PMAO_BUG LONG_ASM_CONST(0x0000020000000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define CPU_FTR_POWER9_DD2_1 LONG_ASM_CONST(0x0000080000000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define CPU_FTR_P9_TM_HV_ASSIST LONG_ASM_CONST(0x0000100000000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define CPU_FTR_P9_TM_XER_SO_BUG LONG_ASM_CONST(0x0000200000000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define CPU_FTR_P9_TLBIE_STQ_BUG LONG_ASM_CONST(0x0000400000000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define CPU_FTR_P9_TIDR LONG_ASM_CONST(0x0000800000000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define CPU_FTR_P9_TLBIE_ERAT_BUG LONG_ASM_CONST(0x0001000000000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define CPU_FTR_P9_RADIX_PREFETCH_BUG LONG_ASM_CONST(0x0002000000000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define CPU_FTR_ARCH_31 LONG_ASM_CONST(0x0004000000000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define CPU_FTR_DAWR1 LONG_ASM_CONST(0x0008000000000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define MMU_FTR_PPCAS_ARCH_V2 (MMU_FTR_TLBIEL | MMU_FTR_16M_PAGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* We only set the altivec features if the kernel was compiled with altivec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #ifdef CONFIG_ALTIVEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define CPU_FTR_ALTIVEC_COMP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define PPC_FEATURE_HAS_ALTIVEC_COMP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* We only set the VSX features if the kernel was compiled with VSX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #ifdef CONFIG_VSX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define CPU_FTR_VSX_COMP CPU_FTR_VSX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define PPC_FEATURE_HAS_VSX_COMP PPC_FEATURE_HAS_VSX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define CPU_FTR_VSX_COMP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define PPC_FEATURE_HAS_VSX_COMP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* We only set the spe features if the kernel was compiled with spe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #ifdef CONFIG_SPE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define CPU_FTR_SPE_COMP CPU_FTR_SPE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define CPU_FTR_SPE_COMP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define PPC_FEATURE_HAS_SPE_COMP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* We only set the TM feature if the kernel was compiled with TM supprt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define CPU_FTR_TM_COMP CPU_FTR_TM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define PPC_FEATURE2_HTM_COMP PPC_FEATURE2_HTM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define PPC_FEATURE2_HTM_NOSC_COMP PPC_FEATURE2_HTM_NOSC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define CPU_FTR_TM_COMP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define PPC_FEATURE2_HTM_COMP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define PPC_FEATURE2_HTM_NOSC_COMP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* We need to mark all pages as being coherent if we're SMP or we have a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * require it for PCI "streaming/prefetch" to work properly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * This is also required by 52xx family.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) || defined(CONFIG_PPC_MPC52xx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define CPU_FTR_COMMON 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* The powersave features NAP & DOZE seems to confuse BDI when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) debugging. So if a BDI is used, disable theses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #ifndef CONFIG_BDI_SWITCH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define CPU_FTR_MAYBE_CAN_DOZE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define CPU_FTR_MAYBE_CAN_NAP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define CPU_FTRS_603 (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE | CPU_FTR_NOEXECUTE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define CPU_FTRS_604 (CPU_FTR_COMMON | CPU_FTR_PPC_LE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define CPU_FTRS_740 (CPU_FTR_COMMON | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) CPU_FTR_PPC_LE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define CPU_FTRS_750 (CPU_FTR_COMMON | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) CPU_FTR_PPC_LE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define CPU_FTRS_750CL (CPU_FTRS_750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define CPU_FTRS_750FX1 (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define CPU_FTRS_750FX2 (CPU_FTRS_750 | CPU_FTR_NO_DPM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define CPU_FTRS_750FX (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define CPU_FTRS_750GX (CPU_FTRS_750FX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) CPU_FTR_ALTIVEC_COMP | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define CPU_FTRS_7400 (CPU_FTR_COMMON | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define CPU_FTRS_7450_20 (CPU_FTR_COMMON | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define CPU_FTRS_7450_21 (CPU_FTR_COMMON | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define CPU_FTRS_7450_23 (CPU_FTR_COMMON | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) CPU_FTR_NEED_PAIRED_STWCX | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) CPU_FTR_NEED_PAIRED_STWCX | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) CPU_FTR_SPEC7450 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define CPU_FTRS_7455_20 (CPU_FTR_COMMON | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) CPU_FTR_NEED_PAIRED_STWCX | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define CPU_FTRS_7455 (CPU_FTR_COMMON | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define CPU_FTRS_7447_10 (CPU_FTR_COMMON | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) CPU_FTR_NEED_PAIRED_STWCX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define CPU_FTRS_7447 (CPU_FTR_COMMON | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define CPU_FTRS_7447A (CPU_FTR_COMMON | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define CPU_FTRS_7448 (CPU_FTR_COMMON | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define CPU_FTRS_82XX (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_NOEXECUTE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define CPU_FTRS_G2_LE (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NOEXECUTE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) CPU_FTR_MAYBE_CAN_NAP | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) CPU_FTR_COMMON | CPU_FTR_NOEXECUTE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) CPU_FTR_MAYBE_CAN_NAP | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE | CPU_FTR_NOEXECUTE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define CPU_FTRS_8XX (CPU_FTR_NOEXECUTE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define CPU_FTRS_40X (CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define CPU_FTRS_44X (CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define CPU_FTRS_440x6 (CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) CPU_FTR_INDEXED_DCR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define CPU_FTRS_47X (CPU_FTRS_440x6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define CPU_FTRS_E200 (CPU_FTR_SPE_COMP | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) CPU_FTR_NOEXECUTE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) CPU_FTR_DEBUG_LVL_EXC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define CPU_FTRS_E500 (CPU_FTR_MAYBE_CAN_DOZE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) CPU_FTR_NOEXECUTE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define CPU_FTRS_E500MC (CPU_FTR_NODSISRALIGN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) CPU_FTR_DBELL | CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) * e5500/e6500 erratum A-006958 is a timebase bug that can use the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * same workaround as CPU_FTR_CELL_TB_BUG.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define CPU_FTRS_E5500 (CPU_FTR_NODSISRALIGN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_CELL_TB_BUG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define CPU_FTRS_E6500 (CPU_FTR_NODSISRALIGN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_ALTIVEC_COMP | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) CPU_FTR_CELL_TB_BUG | CPU_FTR_SMT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /* 64-bit CPUs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define CPU_FTRS_PPC970 (CPU_FTR_LWSYNC | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) CPU_FTR_CP_USE_DCBTZ | CPU_FTR_STCX_CHECKS_ADDRESS | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) CPU_FTR_HVMODE | CPU_FTR_DABRX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define CPU_FTRS_POWER5 (CPU_FTR_LWSYNC | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) CPU_FTR_MMCRA | CPU_FTR_SMT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_DABRX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define CPU_FTRS_POWER6 (CPU_FTR_LWSYNC | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) CPU_FTR_MMCRA | CPU_FTR_SMT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) CPU_FTR_COHERENT_ICACHE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_CFAR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) CPU_FTR_DABRX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define CPU_FTRS_POWER7 (CPU_FTR_LWSYNC | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) CPU_FTR_MMCRA | CPU_FTR_SMT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) CPU_FTR_COHERENT_ICACHE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) CPU_FTR_CFAR | CPU_FTR_HVMODE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) CPU_FTR_VMX_COPY | CPU_FTR_HAS_PPR | CPU_FTR_DABRX )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define CPU_FTRS_POWER8 (CPU_FTR_LWSYNC | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) CPU_FTR_MMCRA | CPU_FTR_SMT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) CPU_FTR_COHERENT_ICACHE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) CPU_FTR_DSCR | CPU_FTR_SAO | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_DAWR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) CPU_FTR_ARCH_207S | CPU_FTR_TM_COMP )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define CPU_FTRS_POWER8E (CPU_FTRS_POWER8 | CPU_FTR_PMAO_BUG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define CPU_FTRS_POWER9 (CPU_FTR_LWSYNC | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) CPU_FTR_MMCRA | CPU_FTR_SMT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) CPU_FTR_COHERENT_ICACHE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) CPU_FTR_DSCR | CPU_FTR_SAO | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_ARCH_207S | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) CPU_FTR_TM_COMP | CPU_FTR_ARCH_300 | CPU_FTR_P9_TLBIE_STQ_BUG | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) CPU_FTR_P9_TLBIE_ERAT_BUG | CPU_FTR_P9_TIDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define CPU_FTRS_POWER9_DD2_0 (CPU_FTRS_POWER9 | CPU_FTR_P9_RADIX_PREFETCH_BUG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define CPU_FTRS_POWER9_DD2_1 (CPU_FTRS_POWER9 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) CPU_FTR_P9_RADIX_PREFETCH_BUG | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) CPU_FTR_POWER9_DD2_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define CPU_FTRS_POWER9_DD2_2 (CPU_FTRS_POWER9 | CPU_FTR_POWER9_DD2_1 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) CPU_FTR_P9_TM_HV_ASSIST | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) CPU_FTR_P9_TM_XER_SO_BUG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define CPU_FTRS_POWER10 (CPU_FTR_LWSYNC | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) CPU_FTR_MMCRA | CPU_FTR_SMT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) CPU_FTR_COHERENT_ICACHE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) CPU_FTR_DSCR | CPU_FTR_SAO | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_ARCH_207S | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) CPU_FTR_ARCH_300 | CPU_FTR_ARCH_31 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) CPU_FTR_DAWR | CPU_FTR_DAWR1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define CPU_FTRS_CELL (CPU_FTR_LWSYNC | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) CPU_FTR_PAUSE_ZERO | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) CPU_FTR_UNALIGNED_LD_STD | CPU_FTR_DABRX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define CPU_FTRS_PA6T (CPU_FTR_LWSYNC | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_DABRX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define CPU_FTRS_COMPATIBLE (CPU_FTR_PPCAS_ARCH_V2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #ifdef __powerpc64__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #ifdef CONFIG_PPC_BOOK3E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define CPU_FTRS_POSSIBLE (CPU_FTRS_E6500 | CPU_FTRS_E5500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #ifdef CONFIG_CPU_LITTLE_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define CPU_FTRS_POSSIBLE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) (CPU_FTRS_POWER7 | CPU_FTRS_POWER8E | CPU_FTRS_POWER8 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) CPU_FTR_ALTIVEC_COMP | CPU_FTR_VSX_COMP | CPU_FTRS_POWER9 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) CPU_FTRS_POWER9_DD2_1 | CPU_FTRS_POWER9_DD2_2 | CPU_FTRS_POWER10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define CPU_FTRS_POSSIBLE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) (CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) CPU_FTRS_POWER6 | CPU_FTRS_POWER7 | CPU_FTRS_POWER8E | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) CPU_FTRS_POWER8 | CPU_FTRS_CELL | CPU_FTRS_PA6T | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) CPU_FTR_VSX_COMP | CPU_FTR_ALTIVEC_COMP | CPU_FTRS_POWER9 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) CPU_FTRS_POWER9_DD2_1 | CPU_FTRS_POWER9_DD2_2 | CPU_FTRS_POWER10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #endif /* CONFIG_CPU_LITTLE_ENDIAN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) CPU_FTRS_POSSIBLE =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #ifdef CONFIG_PPC_BOOK3S_32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) CPU_FTRS_CLASSIC32 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #ifdef CONFIG_PPC_8xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) CPU_FTRS_8XX |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #ifdef CONFIG_40x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) CPU_FTRS_40X |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #ifdef CONFIG_44x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) CPU_FTRS_44X | CPU_FTRS_440x6 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #ifdef CONFIG_PPC_47x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) CPU_FTRS_47X | CPU_FTR_476_DD2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #ifdef CONFIG_E200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) CPU_FTRS_E200 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #ifdef CONFIG_E500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) CPU_FTRS_E500 | CPU_FTRS_E500_2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #ifdef CONFIG_PPC_E500MC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) CPU_FTRS_E500MC | CPU_FTRS_E5500 | CPU_FTRS_E6500 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #endif /* __powerpc64__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #ifdef __powerpc64__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #ifdef CONFIG_PPC_BOOK3E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define CPU_FTRS_ALWAYS (CPU_FTRS_E6500 & CPU_FTRS_E5500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #ifdef CONFIG_PPC_DT_CPU_FTRS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define CPU_FTRS_DT_CPU_BASE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) (CPU_FTR_LWSYNC | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) CPU_FTR_FPU_UNAVAILABLE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) CPU_FTR_NODSISRALIGN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) CPU_FTR_NOEXECUTE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) CPU_FTR_COHERENT_ICACHE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) CPU_FTR_STCX_CHECKS_ADDRESS | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) CPU_FTR_DAWR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) CPU_FTR_ARCH_206 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) CPU_FTR_ARCH_207S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define CPU_FTRS_DT_CPU_BASE (~0ul)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #ifdef CONFIG_CPU_LITTLE_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define CPU_FTRS_ALWAYS \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) (CPU_FTRS_POSSIBLE & ~CPU_FTR_HVMODE & CPU_FTRS_POWER7 & \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) CPU_FTRS_POWER8E & CPU_FTRS_POWER8 & CPU_FTRS_POWER9 & \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) CPU_FTRS_POWER9_DD2_1 & CPU_FTRS_DT_CPU_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define CPU_FTRS_ALWAYS \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) (CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) CPU_FTRS_POWER6 & CPU_FTRS_POWER7 & CPU_FTRS_CELL & \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) CPU_FTRS_PA6T & CPU_FTRS_POWER8 & CPU_FTRS_POWER8E & \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) ~CPU_FTR_HVMODE & CPU_FTRS_POSSIBLE & CPU_FTRS_POWER9 & \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) CPU_FTRS_POWER9_DD2_1 & CPU_FTRS_DT_CPU_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #endif /* CONFIG_CPU_LITTLE_ENDIAN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) CPU_FTRS_ALWAYS =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #ifdef CONFIG_PPC_BOOK3S_32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) CPU_FTRS_CLASSIC32 &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #ifdef CONFIG_PPC_8xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) CPU_FTRS_8XX &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #ifdef CONFIG_40x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) CPU_FTRS_40X &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #ifdef CONFIG_44x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) CPU_FTRS_44X & CPU_FTRS_440x6 &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #ifdef CONFIG_E200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) CPU_FTRS_E200 &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #ifdef CONFIG_E500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) CPU_FTRS_E500 & CPU_FTRS_E500_2 &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #ifdef CONFIG_PPC_E500MC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) CPU_FTRS_E500MC & CPU_FTRS_E5500 & CPU_FTRS_E6500 &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) ~CPU_FTR_EMB_HV & /* can be removed at runtime */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) CPU_FTRS_POSSIBLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #endif /* __powerpc64__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) * Maximum number of hw breakpoint supported on powerpc. Number of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) * breakpoints supported by actual hw might be less than this, which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) * is decided at run time in nr_wp_slots().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #define HBP_NUM_MAX 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) #endif /* !__ASSEMBLY__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) #endif /* __ASM_POWERPC_CPUTABLE_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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