^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef _ASM_POWERPC_CPUIDLE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define _ASM_POWERPC_CPUIDLE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #ifdef CONFIG_PPC_POWERNV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) /* Thread state used in powernv idle state management */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define PNV_THREAD_RUNNING 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define PNV_THREAD_NAP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define PNV_THREAD_SLEEP 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define PNV_THREAD_WINKLE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Core state used in powernv idle for POWER8.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * The lock bit synchronizes updates to the state, as well as parts of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * sleep/wake code (see kernel/idle_book3s.S).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * Bottom 8 bits track the idle state of each thread. Bit is cleared before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * the thread executes an idle instruction (nap/sleep/winkle).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * Then there is winkle tracking. A core does not lose complete state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * until every thread is in winkle. So the winkle count field counts the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * number of threads in winkle (small window of false positives is okay
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * around the sleep/wake, so long as there are no false negatives).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * When the winkle count reaches 8 (the COUNT_ALL_BIT becomes set), then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * the THREAD_WINKLE_BITS are set, which indicate which threads have not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * yet woken from the winkle state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define NR_PNV_CORE_IDLE_LOCK_BIT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PNV_CORE_IDLE_LOCK_BIT (1ULL << NR_PNV_CORE_IDLE_LOCK_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PNV_CORE_IDLE_WINKLE_COUNT_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PNV_CORE_IDLE_WINKLE_COUNT 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PNV_CORE_IDLE_WINKLE_COUNT_BITS 0x000F0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PNV_CORE_IDLE_THREAD_WINKLE_BITS_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PNV_CORE_IDLE_THREAD_WINKLE_BITS 0x0000FF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PNV_CORE_IDLE_THREAD_BITS 0x000000FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * ============================ NOTE =================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * The older firmware populates only the RL field in the psscr_val and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * sets the psscr_mask to 0xf. On such a firmware, the kernel sets the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * remaining PSSCR fields to default values as follows:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * - ESL and EC bits are to 1. So wakeup from any stop state will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * at vector 0x100.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * - MTL and PSLL are set to the maximum allowed value as per the ISA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * i.e. 15.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * - The Transition Rate, TR is set to the Maximum value 3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PSSCR_HV_DEFAULT_VAL (PSSCR_ESL | PSSCR_EC | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) PSSCR_PSLL_MASK | PSSCR_TR_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) PSSCR_MTL_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PSSCR_HV_DEFAULT_MASK (PSSCR_ESL | PSSCR_EC | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) PSSCR_PSLL_MASK | PSSCR_TR_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) PSSCR_MTL_MASK | PSSCR_RL_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define PSSCR_EC_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PSSCR_ESL_SHIFT 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define GET_PSSCR_EC(x) (((x) & PSSCR_EC) >> PSSCR_EC_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define GET_PSSCR_ESL(x) (((x) & PSSCR_ESL) >> PSSCR_ESL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define GET_PSSCR_RL(x) ((x) & PSSCR_RL_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define ERR_EC_ESL_MISMATCH -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define ERR_DEEP_STATE_ESL_MISMATCH -2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define PNV_IDLE_NAME_LEN 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct pnv_idle_states_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) char name[PNV_IDLE_NAME_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u32 latency_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u32 residency_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u64 psscr_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u64 psscr_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) bool valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) extern struct pnv_idle_states_t *pnv_idle_states;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) extern int nr_pnv_idle_states;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) unsigned long pnv_cpu_offline(unsigned int cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) int validate_psscr_val_mask(u64 *psscr_val, u64 *psscr_mask, u32 flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static inline void report_invalid_psscr_val(u64 psscr_val, int err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) switch (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) case ERR_EC_ESL_MISMATCH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) pr_warn("Invalid psscr 0x%016llx : ESL,EC bits unequal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) psscr_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) case ERR_DEEP_STATE_ESL_MISMATCH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) pr_warn("Invalid psscr 0x%016llx : ESL cleared for deep stop-state",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) psscr_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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