^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Communication Processor Module v2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * This file contains structures and information for the communication
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * processor channels found in the dual port RAM or parameter RAM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * All CPM control and status is available through the CPM2 internal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * memory map. See immap_cpm2.h for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifdef __KERNEL__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef __CPM2__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define __CPM2__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/immap_cpm2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/cpm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <sysdev/fsl_soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* CPM Command register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CPM_CR_RST ((uint)0x80000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CPM_CR_PAGE ((uint)0x7c000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CPM_CR_SBLOCK ((uint)0x03e00000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CPM_CR_FLG ((uint)0x00010000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CPM_CR_MCN ((uint)0x00003fc0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CPM_CR_OPCODE ((uint)0x0000000f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* Device sub-block and page codes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CPM_CR_SCC1_SBLOCK (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CPM_CR_SCC2_SBLOCK (0x05)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CPM_CR_SCC3_SBLOCK (0x06)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CPM_CR_SCC4_SBLOCK (0x07)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CPM_CR_SMC1_SBLOCK (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CPM_CR_SMC2_SBLOCK (0x09)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CPM_CR_SPI_SBLOCK (0x0a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CPM_CR_I2C_SBLOCK (0x0b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CPM_CR_TIMER_SBLOCK (0x0f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CPM_CR_RAND_SBLOCK (0x0e)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CPM_CR_FCC1_SBLOCK (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CPM_CR_FCC2_SBLOCK (0x11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CPM_CR_FCC3_SBLOCK (0x12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CPM_CR_IDMA1_SBLOCK (0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CPM_CR_IDMA2_SBLOCK (0x15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CPM_CR_IDMA3_SBLOCK (0x16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CPM_CR_IDMA4_SBLOCK (0x17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CPM_CR_MCC1_SBLOCK (0x1c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CPM_CR_FCC_SBLOCK(x) (x + 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CPM_CR_SCC1_PAGE (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CPM_CR_SCC2_PAGE (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CPM_CR_SCC3_PAGE (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CPM_CR_SCC4_PAGE (0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CPM_CR_SMC1_PAGE (0x07)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CPM_CR_SMC2_PAGE (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CPM_CR_SPI_PAGE (0x09)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CPM_CR_I2C_PAGE (0x0a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CPM_CR_TIMER_PAGE (0x0a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CPM_CR_RAND_PAGE (0x0a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CPM_CR_FCC1_PAGE (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CPM_CR_FCC2_PAGE (0x05)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CPM_CR_FCC3_PAGE (0x06)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CPM_CR_IDMA1_PAGE (0x07)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CPM_CR_IDMA2_PAGE (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CPM_CR_IDMA3_PAGE (0x09)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CPM_CR_IDMA4_PAGE (0x0a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CPM_CR_MCC1_PAGE (0x07)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CPM_CR_MCC2_PAGE (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CPM_CR_FCC_PAGE(x) (x + 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* CPM2-specific opcodes (see cpm.h for common opcodes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define CPM_CR_START_IDMA ((ushort)0x0009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define mk_cr_cmd(PG, SBC, MCN, OP) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) ((PG << 26) | (SBC << 21) | (MCN << 6) | OP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* The number of pages of host memory we allocate for CPM. This is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * done early in kernel initialization to get physically contiguous
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * pages.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define NUM_CPM_HOST_PAGES 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* Export the base address of the communication processor registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * and dual port ram.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) extern cpm_cpm2_t __iomem *cpmp; /* Pointer to comm processor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define cpm_dpalloc cpm_muram_alloc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define cpm_dpfree cpm_muram_free
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define cpm_dpram_addr cpm_muram_addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) extern void cpm2_reset(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* Baud rate generators.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define CPM_BRG_RST ((uint)0x00020000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define CPM_BRG_EN ((uint)0x00010000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define CPM_BRG_EXTC_INT ((uint)0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define CPM_BRG_EXTC_CLK3_9 ((uint)0x00004000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define CPM_BRG_EXTC_CLK5_15 ((uint)0x00008000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define CPM_BRG_ATB ((uint)0x00002000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define CPM_BRG_CD_MASK ((uint)0x00001ffe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define CPM_BRG_DIV16 ((uint)0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define CPM2_BRG_INT_CLK (get_brgfreq())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define CPM2_BRG_UART_CLK (CPM2_BRG_INT_CLK/16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) extern void __cpm2_setbrg(uint brg, uint rate, uint clk, int div16, int src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* This function is used by UARTS, or anything else that uses a 16x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * oversampled clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static inline void cpm_setbrg(uint brg, uint rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) __cpm2_setbrg(brg, rate, CPM2_BRG_UART_CLK, 0, CPM_BRG_EXTC_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* This function is used to set high speed synchronous baud rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static inline void cpm2_fastbrg(uint brg, uint rate, int div16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) __cpm2_setbrg(brg, rate, CPM2_BRG_INT_CLK, div16, CPM_BRG_EXTC_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* Parameter RAM offsets from the base.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define PROFF_SCC1 ((uint)0x8000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define PROFF_SCC2 ((uint)0x8100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define PROFF_SCC3 ((uint)0x8200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define PROFF_SCC4 ((uint)0x8300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define PROFF_FCC1 ((uint)0x8400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define PROFF_FCC2 ((uint)0x8500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define PROFF_FCC3 ((uint)0x8600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define PROFF_MCC1 ((uint)0x8700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define PROFF_SMC1_BASE ((uint)0x87fc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define PROFF_IDMA1_BASE ((uint)0x87fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define PROFF_MCC2 ((uint)0x8800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define PROFF_SMC2_BASE ((uint)0x88fc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define PROFF_IDMA2_BASE ((uint)0x88fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define PROFF_SPI_BASE ((uint)0x89fc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define PROFF_IDMA3_BASE ((uint)0x89fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define PROFF_TIMERS ((uint)0x8ae0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define PROFF_REVNUM ((uint)0x8af0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define PROFF_RAND ((uint)0x8af8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define PROFF_I2C_BASE ((uint)0x8afc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define PROFF_IDMA4_BASE ((uint)0x8afe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define PROFF_SCC_SIZE ((uint)0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define PROFF_FCC_SIZE ((uint)0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define PROFF_SMC_SIZE ((uint)64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* The SMCs are relocated to any of the first eight DPRAM pages.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * We will fix these at the first locations of DPRAM, until we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * get some microcode patches :-).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * The parameter ram space for the SMCs is fifty-some bytes, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * they are required to start on a 64 byte boundary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define PROFF_SMC1 (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define PROFF_SMC2 (64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* Define enough so I can at least use the serial port as a UART.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) typedef struct smc_uart {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) ushort smc_rbase; /* Rx Buffer descriptor base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) ushort smc_tbase; /* Tx Buffer descriptor base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) u_char smc_rfcr; /* Rx function code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) u_char smc_tfcr; /* Tx function code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) ushort smc_mrblr; /* Max receive buffer length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) uint smc_rstate; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) uint smc_idp; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) ushort smc_rbptr; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) ushort smc_ibc; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) uint smc_rxtmp; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) uint smc_tstate; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) uint smc_tdp; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) ushort smc_tbptr; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) ushort smc_tbc; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) uint smc_txtmp; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) ushort smc_maxidl; /* Maximum idle characters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) ushort smc_tmpidl; /* Temporary idle counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) ushort smc_brklen; /* Last received break length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) ushort smc_brkec; /* rcv'd break condition counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) ushort smc_brkcr; /* xmt break count register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) ushort smc_rmask; /* Temporary bit mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) uint smc_stmp; /* SDMA Temp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) } smc_uart_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* SMC uart mode register (Internal memory map).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define SMCMR_REN ((ushort)0x0001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define SMCMR_TEN ((ushort)0x0002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define SMCMR_DM ((ushort)0x000c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define SMCMR_SM_GCI ((ushort)0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define SMCMR_SM_UART ((ushort)0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define SMCMR_SM_TRANS ((ushort)0x0030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define SMCMR_SM_MASK ((ushort)0x0030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define SMCMR_REVD SMCMR_PM_EVEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define SMCMR_PEN ((ushort)0x0200) /* Parity enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define SMCMR_BS SMCMR_PEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* SMC Event and Mask register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define SMCM_TXE ((unsigned char)0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define SMCM_BSY ((unsigned char)0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define SMCM_TX ((unsigned char)0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define SMCM_RX ((unsigned char)0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* SCCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define SCC_GSMRH_IRP ((uint)0x00040000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define SCC_GSMRH_GDE ((uint)0x00010000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define SCC_GSMRH_REVD ((uint)0x00002000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define SCC_GSMRH_TRX ((uint)0x00001000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define SCC_GSMRH_TTX ((uint)0x00000800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define SCC_GSMRH_CDP ((uint)0x00000400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define SCC_GSMRH_CTSP ((uint)0x00000200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define SCC_GSMRH_CDS ((uint)0x00000100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define SCC_GSMRH_CTSS ((uint)0x00000080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define SCC_GSMRH_TFL ((uint)0x00000040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define SCC_GSMRH_RFW ((uint)0x00000020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define SCC_GSMRH_TXSY ((uint)0x00000010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define SCC_GSMRH_SYNL16 ((uint)0x0000000c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define SCC_GSMRH_SYNL8 ((uint)0x00000008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define SCC_GSMRH_SYNL4 ((uint)0x00000004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define SCC_GSMRH_RTSM ((uint)0x00000002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define SCC_GSMRH_RSYN ((uint)0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define SCC_GSMRL_EDGE_NONE ((uint)0x60000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define SCC_GSMRL_EDGE_NEG ((uint)0x40000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define SCC_GSMRL_EDGE_POS ((uint)0x20000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define SCC_GSMRL_TCI ((uint)0x10000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define SCC_GSMRL_TSNC_3 ((uint)0x0c000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define SCC_GSMRL_TSNC_4 ((uint)0x08000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define SCC_GSMRL_TSNC_14 ((uint)0x04000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define SCC_GSMRL_TSNC_INF ((uint)0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define SCC_GSMRL_RINV ((uint)0x02000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define SCC_GSMRL_TINV ((uint)0x01000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define SCC_GSMRL_TPL_128 ((uint)0x00c00000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define SCC_GSMRL_TPL_64 ((uint)0x00a00000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define SCC_GSMRL_TPL_48 ((uint)0x00800000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define SCC_GSMRL_TPL_32 ((uint)0x00600000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define SCC_GSMRL_TPL_16 ((uint)0x00400000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define SCC_GSMRL_TPL_8 ((uint)0x00200000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define SCC_GSMRL_TPL_NONE ((uint)0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define SCC_GSMRL_TPP_01 ((uint)0x00100000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define SCC_GSMRL_TPP_10 ((uint)0x00080000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define SCC_GSMRL_TEND ((uint)0x00040000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define SCC_GSMRL_TDCR_32 ((uint)0x00030000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define SCC_GSMRL_TDCR_16 ((uint)0x00020000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define SCC_GSMRL_TDCR_8 ((uint)0x00010000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define SCC_GSMRL_TDCR_1 ((uint)0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define SCC_GSMRL_RDCR_32 ((uint)0x0000c000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define SCC_GSMRL_RDCR_16 ((uint)0x00008000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define SCC_GSMRL_RDCR_8 ((uint)0x00004000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define SCC_GSMRL_RDCR_1 ((uint)0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define SCC_GSMRL_RENC_MANCH ((uint)0x00002000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define SCC_GSMRL_RENC_FM0 ((uint)0x00001000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define SCC_GSMRL_RENC_NRZI ((uint)0x00000800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define SCC_GSMRL_RENC_NRZ ((uint)0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define SCC_GSMRL_TENC_MANCH ((uint)0x00000400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define SCC_GSMRL_TENC_FM0 ((uint)0x00000200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define SCC_GSMRL_TENC_NRZI ((uint)0x00000100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define SCC_GSMRL_TENC_NRZ ((uint)0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define SCC_GSMRL_DIAG_NORM ((uint)0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define SCC_GSMRL_ENR ((uint)0x00000020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define SCC_GSMRL_ENT ((uint)0x00000010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define SCC_GSMRL_MODE_ENET ((uint)0x0000000c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define SCC_GSMRL_MODE_V14 ((uint)0x00000007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define SCC_GSMRL_MODE_UART ((uint)0x00000004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define SCC_GSMRL_MODE_SS7 ((uint)0x00000003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define SCC_GSMRL_MODE_ATALK ((uint)0x00000002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define SCC_GSMRL_MODE_HDLC ((uint)0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define SCC_TODR_TOD ((ushort)0x8000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /* SCC Event and Mask register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define SCCM_TXE ((unsigned char)0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define SCCM_BSY ((unsigned char)0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define SCCM_TX ((unsigned char)0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define SCCM_RX ((unsigned char)0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) typedef struct scc_param {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) ushort scc_rbase; /* Rx Buffer descriptor base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) ushort scc_tbase; /* Tx Buffer descriptor base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) u_char scc_rfcr; /* Rx function code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) u_char scc_tfcr; /* Tx function code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) ushort scc_mrblr; /* Max receive buffer length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) uint scc_rstate; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) uint scc_idp; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) ushort scc_rbptr; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) ushort scc_ibc; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) uint scc_rxtmp; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) uint scc_tstate; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) uint scc_tdp; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) ushort scc_tbptr; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) ushort scc_tbc; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) uint scc_txtmp; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) uint scc_rcrc; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) uint scc_tcrc; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) } sccp_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* Function code bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define SCC_EB ((u_char) 0x10) /* Set big endian byte order */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define SCC_GBL ((u_char) 0x20) /* Snooping enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* CPM Ethernet through SCC1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) typedef struct scc_enet {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) sccp_t sen_genscc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) uint sen_cpres; /* Preset CRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) uint sen_cmask; /* Constant mask for CRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) uint sen_crcec; /* CRC Error counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) uint sen_alec; /* alignment error counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) uint sen_disfc; /* discard frame counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) ushort sen_pads; /* Tx short frame pad character */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) ushort sen_retlim; /* Retry limit threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) ushort sen_retcnt; /* Retry limit counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) ushort sen_maxflr; /* maximum frame length register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) ushort sen_minflr; /* minimum frame length register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) ushort sen_maxd1; /* maximum DMA1 length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) ushort sen_maxd2; /* maximum DMA2 length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) ushort sen_maxd; /* Rx max DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) ushort sen_dmacnt; /* Rx DMA counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) ushort sen_maxb; /* Max BD byte count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) ushort sen_gaddr1; /* Group address filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) ushort sen_gaddr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) ushort sen_gaddr3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) ushort sen_gaddr4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) uint sen_tbuf0data0; /* Save area 0 - current frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) uint sen_tbuf0data1; /* Save area 1 - current frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) uint sen_tbuf0rba; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) uint sen_tbuf0crc; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) ushort sen_tbuf0bcnt; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) ushort sen_paddrh; /* physical address (MSB) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) ushort sen_paddrm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) ushort sen_paddrl; /* physical address (LSB) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) ushort sen_pper; /* persistence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) ushort sen_rfbdptr; /* Rx first BD pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) ushort sen_tfbdptr; /* Tx first BD pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) ushort sen_tlbdptr; /* Tx last BD pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) uint sen_tbuf1data0; /* Save area 0 - current frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) uint sen_tbuf1data1; /* Save area 1 - current frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) uint sen_tbuf1rba; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) uint sen_tbuf1crc; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) ushort sen_tbuf1bcnt; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) ushort sen_txlen; /* Tx Frame length counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) ushort sen_iaddr1; /* Individual address filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) ushort sen_iaddr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) ushort sen_iaddr3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) ushort sen_iaddr4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) ushort sen_boffcnt; /* Backoff counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /* NOTE: Some versions of the manual have the following items
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) * incorrectly documented. Below is the proper order.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) ushort sen_taddrh; /* temp address (MSB) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) ushort sen_taddrm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) ushort sen_taddrl; /* temp address (LSB) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) } scc_enet_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /* SCC Event register as used by Ethernet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) /* SCC Mode Register (PSMR) as used by Ethernet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /* SCC as UART
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) typedef struct scc_uart {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) sccp_t scc_genscc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) uint scc_res1; /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) uint scc_res2; /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) ushort scc_maxidl; /* Maximum idle chars */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) ushort scc_idlc; /* temp idle counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) ushort scc_brkcr; /* Break count register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) ushort scc_parec; /* receive parity error counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) ushort scc_frmec; /* receive framing error counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) ushort scc_nosec; /* receive noise counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) ushort scc_brkec; /* receive break condition counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) ushort scc_brkln; /* last received break length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) ushort scc_uaddr1; /* UART address character 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) ushort scc_uaddr2; /* UART address character 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) ushort scc_rtemp; /* Temp storage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) ushort scc_toseq; /* Transmit out of sequence char */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) ushort scc_char1; /* control character 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) ushort scc_char2; /* control character 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) ushort scc_char3; /* control character 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) ushort scc_char4; /* control character 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) ushort scc_char5; /* control character 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) ushort scc_char6; /* control character 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) ushort scc_char7; /* control character 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) ushort scc_char8; /* control character 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) ushort scc_rccm; /* receive control character mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) ushort scc_rccr; /* receive control character register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) ushort scc_rlbc; /* receive last break character */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) } scc_uart_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /* SCC Event and Mask registers when it is used as a UART.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define UART_SCCM_GLR ((ushort)0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define UART_SCCM_GLT ((ushort)0x0800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define UART_SCCM_AB ((ushort)0x0200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define UART_SCCM_IDL ((ushort)0x0100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define UART_SCCM_GRA ((ushort)0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define UART_SCCM_BRKE ((ushort)0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define UART_SCCM_BRKS ((ushort)0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define UART_SCCM_CCR ((ushort)0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define UART_SCCM_BSY ((ushort)0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define UART_SCCM_TX ((ushort)0x0002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define UART_SCCM_RX ((ushort)0x0001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /* The SCC PSMR when used as a UART.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define SCU_PSMR_FLC ((ushort)0x8000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define SCU_PSMR_SL ((ushort)0x4000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define SCU_PSMR_CL ((ushort)0x3000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define SCU_PSMR_UM ((ushort)0x0c00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define SCU_PSMR_FRZ ((ushort)0x0200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define SCU_PSMR_RZS ((ushort)0x0100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define SCU_PSMR_SYN ((ushort)0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define SCU_PSMR_DRT ((ushort)0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define SCU_PSMR_PEN ((ushort)0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define SCU_PSMR_RPM ((ushort)0x000c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define SCU_PSMR_REVP ((ushort)0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define SCU_PSMR_TPM ((ushort)0x0003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define SCU_PSMR_TEVP ((ushort)0x0002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) /* CPM Transparent mode SCC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) typedef struct scc_trans {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) sccp_t st_genscc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) uint st_cpres; /* Preset CRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) uint st_cmask; /* Constant mask for CRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) } scc_trans_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) /* How about some FCCs.....
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define FCC_GFMR_DIAG_NORM ((uint)0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define FCC_GFMR_DIAG_LE ((uint)0x40000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define FCC_GFMR_DIAG_AE ((uint)0x80000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define FCC_GFMR_DIAG_ALE ((uint)0xc0000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define FCC_GFMR_TCI ((uint)0x20000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define FCC_GFMR_TRX ((uint)0x10000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define FCC_GFMR_TTX ((uint)0x08000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define FCC_GFMR_CDP ((uint)0x04000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define FCC_GFMR_CTSP ((uint)0x02000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define FCC_GFMR_CDS ((uint)0x01000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define FCC_GFMR_CTSS ((uint)0x00800000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define FCC_GFMR_SYNL_NONE ((uint)0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define FCC_GFMR_SYNL_AUTO ((uint)0x00004000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define FCC_GFMR_SYNL_8 ((uint)0x00008000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define FCC_GFMR_SYNL_16 ((uint)0x0000c000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define FCC_GFMR_RTSM ((uint)0x00002000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define FCC_GFMR_RENC_NRZ ((uint)0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define FCC_GFMR_RENC_NRZI ((uint)0x00000800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define FCC_GFMR_REVD ((uint)0x00000400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define FCC_GFMR_TENC_NRZ ((uint)0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define FCC_GFMR_TENC_NRZI ((uint)0x00000100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define FCC_GFMR_TCRC_16 ((uint)0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define FCC_GFMR_TCRC_32 ((uint)0x00000080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define FCC_GFMR_ENR ((uint)0x00000020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define FCC_GFMR_ENT ((uint)0x00000010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define FCC_GFMR_MODE_ENET ((uint)0x0000000c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define FCC_GFMR_MODE_ATM ((uint)0x0000000a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define FCC_GFMR_MODE_HDLC ((uint)0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) /* Generic FCC parameter ram.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) typedef struct fcc_param {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) ushort fcc_riptr; /* Rx Internal temp pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) ushort fcc_tiptr; /* Tx Internal temp pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) ushort fcc_res1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) ushort fcc_mrblr; /* Max receive buffer length, mod 32 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) uint fcc_rstate; /* Upper byte is Func code, must be set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) uint fcc_rbase; /* Receive BD base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) ushort fcc_rbdstat; /* RxBD status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) ushort fcc_rbdlen; /* RxBD down counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) uint fcc_rdptr; /* RxBD internal data pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) uint fcc_tstate; /* Upper byte is Func code, must be set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) uint fcc_tbase; /* Transmit BD base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) ushort fcc_tbdstat; /* TxBD status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) ushort fcc_tbdlen; /* TxBD down counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) uint fcc_tdptr; /* TxBD internal data pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) uint fcc_rbptr; /* Rx BD Internal buf pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) uint fcc_tbptr; /* Tx BD Internal buf pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) uint fcc_rcrc; /* Rx temp CRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) uint fcc_res2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) uint fcc_tcrc; /* Tx temp CRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) } fccp_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) /* Ethernet controller through FCC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) typedef struct fcc_enet {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) fccp_t fen_genfcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) uint fen_statbuf; /* Internal status buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) uint fen_camptr; /* CAM address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) uint fen_cmask; /* Constant mask for CRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) uint fen_cpres; /* Preset CRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) uint fen_crcec; /* CRC Error counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) uint fen_alec; /* alignment error counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) uint fen_disfc; /* discard frame counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) ushort fen_retlim; /* Retry limit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) ushort fen_retcnt; /* Retry counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) ushort fen_pper; /* Persistence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) ushort fen_boffcnt; /* backoff counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) uint fen_gaddrh; /* Group address filter, high 32-bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) uint fen_gaddrl; /* Group address filter, low 32-bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) ushort fen_tfcstat; /* out of sequence TxBD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) ushort fen_tfclen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) uint fen_tfcptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) ushort fen_mflr; /* Maximum frame length (1518) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) ushort fen_paddrh; /* MAC address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) ushort fen_paddrm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) ushort fen_paddrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) ushort fen_ibdcount; /* Internal BD counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) ushort fen_ibdstart; /* Internal BD start pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) ushort fen_ibdend; /* Internal BD end pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) ushort fen_txlen; /* Internal Tx frame length counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) uint fen_ibdbase[8]; /* Internal use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) uint fen_iaddrh; /* Individual address filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) uint fen_iaddrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) ushort fen_minflr; /* Minimum frame length (64) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) ushort fen_taddrh; /* Filter transfer MAC address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) ushort fen_taddrm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) ushort fen_taddrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) ushort fen_padptr; /* Pointer to pad byte buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) ushort fen_cftype; /* control frame type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) ushort fen_cfrange; /* control frame range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) ushort fen_maxb; /* maximum BD count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) ushort fen_maxd1; /* Max DMA1 length (1520) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) ushort fen_maxd2; /* Max DMA2 length (1520) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) ushort fen_maxd; /* internal max DMA count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) ushort fen_dmacnt; /* internal DMA counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) uint fen_octc; /* Total octect counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) uint fen_colc; /* Total collision counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) uint fen_broc; /* Total broadcast packet counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) uint fen_mulc; /* Total multicast packet count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) uint fen_uspc; /* Total packets < 64 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) uint fen_frgc; /* Total packets < 64 bytes with errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) uint fen_ospc; /* Total packets > 1518 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) uint fen_jbrc; /* Total packets > 1518 with errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) uint fen_p64c; /* Total packets == 64 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) uint fen_p65c; /* Total packets 64 < bytes <= 127 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) uint fen_p128c; /* Total packets 127 < bytes <= 255 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) uint fen_p256c; /* Total packets 256 < bytes <= 511 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) uint fen_p512c; /* Total packets 512 < bytes <= 1023 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) uint fen_p1024c; /* Total packets 1024 < bytes <= 1518 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) uint fen_cambuf; /* Internal CAM buffer poiner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) ushort fen_rfthr; /* Received frames threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) ushort fen_rfcnt; /* Received frames count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) } fcc_enet_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) /* FCC Event/Mask register as used by Ethernet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #define FCC_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #define FCC_ENET_RXC ((ushort)0x0040) /* Control Frame Received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #define FCC_ENET_TXC ((ushort)0x0020) /* Out of seq. Tx sent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #define FCC_ENET_TXE ((ushort)0x0010) /* Transmit Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #define FCC_ENET_RXF ((ushort)0x0008) /* Full frame received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #define FCC_ENET_BSY ((ushort)0x0004) /* Busy. Rx Frame dropped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #define FCC_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #define FCC_ENET_RXB ((ushort)0x0001) /* A buffer was received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) /* FCC Mode Register (FPSMR) as used by Ethernet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #define FCC_PSMR_HBC ((uint)0x80000000) /* Enable heartbeat */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define FCC_PSMR_FC ((uint)0x40000000) /* Force Collision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define FCC_PSMR_SBT ((uint)0x20000000) /* Stop backoff timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define FCC_PSMR_LPB ((uint)0x10000000) /* Local protect. 1 = FDX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #define FCC_PSMR_LCW ((uint)0x08000000) /* Late collision select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #define FCC_PSMR_FDE ((uint)0x04000000) /* Full Duplex Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) #define FCC_PSMR_MON ((uint)0x02000000) /* RMON Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #define FCC_PSMR_PRO ((uint)0x00400000) /* Promiscuous Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) #define FCC_PSMR_FCE ((uint)0x00200000) /* Flow Control Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) #define FCC_PSMR_RSH ((uint)0x00100000) /* Receive Short Frames */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #define FCC_PSMR_CAM ((uint)0x00000400) /* CAM enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #define FCC_PSMR_BRO ((uint)0x00000200) /* Broadcast pkt discard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) #define FCC_PSMR_ENCRC ((uint)0x00000080) /* Use 32-bit CRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) /* IIC parameter RAM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) typedef struct iic {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) ushort iic_rbase; /* Rx Buffer descriptor base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) ushort iic_tbase; /* Tx Buffer descriptor base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) u_char iic_rfcr; /* Rx function code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) u_char iic_tfcr; /* Tx function code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) ushort iic_mrblr; /* Max receive buffer length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) uint iic_rstate; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) uint iic_rdp; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) ushort iic_rbptr; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) ushort iic_rbc; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) uint iic_rxtmp; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) uint iic_tstate; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) uint iic_tdp; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) ushort iic_tbptr; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) ushort iic_tbc; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) uint iic_txtmp; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) } iic_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) /* IDMA parameter RAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) typedef struct idma {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) ushort ibase; /* IDMA buffer descriptor table base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) ushort dcm; /* DMA channel mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) ushort ibdptr; /* IDMA current buffer descriptor pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) ushort dpr_buf; /* IDMA transfer buffer base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) ushort buf_inv; /* internal buffer inventory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) ushort ss_max; /* steady-state maximum transfer size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) ushort dpr_in_ptr; /* write pointer inside the internal buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) ushort sts; /* source transfer size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) ushort dpr_out_ptr; /* read pointer inside the internal buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) ushort seob; /* source end of burst */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) ushort deob; /* destination end of burst */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) ushort dts; /* destination transfer size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) ushort ret_add; /* return address when working in ERM=1 mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) ushort res0; /* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) uint bd_cnt; /* internal byte count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) uint s_ptr; /* source internal data pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) uint d_ptr; /* destination internal data pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) uint istate; /* internal state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) u_char res1[20]; /* pad to 64-byte length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) } idma_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) /* DMA channel mode bit fields
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) #define IDMA_DCM_FB ((ushort)0x8000) /* fly-by mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) #define IDMA_DCM_LP ((ushort)0x4000) /* low priority */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) #define IDMA_DCM_TC2 ((ushort)0x0400) /* value driven on TC[2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) #define IDMA_DCM_DMA_WRAP_MASK ((ushort)0x01c0) /* mask for DMA wrap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) #define IDMA_DCM_DMA_WRAP_64 ((ushort)0x0000) /* 64-byte DMA xfer buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) #define IDMA_DCM_DMA_WRAP_128 ((ushort)0x0040) /* 128-byte DMA xfer buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) #define IDMA_DCM_DMA_WRAP_256 ((ushort)0x0080) /* 256-byte DMA xfer buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) #define IDMA_DCM_DMA_WRAP_512 ((ushort)0x00c0) /* 512-byte DMA xfer buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) #define IDMA_DCM_DMA_WRAP_1024 ((ushort)0x0100) /* 1024-byte DMA xfer buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) #define IDMA_DCM_DMA_WRAP_2048 ((ushort)0x0140) /* 2048-byte DMA xfer buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) #define IDMA_DCM_SINC ((ushort)0x0020) /* source inc addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) #define IDMA_DCM_DINC ((ushort)0x0010) /* destination inc addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) #define IDMA_DCM_ERM ((ushort)0x0008) /* external request mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) #define IDMA_DCM_DT ((ushort)0x0004) /* DONE treatment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) #define IDMA_DCM_SD_MASK ((ushort)0x0003) /* mask for SD bit field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) #define IDMA_DCM_SD_MEM2MEM ((ushort)0x0000) /* memory-to-memory xfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) #define IDMA_DCM_SD_PER2MEM ((ushort)0x0002) /* peripheral-to-memory xfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) #define IDMA_DCM_SD_MEM2PER ((ushort)0x0001) /* memory-to-peripheral xfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) /* IDMA Buffer Descriptors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) typedef struct idma_bd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) uint flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) uint len; /* data length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) uint src; /* source data buffer pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) uint dst; /* destination data buffer pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) } idma_bd_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) /* IDMA buffer descriptor flag bit fields
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) #define IDMA_BD_V ((uint)0x80000000) /* valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) #define IDMA_BD_W ((uint)0x20000000) /* wrap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) #define IDMA_BD_I ((uint)0x10000000) /* interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) #define IDMA_BD_L ((uint)0x08000000) /* last */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) #define IDMA_BD_CM ((uint)0x02000000) /* continuous mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) #define IDMA_BD_SDN ((uint)0x00400000) /* source done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) #define IDMA_BD_DDN ((uint)0x00200000) /* destination done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) #define IDMA_BD_DGBL ((uint)0x00100000) /* destination global */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) #define IDMA_BD_DBO_LE ((uint)0x00040000) /* little-end dest byte order */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) #define IDMA_BD_DBO_BE ((uint)0x00080000) /* big-end dest byte order */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) #define IDMA_BD_DDTB ((uint)0x00010000) /* destination data bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) #define IDMA_BD_SGBL ((uint)0x00002000) /* source global */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) #define IDMA_BD_SBO_LE ((uint)0x00000800) /* little-end src byte order */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) #define IDMA_BD_SBO_BE ((uint)0x00001000) /* big-end src byte order */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) #define IDMA_BD_SDTB ((uint)0x00000200) /* source data bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) /* per-channel IDMA registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) typedef struct im_idma {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) u_char idsr; /* IDMAn event status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) u_char res0[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) u_char idmr; /* IDMAn event mask register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) u_char res1[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) } im_idma_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) /* IDMA event register bit fields
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) #define IDMA_EVENT_SC ((unsigned char)0x08) /* stop completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) #define IDMA_EVENT_OB ((unsigned char)0x04) /* out of buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) #define IDMA_EVENT_EDN ((unsigned char)0x02) /* external DONE asserted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) #define IDMA_EVENT_BC ((unsigned char)0x01) /* buffer descriptor complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) /* RISC Controller Configuration Register (RCCR) bit fields
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) #define RCCR_TIME ((uint)0x80000000) /* timer enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) #define RCCR_TIMEP_MASK ((uint)0x3f000000) /* mask for timer period bit field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) #define RCCR_DR0M ((uint)0x00800000) /* IDMA0 request mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) #define RCCR_DR1M ((uint)0x00400000) /* IDMA1 request mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) #define RCCR_DR2M ((uint)0x00000080) /* IDMA2 request mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) #define RCCR_DR3M ((uint)0x00000040) /* IDMA3 request mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) #define RCCR_DR0QP_MASK ((uint)0x00300000) /* mask for IDMA0 req priority */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) #define RCCR_DR0QP_HIGH ((uint)0x00000000) /* IDMA0 has high req priority */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) #define RCCR_DR0QP_MED ((uint)0x00100000) /* IDMA0 has medium req priority */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) #define RCCR_DR0QP_LOW ((uint)0x00200000) /* IDMA0 has low req priority */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) #define RCCR_DR1QP_MASK ((uint)0x00030000) /* mask for IDMA1 req priority */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) #define RCCR_DR1QP_HIGH ((uint)0x00000000) /* IDMA1 has high req priority */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) #define RCCR_DR1QP_MED ((uint)0x00010000) /* IDMA1 has medium req priority */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) #define RCCR_DR1QP_LOW ((uint)0x00020000) /* IDMA1 has low req priority */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) #define RCCR_DR2QP_MASK ((uint)0x00000030) /* mask for IDMA2 req priority */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) #define RCCR_DR2QP_HIGH ((uint)0x00000000) /* IDMA2 has high req priority */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) #define RCCR_DR2QP_MED ((uint)0x00000010) /* IDMA2 has medium req priority */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) #define RCCR_DR2QP_LOW ((uint)0x00000020) /* IDMA2 has low req priority */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) #define RCCR_DR3QP_MASK ((uint)0x00000003) /* mask for IDMA3 req priority */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) #define RCCR_DR3QP_HIGH ((uint)0x00000000) /* IDMA3 has high req priority */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) #define RCCR_DR3QP_MED ((uint)0x00000001) /* IDMA3 has medium req priority */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) #define RCCR_DR3QP_LOW ((uint)0x00000002) /* IDMA3 has low req priority */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) #define RCCR_EIE ((uint)0x00080000) /* external interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) #define RCCR_SCD ((uint)0x00040000) /* scheduler configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) #define RCCR_ERAM_MASK ((uint)0x0000e000) /* mask for enable RAM microcode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) #define RCCR_ERAM_0KB ((uint)0x00000000) /* use 0KB of dpram for microcode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) #define RCCR_ERAM_2KB ((uint)0x00002000) /* use 2KB of dpram for microcode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) #define RCCR_ERAM_4KB ((uint)0x00004000) /* use 4KB of dpram for microcode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) #define RCCR_ERAM_6KB ((uint)0x00006000) /* use 6KB of dpram for microcode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) #define RCCR_ERAM_8KB ((uint)0x00008000) /* use 8KB of dpram for microcode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) #define RCCR_ERAM_10KB ((uint)0x0000a000) /* use 10KB of dpram for microcode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) #define RCCR_ERAM_12KB ((uint)0x0000c000) /* use 12KB of dpram for microcode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) #define RCCR_EDM0 ((uint)0x00000800) /* DREQ0 edge detect mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) #define RCCR_EDM1 ((uint)0x00000400) /* DREQ1 edge detect mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) #define RCCR_EDM2 ((uint)0x00000200) /* DREQ2 edge detect mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) #define RCCR_EDM3 ((uint)0x00000100) /* DREQ3 edge detect mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) #define RCCR_DEM01 ((uint)0x00000008) /* DONE0/DONE1 edge detect mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) #define RCCR_DEM23 ((uint)0x00000004) /* DONE2/DONE3 edge detect mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) /*-----------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) * CMXFCR - CMX FCC Clock Route Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) #define CMXFCR_FC1 0x40000000 /* FCC1 connection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) #define CMXFCR_RF1CS_MSK 0x38000000 /* Receive FCC1 Clock Source Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) #define CMXFCR_TF1CS_MSK 0x07000000 /* Transmit FCC1 Clock Source Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) #define CMXFCR_FC2 0x00400000 /* FCC2 connection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) #define CMXFCR_RF2CS_MSK 0x00380000 /* Receive FCC2 Clock Source Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) #define CMXFCR_TF2CS_MSK 0x00070000 /* Transmit FCC2 Clock Source Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) #define CMXFCR_FC3 0x00004000 /* FCC3 connection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) #define CMXFCR_RF3CS_MSK 0x00003800 /* Receive FCC3 Clock Source Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) #define CMXFCR_TF3CS_MSK 0x00000700 /* Transmit FCC3 Clock Source Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) #define CMXFCR_RF1CS_BRG5 0x00000000 /* Receive FCC1 Clock Source is BRG5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) #define CMXFCR_RF1CS_BRG6 0x08000000 /* Receive FCC1 Clock Source is BRG6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) #define CMXFCR_RF1CS_BRG7 0x10000000 /* Receive FCC1 Clock Source is BRG7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) #define CMXFCR_RF1CS_BRG8 0x18000000 /* Receive FCC1 Clock Source is BRG8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) #define CMXFCR_RF1CS_CLK9 0x20000000 /* Receive FCC1 Clock Source is CLK9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) #define CMXFCR_RF1CS_CLK10 0x28000000 /* Receive FCC1 Clock Source is CLK10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) #define CMXFCR_RF1CS_CLK11 0x30000000 /* Receive FCC1 Clock Source is CLK11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) #define CMXFCR_RF1CS_CLK12 0x38000000 /* Receive FCC1 Clock Source is CLK12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) #define CMXFCR_TF1CS_BRG5 0x00000000 /* Transmit FCC1 Clock Source is BRG5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) #define CMXFCR_TF1CS_BRG6 0x01000000 /* Transmit FCC1 Clock Source is BRG6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) #define CMXFCR_TF1CS_BRG7 0x02000000 /* Transmit FCC1 Clock Source is BRG7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) #define CMXFCR_TF1CS_BRG8 0x03000000 /* Transmit FCC1 Clock Source is BRG8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) #define CMXFCR_TF1CS_CLK9 0x04000000 /* Transmit FCC1 Clock Source is CLK9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) #define CMXFCR_TF1CS_CLK10 0x05000000 /* Transmit FCC1 Clock Source is CLK10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) #define CMXFCR_TF1CS_CLK11 0x06000000 /* Transmit FCC1 Clock Source is CLK11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) #define CMXFCR_TF1CS_CLK12 0x07000000 /* Transmit FCC1 Clock Source is CLK12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) #define CMXFCR_RF2CS_BRG5 0x00000000 /* Receive FCC2 Clock Source is BRG5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) #define CMXFCR_RF2CS_BRG6 0x00080000 /* Receive FCC2 Clock Source is BRG6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) #define CMXFCR_RF2CS_BRG7 0x00100000 /* Receive FCC2 Clock Source is BRG7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) #define CMXFCR_RF2CS_BRG8 0x00180000 /* Receive FCC2 Clock Source is BRG8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) #define CMXFCR_RF2CS_CLK13 0x00200000 /* Receive FCC2 Clock Source is CLK13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) #define CMXFCR_RF2CS_CLK14 0x00280000 /* Receive FCC2 Clock Source is CLK14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) #define CMXFCR_RF2CS_CLK15 0x00300000 /* Receive FCC2 Clock Source is CLK15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) #define CMXFCR_RF2CS_CLK16 0x00380000 /* Receive FCC2 Clock Source is CLK16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) #define CMXFCR_TF2CS_BRG5 0x00000000 /* Transmit FCC2 Clock Source is BRG5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) #define CMXFCR_TF2CS_BRG6 0x00010000 /* Transmit FCC2 Clock Source is BRG6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) #define CMXFCR_TF2CS_BRG7 0x00020000 /* Transmit FCC2 Clock Source is BRG7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) #define CMXFCR_TF2CS_BRG8 0x00030000 /* Transmit FCC2 Clock Source is BRG8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) #define CMXFCR_TF2CS_CLK13 0x00040000 /* Transmit FCC2 Clock Source is CLK13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) #define CMXFCR_TF2CS_CLK14 0x00050000 /* Transmit FCC2 Clock Source is CLK14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) #define CMXFCR_TF2CS_CLK15 0x00060000 /* Transmit FCC2 Clock Source is CLK15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) #define CMXFCR_TF2CS_CLK16 0x00070000 /* Transmit FCC2 Clock Source is CLK16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) #define CMXFCR_RF3CS_BRG5 0x00000000 /* Receive FCC3 Clock Source is BRG5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) #define CMXFCR_RF3CS_BRG6 0x00000800 /* Receive FCC3 Clock Source is BRG6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) #define CMXFCR_RF3CS_BRG7 0x00001000 /* Receive FCC3 Clock Source is BRG7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) #define CMXFCR_RF3CS_BRG8 0x00001800 /* Receive FCC3 Clock Source is BRG8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) #define CMXFCR_RF3CS_CLK13 0x00002000 /* Receive FCC3 Clock Source is CLK13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) #define CMXFCR_RF3CS_CLK14 0x00002800 /* Receive FCC3 Clock Source is CLK14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) #define CMXFCR_RF3CS_CLK15 0x00003000 /* Receive FCC3 Clock Source is CLK15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) #define CMXFCR_RF3CS_CLK16 0x00003800 /* Receive FCC3 Clock Source is CLK16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) #define CMXFCR_TF3CS_BRG5 0x00000000 /* Transmit FCC3 Clock Source is BRG5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) #define CMXFCR_TF3CS_BRG6 0x00000100 /* Transmit FCC3 Clock Source is BRG6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) #define CMXFCR_TF3CS_BRG7 0x00000200 /* Transmit FCC3 Clock Source is BRG7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) #define CMXFCR_TF3CS_BRG8 0x00000300 /* Transmit FCC3 Clock Source is BRG8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) #define CMXFCR_TF3CS_CLK13 0x00000400 /* Transmit FCC3 Clock Source is CLK13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) #define CMXFCR_TF3CS_CLK14 0x00000500 /* Transmit FCC3 Clock Source is CLK14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) #define CMXFCR_TF3CS_CLK15 0x00000600 /* Transmit FCC3 Clock Source is CLK15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) #define CMXFCR_TF3CS_CLK16 0x00000700 /* Transmit FCC3 Clock Source is CLK16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) /*-----------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) * CMXSCR - CMX SCC Clock Route Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) #define CMXSCR_GR1 0x80000000 /* Grant Support of SCC1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) #define CMXSCR_SC1 0x40000000 /* SCC1 connection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) #define CMXSCR_RS1CS_MSK 0x38000000 /* Receive SCC1 Clock Source Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) #define CMXSCR_TS1CS_MSK 0x07000000 /* Transmit SCC1 Clock Source Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) #define CMXSCR_GR2 0x00800000 /* Grant Support of SCC2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) #define CMXSCR_SC2 0x00400000 /* SCC2 connection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) #define CMXSCR_RS2CS_MSK 0x00380000 /* Receive SCC2 Clock Source Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) #define CMXSCR_TS2CS_MSK 0x00070000 /* Transmit SCC2 Clock Source Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) #define CMXSCR_GR3 0x00008000 /* Grant Support of SCC3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) #define CMXSCR_SC3 0x00004000 /* SCC3 connection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) #define CMXSCR_RS3CS_MSK 0x00003800 /* Receive SCC3 Clock Source Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) #define CMXSCR_TS3CS_MSK 0x00000700 /* Transmit SCC3 Clock Source Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) #define CMXSCR_GR4 0x00000080 /* Grant Support of SCC4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) #define CMXSCR_SC4 0x00000040 /* SCC4 connection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) #define CMXSCR_RS4CS_MSK 0x00000038 /* Receive SCC4 Clock Source Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) #define CMXSCR_TS4CS_MSK 0x00000007 /* Transmit SCC4 Clock Source Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) #define CMXSCR_RS1CS_BRG1 0x00000000 /* SCC1 Rx Clock Source is BRG1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) #define CMXSCR_RS1CS_BRG2 0x08000000 /* SCC1 Rx Clock Source is BRG2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) #define CMXSCR_RS1CS_BRG3 0x10000000 /* SCC1 Rx Clock Source is BRG3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) #define CMXSCR_RS1CS_BRG4 0x18000000 /* SCC1 Rx Clock Source is BRG4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) #define CMXSCR_RS1CS_CLK11 0x20000000 /* SCC1 Rx Clock Source is CLK11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) #define CMXSCR_RS1CS_CLK12 0x28000000 /* SCC1 Rx Clock Source is CLK12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) #define CMXSCR_RS1CS_CLK3 0x30000000 /* SCC1 Rx Clock Source is CLK3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) #define CMXSCR_RS1CS_CLK4 0x38000000 /* SCC1 Rx Clock Source is CLK4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) #define CMXSCR_TS1CS_BRG1 0x00000000 /* SCC1 Tx Clock Source is BRG1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) #define CMXSCR_TS1CS_BRG2 0x01000000 /* SCC1 Tx Clock Source is BRG2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) #define CMXSCR_TS1CS_BRG3 0x02000000 /* SCC1 Tx Clock Source is BRG3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) #define CMXSCR_TS1CS_BRG4 0x03000000 /* SCC1 Tx Clock Source is BRG4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) #define CMXSCR_TS1CS_CLK11 0x04000000 /* SCC1 Tx Clock Source is CLK11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) #define CMXSCR_TS1CS_CLK12 0x05000000 /* SCC1 Tx Clock Source is CLK12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) #define CMXSCR_TS1CS_CLK3 0x06000000 /* SCC1 Tx Clock Source is CLK3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) #define CMXSCR_TS1CS_CLK4 0x07000000 /* SCC1 Tx Clock Source is CLK4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) #define CMXSCR_RS2CS_BRG1 0x00000000 /* SCC2 Rx Clock Source is BRG1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) #define CMXSCR_RS2CS_BRG2 0x00080000 /* SCC2 Rx Clock Source is BRG2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) #define CMXSCR_RS2CS_BRG3 0x00100000 /* SCC2 Rx Clock Source is BRG3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) #define CMXSCR_RS2CS_BRG4 0x00180000 /* SCC2 Rx Clock Source is BRG4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) #define CMXSCR_RS2CS_CLK11 0x00200000 /* SCC2 Rx Clock Source is CLK11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) #define CMXSCR_RS2CS_CLK12 0x00280000 /* SCC2 Rx Clock Source is CLK12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) #define CMXSCR_RS2CS_CLK3 0x00300000 /* SCC2 Rx Clock Source is CLK3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) #define CMXSCR_RS2CS_CLK4 0x00380000 /* SCC2 Rx Clock Source is CLK4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) #define CMXSCR_TS2CS_BRG1 0x00000000 /* SCC2 Tx Clock Source is BRG1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) #define CMXSCR_TS2CS_BRG2 0x00010000 /* SCC2 Tx Clock Source is BRG2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) #define CMXSCR_TS2CS_BRG3 0x00020000 /* SCC2 Tx Clock Source is BRG3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) #define CMXSCR_TS2CS_BRG4 0x00030000 /* SCC2 Tx Clock Source is BRG4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) #define CMXSCR_TS2CS_CLK11 0x00040000 /* SCC2 Tx Clock Source is CLK11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) #define CMXSCR_TS2CS_CLK12 0x00050000 /* SCC2 Tx Clock Source is CLK12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) #define CMXSCR_TS2CS_CLK3 0x00060000 /* SCC2 Tx Clock Source is CLK3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) #define CMXSCR_TS2CS_CLK4 0x00070000 /* SCC2 Tx Clock Source is CLK4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) #define CMXSCR_RS3CS_BRG1 0x00000000 /* SCC3 Rx Clock Source is BRG1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) #define CMXSCR_RS3CS_BRG2 0x00000800 /* SCC3 Rx Clock Source is BRG2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) #define CMXSCR_RS3CS_BRG3 0x00001000 /* SCC3 Rx Clock Source is BRG3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) #define CMXSCR_RS3CS_BRG4 0x00001800 /* SCC3 Rx Clock Source is BRG4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) #define CMXSCR_RS3CS_CLK5 0x00002000 /* SCC3 Rx Clock Source is CLK5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) #define CMXSCR_RS3CS_CLK6 0x00002800 /* SCC3 Rx Clock Source is CLK6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) #define CMXSCR_RS3CS_CLK7 0x00003000 /* SCC3 Rx Clock Source is CLK7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) #define CMXSCR_RS3CS_CLK8 0x00003800 /* SCC3 Rx Clock Source is CLK8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) #define CMXSCR_TS3CS_BRG1 0x00000000 /* SCC3 Tx Clock Source is BRG1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) #define CMXSCR_TS3CS_BRG2 0x00000100 /* SCC3 Tx Clock Source is BRG2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) #define CMXSCR_TS3CS_BRG3 0x00000200 /* SCC3 Tx Clock Source is BRG3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) #define CMXSCR_TS3CS_BRG4 0x00000300 /* SCC3 Tx Clock Source is BRG4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) #define CMXSCR_TS3CS_CLK5 0x00000400 /* SCC3 Tx Clock Source is CLK5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) #define CMXSCR_TS3CS_CLK6 0x00000500 /* SCC3 Tx Clock Source is CLK6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) #define CMXSCR_TS3CS_CLK7 0x00000600 /* SCC3 Tx Clock Source is CLK7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) #define CMXSCR_TS3CS_CLK8 0x00000700 /* SCC3 Tx Clock Source is CLK8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) #define CMXSCR_RS4CS_BRG1 0x00000000 /* SCC4 Rx Clock Source is BRG1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) #define CMXSCR_RS4CS_BRG2 0x00000008 /* SCC4 Rx Clock Source is BRG2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) #define CMXSCR_RS4CS_BRG3 0x00000010 /* SCC4 Rx Clock Source is BRG3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) #define CMXSCR_RS4CS_BRG4 0x00000018 /* SCC4 Rx Clock Source is BRG4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) #define CMXSCR_RS4CS_CLK5 0x00000020 /* SCC4 Rx Clock Source is CLK5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) #define CMXSCR_RS4CS_CLK6 0x00000028 /* SCC4 Rx Clock Source is CLK6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) #define CMXSCR_RS4CS_CLK7 0x00000030 /* SCC4 Rx Clock Source is CLK7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) #define CMXSCR_RS4CS_CLK8 0x00000038 /* SCC4 Rx Clock Source is CLK8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) #define CMXSCR_TS4CS_BRG1 0x00000000 /* SCC4 Tx Clock Source is BRG1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) #define CMXSCR_TS4CS_BRG2 0x00000001 /* SCC4 Tx Clock Source is BRG2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) #define CMXSCR_TS4CS_BRG3 0x00000002 /* SCC4 Tx Clock Source is BRG3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) #define CMXSCR_TS4CS_BRG4 0x00000003 /* SCC4 Tx Clock Source is BRG4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) #define CMXSCR_TS4CS_CLK5 0x00000004 /* SCC4 Tx Clock Source is CLK5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) #define CMXSCR_TS4CS_CLK6 0x00000005 /* SCC4 Tx Clock Source is CLK6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) #define CMXSCR_TS4CS_CLK7 0x00000006 /* SCC4 Tx Clock Source is CLK7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) #define CMXSCR_TS4CS_CLK8 0x00000007 /* SCC4 Tx Clock Source is CLK8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) /*-----------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) * SIUMCR - SIU Module Configuration Register 4-31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) #define SIUMCR_BBD 0x80000000 /* Bus Busy Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) #define SIUMCR_ESE 0x40000000 /* External Snoop Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) #define SIUMCR_PBSE 0x20000000 /* Parity Byte Select Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) #define SIUMCR_CDIS 0x10000000 /* Core Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) #define SIUMCR_DPPC00 0x00000000 /* Data Parity Pins Configuration*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) #define SIUMCR_DPPC01 0x04000000 /* - " - */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) #define SIUMCR_DPPC10 0x08000000 /* - " - */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) #define SIUMCR_DPPC11 0x0c000000 /* - " - */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) #define SIUMCR_L2CPC00 0x00000000 /* L2 Cache Pins Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) #define SIUMCR_L2CPC01 0x01000000 /* - " - */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) #define SIUMCR_L2CPC10 0x02000000 /* - " - */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) #define SIUMCR_L2CPC11 0x03000000 /* - " - */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) #define SIUMCR_LBPC00 0x00000000 /* Local Bus Pins Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) #define SIUMCR_LBPC01 0x00400000 /* - " - */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) #define SIUMCR_LBPC10 0x00800000 /* - " - */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) #define SIUMCR_LBPC11 0x00c00000 /* - " - */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) #define SIUMCR_APPC00 0x00000000 /* Address Parity Pins Configuration*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) #define SIUMCR_APPC01 0x00100000 /* - " - */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) #define SIUMCR_APPC10 0x00200000 /* - " - */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) #define SIUMCR_APPC11 0x00300000 /* - " - */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) #define SIUMCR_CS10PC00 0x00000000 /* CS10 Pin Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) #define SIUMCR_CS10PC01 0x00040000 /* - " - */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) #define SIUMCR_CS10PC10 0x00080000 /* - " - */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) #define SIUMCR_CS10PC11 0x000c0000 /* - " - */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) #define SIUMCR_BCTLC00 0x00000000 /* Buffer Control Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) #define SIUMCR_BCTLC01 0x00010000 /* - " - */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) #define SIUMCR_BCTLC10 0x00020000 /* - " - */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) #define SIUMCR_BCTLC11 0x00030000 /* - " - */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) #define SIUMCR_MMR00 0x00000000 /* Mask Masters Requests */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) #define SIUMCR_MMR01 0x00004000 /* - " - */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) #define SIUMCR_MMR10 0x00008000 /* - " - */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) #define SIUMCR_MMR11 0x0000c000 /* - " - */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) #define SIUMCR_LPBSE 0x00002000 /* LocalBus Parity Byte Select Enable*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) /*-----------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) * SCCR - System Clock Control Register 9-8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) #define SCCR_PCI_MODE 0x00000100 /* PCI Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) #define SCCR_PCI_MODCK 0x00000080 /* Value of PCI_MODCK pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) #define SCCR_PCIDF_MSK 0x00000078 /* PCI division factor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) #define SCCR_PCIDF_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) #ifndef CPM_IMMR_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) #define CPM_IMMR_OFFSET 0x101a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) #define FCC_PSMR_RMII ((uint)0x00020000) /* Use RMII interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) /* FCC iop & clock configuration. BSP code is responsible to define Fx_RXCLK & Fx_TXCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) * in order to use clock-computing stuff below for the FCC x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) /* Automatically generates register configurations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) #define PC_CLK(x) ((uint)(1<<(x-1))) /* FCC CLK I/O ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) #define CMXFCR_RF1CS(x) ((uint)((x-5)<<27)) /* FCC1 Receive Clock Source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) #define CMXFCR_TF1CS(x) ((uint)((x-5)<<24)) /* FCC1 Transmit Clock Source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) #define CMXFCR_RF2CS(x) ((uint)((x-9)<<19)) /* FCC2 Receive Clock Source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) #define CMXFCR_TF2CS(x) ((uint)((x-9)<<16)) /* FCC2 Transmit Clock Source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) #define CMXFCR_RF3CS(x) ((uint)((x-9)<<11)) /* FCC3 Receive Clock Source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) #define CMXFCR_TF3CS(x) ((uint)((x-9)<<8)) /* FCC3 Transmit Clock Source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) #define PC_F1RXCLK PC_CLK(F1_RXCLK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) #define PC_F1TXCLK PC_CLK(F1_TXCLK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) #define CMX1_CLK_ROUTE (CMXFCR_RF1CS(F1_RXCLK) | CMXFCR_TF1CS(F1_TXCLK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) #define CMX1_CLK_MASK ((uint)0xff000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) #define PC_F2RXCLK PC_CLK(F2_RXCLK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) #define PC_F2TXCLK PC_CLK(F2_TXCLK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) #define CMX2_CLK_ROUTE (CMXFCR_RF2CS(F2_RXCLK) | CMXFCR_TF2CS(F2_TXCLK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) #define CMX2_CLK_MASK ((uint)0x00ff0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) #define PC_F3RXCLK PC_CLK(F3_RXCLK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) #define PC_F3TXCLK PC_CLK(F3_TXCLK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) #define CMX3_CLK_ROUTE (CMXFCR_RF3CS(F3_RXCLK) | CMXFCR_TF3CS(F3_TXCLK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) #define CMX3_CLK_MASK ((uint)0x0000ff00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) #define CPMUX_CLK_MASK (CMX3_CLK_MASK | CMX2_CLK_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) #define CPMUX_CLK_ROUTE (CMX3_CLK_ROUTE | CMX2_CLK_ROUTE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) #define CLK_TRX (PC_F3TXCLK | PC_F3RXCLK | PC_F2TXCLK | PC_F2RXCLK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) /* I/O Pin assignment for FCC1. I don't yet know the best way to do this,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) * but there is little variation among the choices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) #define PA1_COL 0x00000001U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) #define PA1_CRS 0x00000002U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) #define PA1_TXER 0x00000004U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) #define PA1_TXEN 0x00000008U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) #define PA1_RXDV 0x00000010U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) #define PA1_RXER 0x00000020U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) #define PA1_TXDAT 0x00003c00U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) #define PA1_RXDAT 0x0003c000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) #define PA1_PSORA0 (PA1_RXDAT | PA1_TXDAT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) #define PA1_PSORA1 (PA1_COL | PA1_CRS | PA1_TXER | PA1_TXEN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) PA1_RXDV | PA1_RXER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) #define PA1_DIRA0 (PA1_RXDAT | PA1_CRS | PA1_COL | PA1_RXER | PA1_RXDV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) #define PA1_DIRA1 (PA1_TXDAT | PA1_TXEN | PA1_TXER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) /* I/O Pin assignment for FCC2. I don't yet know the best way to do this,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) * but there is little variation among the choices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) #define PB2_TXER 0x00000001U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) #define PB2_RXDV 0x00000002U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) #define PB2_TXEN 0x00000004U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) #define PB2_RXER 0x00000008U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) #define PB2_COL 0x00000010U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) #define PB2_CRS 0x00000020U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) #define PB2_TXDAT 0x000003c0U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) #define PB2_RXDAT 0x00003c00U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) #define PB2_PSORB0 (PB2_RXDAT | PB2_TXDAT | PB2_CRS | PB2_COL | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) PB2_RXER | PB2_RXDV | PB2_TXER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) #define PB2_PSORB1 (PB2_TXEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) #define PB2_DIRB0 (PB2_RXDAT | PB2_CRS | PB2_COL | PB2_RXER | PB2_RXDV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) #define PB2_DIRB1 (PB2_TXDAT | PB2_TXEN | PB2_TXER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) /* I/O Pin assignment for FCC3. I don't yet know the best way to do this,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) * but there is little variation among the choices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) #define PB3_RXDV 0x00004000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) #define PB3_RXER 0x00008000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) #define PB3_TXER 0x00010000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) #define PB3_TXEN 0x00020000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) #define PB3_COL 0x00040000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) #define PB3_CRS 0x00080000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) #define PB3_TXDAT 0x0f000000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) #define PC3_TXDAT 0x00000010U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) #define PB3_RXDAT 0x00f00000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) #define PB3_PSORB0 (PB3_RXDAT | PB3_TXDAT | PB3_CRS | PB3_COL | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) PB3_RXER | PB3_RXDV | PB3_TXER | PB3_TXEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) #define PB3_PSORB1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) #define PB3_DIRB0 (PB3_RXDAT | PB3_CRS | PB3_COL | PB3_RXER | PB3_RXDV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) #define PB3_DIRB1 (PB3_TXDAT | PB3_TXEN | PB3_TXER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) #define PC3_DIRC1 (PC3_TXDAT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) /* Handy macro to specify mem for FCCs*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) #define FCC_MEM_OFFSET(x) (CPM_FCC_SPECIAL_BASE + (x*128))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) #define FCC1_MEM_OFFSET FCC_MEM_OFFSET(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) #define FCC2_MEM_OFFSET FCC_MEM_OFFSET(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) #define FCC3_MEM_OFFSET FCC_MEM_OFFSET(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) /* Clocks and GRG's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) enum cpm_clk_dir {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) CPM_CLK_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) CPM_CLK_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) CPM_CLK_RTX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) enum cpm_clk_target {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) CPM_CLK_SCC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) CPM_CLK_SCC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) CPM_CLK_SCC3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) CPM_CLK_SCC4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) CPM_CLK_FCC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) CPM_CLK_FCC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) CPM_CLK_FCC3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) CPM_CLK_SMC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) CPM_CLK_SMC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) enum cpm_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) CPM_CLK_NONE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) CPM_BRG1, /* Baud Rate Generator 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) CPM_BRG2, /* Baud Rate Generator 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) CPM_BRG3, /* Baud Rate Generator 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) CPM_BRG4, /* Baud Rate Generator 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) CPM_BRG5, /* Baud Rate Generator 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) CPM_BRG6, /* Baud Rate Generator 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) CPM_BRG7, /* Baud Rate Generator 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) CPM_BRG8, /* Baud Rate Generator 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) CPM_CLK1, /* Clock 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) CPM_CLK2, /* Clock 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) CPM_CLK3, /* Clock 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) CPM_CLK4, /* Clock 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) CPM_CLK5, /* Clock 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) CPM_CLK6, /* Clock 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) CPM_CLK7, /* Clock 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) CPM_CLK8, /* Clock 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) CPM_CLK9, /* Clock 9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) CPM_CLK10, /* Clock 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) CPM_CLK11, /* Clock 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) CPM_CLK12, /* Clock 12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) CPM_CLK13, /* Clock 13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) CPM_CLK14, /* Clock 14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) CPM_CLK15, /* Clock 15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) CPM_CLK16, /* Clock 16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) CPM_CLK17, /* Clock 17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) CPM_CLK18, /* Clock 18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) CPM_CLK19, /* Clock 19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) CPM_CLK20, /* Clock 20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) CPM_CLK_DUMMY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) extern int cpm2_clk_setup(enum cpm_clk_target target, int clock, int mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) extern int cpm2_smc_clk_setup(enum cpm_clk_target target, int clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) #define CPM_PIN_INPUT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) #define CPM_PIN_OUTPUT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) #define CPM_PIN_PRIMARY 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) #define CPM_PIN_SECONDARY 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) #define CPM_PIN_GPIO 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) #define CPM_PIN_OPENDRAIN 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) void cpm2_set_pin(int port, int pin, int flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) #endif /* __CPM2__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) #endif /* __KERNEL__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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