^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * MPC8xx Communication Processor Module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This file contains structures and information for the communication
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * processor channels. Some CPM control and status is available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * through the MPC8xx internal memory map. See immap.h for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * This file only contains what I need for the moment, not the total
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * CPM capabilities. I (or someone else) will add definitions as they
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * are needed. -- Dan
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * On the MBX board, EPPC-Bug loads CPM microcode into the first 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * bytes of the DP RAM and relocates the I2C parameter area to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * IDMA1 space. The remaining DP RAM is available for buffer descriptors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * or other use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #ifndef __CPM1__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define __CPM1__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/8xx_immap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/cpm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* CPM Command register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CPM_CR_RST ((ushort)0x8000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CPM_CR_OPCODE ((ushort)0x0f00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CPM_CR_CHAN ((ushort)0x00f0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CPM_CR_FLG ((ushort)0x0001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* Channel numbers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CPM_CR_CH_SCC1 ((ushort)0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CPM_CR_CH_I2C ((ushort)0x0001) /* I2C and IDMA1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CPM_CR_CH_SCC2 ((ushort)0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CPM_CR_CH_SPI ((ushort)0x0005) /* SPI / IDMA2 / Timers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CPM_CR_CH_TIMER CPM_CR_CH_SPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CPM_CR_CH_SCC3 ((ushort)0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CPM_CR_CH_SMC1 ((ushort)0x0009) /* SMC1 / DSP1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CPM_CR_CH_SCC4 ((ushort)0x000c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CPM_CR_CH_SMC2 ((ushort)0x000d) /* SMC2 / DSP2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define mk_cr_cmd(CH, CMD) ((CMD << 8) | (CH << 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* Export the base address of the communication processor registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * and dual port ram.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) extern cpm8xx_t __iomem *cpmp; /* Pointer to comm processor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define cpm_dpalloc cpm_muram_alloc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define cpm_dpfree cpm_muram_free
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define cpm_dpram_addr cpm_muram_addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define cpm_dpram_phys cpm_muram_dma
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) extern void cpm_setbrg(uint brg, uint rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) extern void __init cpm_load_patch(cpm8xx_t *cp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) extern void cpm_reset(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* Parameter RAM offsets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define PROFF_SCC1 ((uint)0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define PROFF_IIC ((uint)0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PROFF_SCC2 ((uint)0x0100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PROFF_SPI ((uint)0x0180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define PROFF_SCC3 ((uint)0x0200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define PROFF_SMC1 ((uint)0x0280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define PROFF_DSP1 ((uint)0x02c0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define PROFF_SCC4 ((uint)0x0300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define PROFF_SMC2 ((uint)0x0380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* Define enough so I can at least use the serial port as a UART.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * The MBX uses SMC1 as the host serial port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) typedef struct smc_uart {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) ushort smc_rbase; /* Rx Buffer descriptor base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) ushort smc_tbase; /* Tx Buffer descriptor base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u_char smc_rfcr; /* Rx function code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u_char smc_tfcr; /* Tx function code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) ushort smc_mrblr; /* Max receive buffer length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) uint smc_rstate; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) uint smc_idp; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) ushort smc_rbptr; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) ushort smc_ibc; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) uint smc_rxtmp; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) uint smc_tstate; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) uint smc_tdp; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) ushort smc_tbptr; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) ushort smc_tbc; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) uint smc_txtmp; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) ushort smc_maxidl; /* Maximum idle characters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) ushort smc_tmpidl; /* Temporary idle counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) ushort smc_brklen; /* Last received break length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) ushort smc_brkec; /* rcv'd break condition counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) ushort smc_brkcr; /* xmt break count register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) ushort smc_rmask; /* Temporary bit mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) char res1[8]; /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) ushort smc_rpbase; /* Relocation pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) } smc_uart_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* Function code bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SMC_EB ((u_char)0x10) /* Set big endian byte order */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* SMC uart mode register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SMCMR_REN ((ushort)0x0001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define SMCMR_TEN ((ushort)0x0002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SMCMR_DM ((ushort)0x000c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SMCMR_SM_GCI ((ushort)0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SMCMR_SM_UART ((ushort)0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SMCMR_SM_TRANS ((ushort)0x0030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define SMCMR_SM_MASK ((ushort)0x0030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SMCMR_REVD SMCMR_PM_EVEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define SMCMR_PEN ((ushort)0x0200) /* Parity enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SMCMR_BS SMCMR_PEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* SMC2 as Centronics parallel printer. It is half duplex, in that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * it can only receive or transmit. The parameter ram values for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * each direction are either unique or properly overlap, so we can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * include them in one structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) typedef struct smc_centronics {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) ushort scent_rbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) ushort scent_tbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u_char scent_cfcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u_char scent_smask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) ushort scent_mrblr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) uint scent_rstate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) uint scent_r_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) ushort scent_rbptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) ushort scent_r_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) uint scent_rtemp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) uint scent_tstate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) uint scent_t_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) ushort scent_tbptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) ushort scent_t_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) uint scent_ttemp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) ushort scent_max_sl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) ushort scent_sl_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) ushort scent_character1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) ushort scent_character2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) ushort scent_character3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) ushort scent_character4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) ushort scent_character5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) ushort scent_character6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) ushort scent_character7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) ushort scent_character8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) ushort scent_rccm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) ushort scent_rccr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) } smc_cent_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* Centronics Status Mask Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define SMC_CENT_F ((u_char)0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define SMC_CENT_PE ((u_char)0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define SMC_CENT_S ((u_char)0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* SMC Event and Mask register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define SMCM_TXE ((unsigned char)0x10) /* When in Transparent Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define SMCM_BSY ((unsigned char)0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define SMCM_TX ((unsigned char)0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define SMCM_RX ((unsigned char)0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* Baud rate generators.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define CPM_BRG_RST ((uint)0x00020000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define CPM_BRG_EN ((uint)0x00010000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define CPM_BRG_EXTC_INT ((uint)0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define CPM_BRG_EXTC_CLK2 ((uint)0x00004000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define CPM_BRG_EXTC_CLK6 ((uint)0x00008000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define CPM_BRG_ATB ((uint)0x00002000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define CPM_BRG_CD_MASK ((uint)0x00001ffe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define CPM_BRG_DIV16 ((uint)0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* SI Clock Route Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define SICR_RCLK_SCC1_BRG1 ((uint)0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define SICR_TCLK_SCC1_BRG1 ((uint)0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define SICR_RCLK_SCC2_BRG2 ((uint)0x00000800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define SICR_TCLK_SCC2_BRG2 ((uint)0x00000100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define SICR_RCLK_SCC3_BRG3 ((uint)0x00100000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define SICR_TCLK_SCC3_BRG3 ((uint)0x00020000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define SICR_RCLK_SCC4_BRG4 ((uint)0x18000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define SICR_TCLK_SCC4_BRG4 ((uint)0x03000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* SCCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define SCC_GSMRH_IRP ((uint)0x00040000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define SCC_GSMRH_GDE ((uint)0x00010000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define SCC_GSMRH_REVD ((uint)0x00002000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define SCC_GSMRH_TRX ((uint)0x00001000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define SCC_GSMRH_TTX ((uint)0x00000800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define SCC_GSMRH_CDP ((uint)0x00000400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define SCC_GSMRH_CTSP ((uint)0x00000200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define SCC_GSMRH_CDS ((uint)0x00000100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define SCC_GSMRH_CTSS ((uint)0x00000080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define SCC_GSMRH_TFL ((uint)0x00000040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define SCC_GSMRH_RFW ((uint)0x00000020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define SCC_GSMRH_TXSY ((uint)0x00000010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define SCC_GSMRH_SYNL16 ((uint)0x0000000c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define SCC_GSMRH_SYNL8 ((uint)0x00000008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define SCC_GSMRH_SYNL4 ((uint)0x00000004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define SCC_GSMRH_RTSM ((uint)0x00000002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define SCC_GSMRH_RSYN ((uint)0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define SCC_GSMRL_EDGE_NONE ((uint)0x60000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define SCC_GSMRL_EDGE_NEG ((uint)0x40000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define SCC_GSMRL_EDGE_POS ((uint)0x20000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define SCC_GSMRL_TCI ((uint)0x10000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define SCC_GSMRL_TSNC_3 ((uint)0x0c000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define SCC_GSMRL_TSNC_4 ((uint)0x08000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define SCC_GSMRL_TSNC_14 ((uint)0x04000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define SCC_GSMRL_TSNC_INF ((uint)0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define SCC_GSMRL_RINV ((uint)0x02000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define SCC_GSMRL_TINV ((uint)0x01000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define SCC_GSMRL_TPL_128 ((uint)0x00c00000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define SCC_GSMRL_TPL_64 ((uint)0x00a00000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define SCC_GSMRL_TPL_48 ((uint)0x00800000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define SCC_GSMRL_TPL_32 ((uint)0x00600000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define SCC_GSMRL_TPL_16 ((uint)0x00400000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define SCC_GSMRL_TPL_8 ((uint)0x00200000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define SCC_GSMRL_TPL_NONE ((uint)0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define SCC_GSMRL_TPP_01 ((uint)0x00100000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define SCC_GSMRL_TPP_10 ((uint)0x00080000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define SCC_GSMRL_TEND ((uint)0x00040000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define SCC_GSMRL_TDCR_32 ((uint)0x00030000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define SCC_GSMRL_TDCR_16 ((uint)0x00020000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define SCC_GSMRL_TDCR_8 ((uint)0x00010000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define SCC_GSMRL_TDCR_1 ((uint)0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define SCC_GSMRL_RDCR_32 ((uint)0x0000c000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define SCC_GSMRL_RDCR_16 ((uint)0x00008000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define SCC_GSMRL_RDCR_8 ((uint)0x00004000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define SCC_GSMRL_RDCR_1 ((uint)0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define SCC_GSMRL_RENC_MANCH ((uint)0x00002000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define SCC_GSMRL_RENC_FM0 ((uint)0x00001000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define SCC_GSMRL_RENC_NRZI ((uint)0x00000800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define SCC_GSMRL_RENC_NRZ ((uint)0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define SCC_GSMRL_TENC_MANCH ((uint)0x00000400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define SCC_GSMRL_TENC_FM0 ((uint)0x00000200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define SCC_GSMRL_TENC_NRZI ((uint)0x00000100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define SCC_GSMRL_TENC_NRZ ((uint)0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define SCC_GSMRL_DIAG_NORM ((uint)0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define SCC_GSMRL_ENR ((uint)0x00000020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define SCC_GSMRL_ENT ((uint)0x00000010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define SCC_GSMRL_MODE_ENET ((uint)0x0000000c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define SCC_GSMRL_MODE_QMC ((uint)0x0000000a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define SCC_GSMRL_MODE_V14 ((uint)0x00000007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define SCC_GSMRL_MODE_UART ((uint)0x00000004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define SCC_GSMRL_MODE_SS7 ((uint)0x00000003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define SCC_GSMRL_MODE_ATALK ((uint)0x00000002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define SCC_GSMRL_MODE_HDLC ((uint)0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define SCC_TODR_TOD ((ushort)0x8000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* SCC Event and Mask register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define SCCM_TXE ((unsigned char)0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define SCCM_BSY ((unsigned char)0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define SCCM_TX ((unsigned char)0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define SCCM_RX ((unsigned char)0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) typedef struct scc_param {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) ushort scc_rbase; /* Rx Buffer descriptor base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) ushort scc_tbase; /* Tx Buffer descriptor base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) u_char scc_rfcr; /* Rx function code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) u_char scc_tfcr; /* Tx function code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) ushort scc_mrblr; /* Max receive buffer length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) uint scc_rstate; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) uint scc_idp; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) ushort scc_rbptr; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) ushort scc_ibc; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) uint scc_rxtmp; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) uint scc_tstate; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) uint scc_tdp; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) ushort scc_tbptr; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) ushort scc_tbc; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) uint scc_txtmp; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) uint scc_rcrc; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) uint scc_tcrc; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) } sccp_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /* Function code bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define SCC_EB ((u_char)0x10) /* Set big endian byte order */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* CPM Ethernet through SCCx.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) typedef struct scc_enet {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) sccp_t sen_genscc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) uint sen_cpres; /* Preset CRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) uint sen_cmask; /* Constant mask for CRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) uint sen_crcec; /* CRC Error counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) uint sen_alec; /* alignment error counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) uint sen_disfc; /* discard frame counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) ushort sen_pads; /* Tx short frame pad character */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) ushort sen_retlim; /* Retry limit threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) ushort sen_retcnt; /* Retry limit counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) ushort sen_maxflr; /* maximum frame length register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) ushort sen_minflr; /* minimum frame length register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) ushort sen_maxd1; /* maximum DMA1 length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) ushort sen_maxd2; /* maximum DMA2 length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) ushort sen_maxd; /* Rx max DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) ushort sen_dmacnt; /* Rx DMA counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) ushort sen_maxb; /* Max BD byte count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) ushort sen_gaddr1; /* Group address filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) ushort sen_gaddr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) ushort sen_gaddr3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) ushort sen_gaddr4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) uint sen_tbuf0data0; /* Save area 0 - current frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) uint sen_tbuf0data1; /* Save area 1 - current frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) uint sen_tbuf0rba; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) uint sen_tbuf0crc; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) ushort sen_tbuf0bcnt; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) ushort sen_paddrh; /* physical address (MSB) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) ushort sen_paddrm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) ushort sen_paddrl; /* physical address (LSB) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) ushort sen_pper; /* persistence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) ushort sen_rfbdptr; /* Rx first BD pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) ushort sen_tfbdptr; /* Tx first BD pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) ushort sen_tlbdptr; /* Tx last BD pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) uint sen_tbuf1data0; /* Save area 0 - current frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) uint sen_tbuf1data1; /* Save area 1 - current frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) uint sen_tbuf1rba; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) uint sen_tbuf1crc; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) ushort sen_tbuf1bcnt; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) ushort sen_txlen; /* Tx Frame length counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) ushort sen_iaddr1; /* Individual address filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) ushort sen_iaddr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) ushort sen_iaddr3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) ushort sen_iaddr4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) ushort sen_boffcnt; /* Backoff counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /* NOTE: Some versions of the manual have the following items
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * incorrectly documented. Below is the proper order.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) ushort sen_taddrh; /* temp address (MSB) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) ushort sen_taddrm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) ushort sen_taddrl; /* temp address (LSB) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) } scc_enet_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /* SCC Event register as used by Ethernet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /* SCC Mode Register (PMSR) as used by Ethernet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /* SCC as UART
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) typedef struct scc_uart {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) sccp_t scc_genscc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) char res1[8]; /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) ushort scc_maxidl; /* Maximum idle chars */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) ushort scc_idlc; /* temp idle counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) ushort scc_brkcr; /* Break count register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) ushort scc_parec; /* receive parity error counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) ushort scc_frmec; /* receive framing error counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) ushort scc_nosec; /* receive noise counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) ushort scc_brkec; /* receive break condition counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) ushort scc_brkln; /* last received break length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) ushort scc_uaddr1; /* UART address character 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) ushort scc_uaddr2; /* UART address character 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) ushort scc_rtemp; /* Temp storage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) ushort scc_toseq; /* Transmit out of sequence char */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) ushort scc_char1; /* control character 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) ushort scc_char2; /* control character 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) ushort scc_char3; /* control character 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) ushort scc_char4; /* control character 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) ushort scc_char5; /* control character 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) ushort scc_char6; /* control character 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) ushort scc_char7; /* control character 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) ushort scc_char8; /* control character 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) ushort scc_rccm; /* receive control character mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) ushort scc_rccr; /* receive control character register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) ushort scc_rlbc; /* receive last break character */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) } scc_uart_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) /* SCC Event and Mask registers when it is used as a UART.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define UART_SCCM_GLR ((ushort)0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define UART_SCCM_GLT ((ushort)0x0800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define UART_SCCM_AB ((ushort)0x0200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define UART_SCCM_IDL ((ushort)0x0100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define UART_SCCM_GRA ((ushort)0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define UART_SCCM_BRKE ((ushort)0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define UART_SCCM_BRKS ((ushort)0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define UART_SCCM_CCR ((ushort)0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define UART_SCCM_BSY ((ushort)0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define UART_SCCM_TX ((ushort)0x0002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define UART_SCCM_RX ((ushort)0x0001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /* The SCC PMSR when used as a UART.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define SCU_PSMR_FLC ((ushort)0x8000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define SCU_PSMR_SL ((ushort)0x4000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define SCU_PSMR_CL ((ushort)0x3000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define SCU_PSMR_UM ((ushort)0x0c00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define SCU_PSMR_FRZ ((ushort)0x0200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define SCU_PSMR_RZS ((ushort)0x0100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define SCU_PSMR_SYN ((ushort)0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define SCU_PSMR_DRT ((ushort)0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define SCU_PSMR_PEN ((ushort)0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define SCU_PSMR_RPM ((ushort)0x000c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define SCU_PSMR_REVP ((ushort)0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define SCU_PSMR_TPM ((ushort)0x0003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define SCU_PSMR_TEVP ((ushort)0x0002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /* CPM Transparent mode SCC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) typedef struct scc_trans {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) sccp_t st_genscc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) uint st_cpres; /* Preset CRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) uint st_cmask; /* Constant mask for CRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) } scc_trans_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) /* IIC parameter RAM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) typedef struct iic {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) ushort iic_rbase; /* Rx Buffer descriptor base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) ushort iic_tbase; /* Tx Buffer descriptor base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) u_char iic_rfcr; /* Rx function code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) u_char iic_tfcr; /* Tx function code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) ushort iic_mrblr; /* Max receive buffer length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) uint iic_rstate; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) uint iic_rdp; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) ushort iic_rbptr; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) ushort iic_rbc; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) uint iic_rxtmp; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) uint iic_tstate; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) uint iic_tdp; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) ushort iic_tbptr; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) ushort iic_tbc; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) uint iic_txtmp; /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) char res1[4]; /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) ushort iic_rpbase; /* Relocation pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) char res2[2]; /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) } iic_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) * RISC Controller Configuration Register definitons
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define RCCR_TIME 0x8000 /* RISC Timer Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define RCCR_TIMEP(t) (((t) & 0x3F)<<8) /* RISC Timer Period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define RCCR_TIME_MASK 0x00FF /* not RISC Timer related bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /* RISC Timer Parameter RAM offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define PROFF_RTMR ((uint)0x01B0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) typedef struct risc_timer_pram {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) unsigned short tm_base; /* RISC Timer Table Base Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) unsigned short tm_ptr; /* RISC Timer Table Pointer (internal) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) unsigned short r_tmr; /* RISC Timer Mode Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) unsigned short r_tmv; /* RISC Timer Valid Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) unsigned long tm_cmd; /* RISC Timer Command Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) unsigned long tm_cnt; /* RISC Timer Internal Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) } rt_pram_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) /* Bits in RISC Timer Command Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define TM_CMD_VALID 0x80000000 /* Valid - Enables the timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define TM_CMD_RESTART 0x40000000 /* Restart - for automatic restart */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define TM_CMD_PWM 0x20000000 /* Run in Pulse Width Modulation Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define TM_CMD_NUM(n) (((n)&0xF)<<16) /* Timer Number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define TM_CMD_PERIOD(p) ((p)&0xFFFF) /* Timer Period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) /* CPM interrupts. There are nearly 32 interrupts generated by CPM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) * channels or devices. All of these are presented to the PPC core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) * as a single interrupt. The CPM interrupt handler dispatches its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) * own handlers, in a similar fashion to the PPC core handler. We
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) * use the table as defined in the manuals (i.e. no special high
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) * priority and SCC1 == SCCa, etc...).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define CPMVEC_NR 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define CPMVEC_PIO_PC15 ((ushort)0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define CPMVEC_SCC1 ((ushort)0x1e)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define CPMVEC_SCC2 ((ushort)0x1d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define CPMVEC_SCC3 ((ushort)0x1c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define CPMVEC_SCC4 ((ushort)0x1b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define CPMVEC_PIO_PC14 ((ushort)0x1a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define CPMVEC_TIMER1 ((ushort)0x19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define CPMVEC_PIO_PC13 ((ushort)0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define CPMVEC_PIO_PC12 ((ushort)0x17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define CPMVEC_SDMA_CB_ERR ((ushort)0x16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define CPMVEC_IDMA1 ((ushort)0x15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define CPMVEC_IDMA2 ((ushort)0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define CPMVEC_TIMER2 ((ushort)0x12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define CPMVEC_RISCTIMER ((ushort)0x11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define CPMVEC_I2C ((ushort)0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define CPMVEC_PIO_PC11 ((ushort)0x0f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define CPMVEC_PIO_PC10 ((ushort)0x0e)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define CPMVEC_TIMER3 ((ushort)0x0c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define CPMVEC_PIO_PC9 ((ushort)0x0b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define CPMVEC_PIO_PC8 ((ushort)0x0a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define CPMVEC_PIO_PC7 ((ushort)0x09)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define CPMVEC_TIMER4 ((ushort)0x07)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define CPMVEC_PIO_PC6 ((ushort)0x06)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define CPMVEC_SPI ((ushort)0x05)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define CPMVEC_SMC1 ((ushort)0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define CPMVEC_SMC2 ((ushort)0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define CPMVEC_PIO_PC5 ((ushort)0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define CPMVEC_PIO_PC4 ((ushort)0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define CPMVEC_ERROR ((ushort)0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) /* CPM interrupt configuration vector.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define CICR_IEN ((uint)0x00000080) /* Int. enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define CICR_SPS ((uint)0x00000001) /* SCC Spread */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define CPM_PIN_INPUT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define CPM_PIN_OUTPUT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define CPM_PIN_PRIMARY 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define CPM_PIN_SECONDARY 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define CPM_PIN_GPIO 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define CPM_PIN_OPENDRAIN 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define CPM_PIN_FALLEDGE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define CPM_PIN_ANYEDGE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) enum cpm_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) CPM_PORTA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) CPM_PORTB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) CPM_PORTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) CPM_PORTD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) CPM_PORTE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) void cpm1_set_pin(enum cpm_port port, int pin, int flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) enum cpm_clk_dir {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) CPM_CLK_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) CPM_CLK_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) CPM_CLK_RTX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) enum cpm_clk_target {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) CPM_CLK_SCC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) CPM_CLK_SCC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) CPM_CLK_SCC3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) CPM_CLK_SCC4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) CPM_CLK_SMC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) CPM_CLK_SMC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) enum cpm_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) CPM_BRG1, /* Baud Rate Generator 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) CPM_BRG2, /* Baud Rate Generator 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) CPM_BRG3, /* Baud Rate Generator 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) CPM_BRG4, /* Baud Rate Generator 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) CPM_CLK1, /* Clock 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) CPM_CLK2, /* Clock 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) CPM_CLK3, /* Clock 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) CPM_CLK4, /* Clock 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) CPM_CLK5, /* Clock 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) CPM_CLK6, /* Clock 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) CPM_CLK7, /* Clock 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) CPM_CLK8, /* Clock 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) int cpm1_clk_setup(enum cpm_clk_target target, int clock, int mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) int cpm1_gpiochip_add16(struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) int cpm1_gpiochip_add32(struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #endif /* __CPM1__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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